1 /***************************************************************************/
4 * linux/arch/m68knommu/platform/5307/config.c
6 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
7 * Copyright (C) 2000, Lineo (www.lineo.com)
10 /***************************************************************************/
12 #include <linux/kernel.h>
13 #include <linux/param.h>
14 #include <linux/init.h>
16 #include <asm/machdep.h>
17 #include <asm/coldfire.h>
18 #include <asm/mcfsim.h>
19 #include <asm/mcfuart.h>
20 #include <asm/mcfwdebug.h>
22 /***************************************************************************/
24 extern unsigned int mcf_timervector;
25 extern unsigned int mcf_profilevector;
26 extern unsigned int mcf_timerlevel;
28 /***************************************************************************/
31 * Some platforms need software versions of the GPIO data registers.
33 unsigned short ppdata;
34 unsigned char ledbank = 0xff;
36 /***************************************************************************/
38 static struct mcf_platform_uart m5307_uart_platform[] = {
40 .mapbase = MCF_MBAR + MCFUART_BASE1,
44 .mapbase = MCF_MBAR + MCFUART_BASE2,
50 static struct platform_device m5307_uart = {
53 .dev.platform_data = m5307_uart_platform,
56 static struct platform_device *m5307_devices[] __initdata = {
60 /***************************************************************************/
62 static void __init m5307_uart_init_line(int line, int irq)
65 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
66 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
67 mcf_clrimr(MCFINTC_UART0);
68 } else if (line == 1) {
69 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
70 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
71 mcf_clrimr(MCFINTC_UART1);
75 static void __init m5307_uarts_init(void)
77 const int nrlines = ARRAY_SIZE(m5307_uart_platform);
80 for (line = 0; (line < nrlines); line++)
81 m5307_uart_init_line(line, m5307_uart_platform[line].irq);
84 /***************************************************************************/
86 void mcf_settimericr(unsigned int timer, unsigned int level)
88 volatile unsigned char *icrp;
89 unsigned int icr, imr;
93 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break;
94 default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break;
97 icrp = (volatile unsigned char *) (MCF_MBAR + icr);
98 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
103 /***************************************************************************/
105 void m5307_cpu_reset(void)
108 /* Set watchdog to soft reset, and enabled */
109 __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
111 /* wait for watchdog to timeout */;
114 /***************************************************************************/
116 void __init config_BSP(char *commandp, int size)
118 #if defined(CONFIG_NETtel) || \
119 defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA)
120 /* Copy command line from FLASH to local buffer... */
121 memcpy(commandp, (char *) 0xf0004000, size);
122 commandp[size-1] = 0;
123 /* Different timer setup - to prevent device clash */
124 mcf_timervector = 30;
125 mcf_profilevector = 31;
129 mach_reset = m5307_cpu_reset;
131 #ifdef CONFIG_BDM_DISABLE
133 * Disable the BDM clocking. This also turns off most of the rest of
134 * the BDM device. This is good for EMC reasons. This option is not
135 * incompatible with the memory protection option.
137 wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
141 /***************************************************************************/
143 static int __init init_BSP(void)
146 platform_add_devices(m5307_devices, ARRAY_SIZE(m5307_devices));
150 arch_initcall(init_BSP);
152 /***************************************************************************/