4 * Interrupt controller code for the ColdFire 5208, 5207 & 532x parts.
6 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file COPYING in the main directory of this archive
13 #include <linux/types.h>
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
19 #include <asm/coldfire.h>
20 #include <asm/mcfsim.h>
21 #include <asm/traps.h>
23 static void intc_irq_mask(unsigned int irq)
25 if (irq >= MCFINT_VECBASE) {
26 if (irq < MCFINT_VECBASE + 64)
27 __raw_writeb(irq - MCFINT_VECBASE, MCFINTC0_SIMR);
28 else if ((irq < MCFINT_VECBASE + 128) && MCFINTC1_SIMR)
29 __raw_writeb(irq - MCFINT_VECBASE - 64, MCFINTC1_SIMR);
33 static void intc_irq_unmask(unsigned int irq)
35 if (irq >= MCFINT_VECBASE) {
36 if (irq < MCFINT_VECBASE + 64)
37 __raw_writeb(irq - MCFINT_VECBASE, MCFINTC0_CIMR);
38 else if ((irq < MCFINT_VECBASE + 128) && MCFINTC1_CIMR)
39 __raw_writeb(irq - MCFINT_VECBASE - 64, MCFINTC1_CIMR);
43 static int intc_irq_set_type(unsigned int irq, unsigned int type)
45 if (irq >= MCFINT_VECBASE) {
46 if (irq < MCFINT_VECBASE + 64)
47 __raw_writeb(5, MCFINTC0_ICR0 + irq - MCFINT_VECBASE);
48 else if ((irq < MCFINT_VECBASE) && MCFINTC1_ICR0)
49 __raw_writeb(5, MCFINTC1_ICR0 + irq - MCFINT_VECBASE - 64);
54 static struct irq_chip intc_irq_chip = {
56 .mask = intc_irq_mask,
57 .unmask = intc_irq_unmask,
58 .set_type = intc_irq_set_type,
61 void __init init_IRQ(void)
67 /* Mask all interrupt sources */
68 __raw_writeb(0xff, MCFINTC0_SIMR);
70 __raw_writeb(0xff, MCFINTC1_SIMR);
72 for (irq = 0; (irq < NR_IRQS); irq++) {
73 irq_desc[irq].status = IRQ_DISABLED;
74 irq_desc[irq].action = NULL;
75 irq_desc[irq].depth = 1;
76 irq_desc[irq].chip = &intc_irq_chip;
77 intc_irq_set_type(irq, 0);