2 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2007-2009 PetaLogix
4 * Copyright (C) 2006 Atmark Techno, Inc.
6 * MMU code derived from arch/ppc/kernel/head_4xx.S:
7 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
8 * Initial PowerPC version.
9 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
11 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
12 * Low-level exception handers, MMU support, and rewrite.
13 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
14 * PowerPC 8xx modifications.
15 * Copyright (c) 1998-1999 TiVo, Inc.
16 * PowerPC 403GCX modifications.
17 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
18 * PowerPC 403GCX/405GP modifications.
19 * Copyright 2000 MontaVista Software Inc.
20 * PPC405 modifications
21 * PowerPC 403GCX/405GP modifications.
22 * Author: MontaVista Software, Inc.
23 * frank_rowand@mvista.com or source@mvista.com
24 * debbie_chu@mvista.com
26 * This file is subject to the terms and conditions of the GNU General Public
27 * License. See the file "COPYING" in the main directory of this archive
31 #include <linux/init.h>
32 #include <linux/linkage.h>
33 #include <asm/thread_info.h>
35 #include <linux/of_fdt.h> /* for OF_DT_HEADER */
38 #include <asm/setup.h> /* COMMAND_LINE_SIZE */
40 #include <asm/processor.h>
43 .global empty_zero_page
47 .global swapper_pg_dir
51 #endif /* CONFIG_MMU */
55 #if CONFIG_KERNEL_BASE_ADDR == 0
56 brai TOPHYS(real_start)
65 * Here is checking mechanism which check if Microblaze has msr instructions
66 * We load msr and compare it with previous r1 value - if is the same,
67 * msr instructions works if not - cpu don't have them.
69 /* r8=0 - I have msr instr, 1 - I don't have them */
70 rsubi r0, r0, 1 /* set the carry bit */
71 msrclr r0, 0x4 /* try to clear it */
72 /* read the carry bit, r8 will be '0' if msrclr exists */
75 /* r7 may point to an FDT, or there may be one linked in.
76 if it's in r7, we've got to save it away ASAP.
77 We ensure r7 points to a valid FDT, just in case the bootloader
78 is broken or non-existent */
79 beqi r7, no_fdt_arg /* NULL pointer? don't copy */
80 /* Does r7 point to a valid FDT? Load HEADER magic number */
81 /* Run time Big/Little endian platform */
82 /* Save 1 as word and load byte - 0 - BIG, 1 - LITTLE */
83 addik r11, r0, 0x1 /* BIG/LITTLE checking value */
84 /* __bss_start will be zeroed later - it is just temp location */
85 swi r11, r0, TOPHYS(__bss_start)
86 lbui r11, r0, TOPHYS(__bss_start)
87 beqid r11, big_endian /* DO NOT break delay stop dependency */
88 lw r11, r0, r7 /* Big endian load in delay slot */
89 lwr r11, r0, r7 /* Little endian load */
91 rsubi r11, r11, OF_DT_HEADER /* Check FDT header */
92 beqi r11, _prepare_copy_fdt
93 or r7, r0, r0 /* clear R7 when not valid DTB */
94 bnei r11, no_fdt_arg /* No - get out of here */
96 or r11, r0, r0 /* incremment */
97 ori r4, r0, TOPHYS(_fdt_start)
98 ori r3, r0, (0x4000 - 4)
100 lw r12, r7, r11 /* r12 = r7 + r11 */
101 sw r12, r4, r11 /* addr[r4 + r11] = r12 */
102 addik r11, r11, 4 /* increment counting */
103 bgtid r3, _copy_fdt /* loop for all entries */
104 addik r3, r3, -4 /* descrement loop */
109 #ifndef CONFIG_CMDLINE_BOOL
111 * handling command line
112 * copy command line to __init_end. There is space for storing command line.
114 or r6, r0, r0 /* incremment */
115 ori r4, r0, __init_end /* load address of command line */
116 tophys(r4,r4) /* convert to phys address */
117 ori r3, r0, COMMAND_LINE_SIZE - 1 /* number of loops */
119 lbu r2, r5, r6 /* r2=r5+r6 - r5 contain pointer to command line */
120 sb r2, r4, r6 /* addr[r4+r6]= r2*/
121 addik r6, r6, 1 /* increment counting */
122 bgtid r3, _copy_command_line /* loop for all entries */
123 addik r3, r3, -1 /* descrement loop */
124 addik r5, r4, 0 /* add new space for command line */
126 #endif /* CONFIG_CMDLINE_BOOL */
129 /* save bram context */
130 or r6, r0, r0 /* incremment */
131 ori r4, r0, TOPHYS(_bram_load_start) /* save bram context */
132 ori r3, r0, (LMB_SIZE - 4)
134 lw r7, r0, r6 /* r7 = r0 + r6 */
135 sw r7, r4, r6 /* addr[r4 + r6] = r7*/
136 addik r6, r6, 4 /* increment counting */
137 bgtid r3, _copy_bram /* loop for all entries */
138 addik r3, r3, -4 /* descrement loop */
140 /* We have to turn on the MMU right away. */
143 * Set up the initial MMU state so we can do the first level of
144 * kernel initialization. This maps the first 16 MBytes of memory 1:1
145 * virtual to physical.
148 addik r3, r0, MICROBLAZE_TLB_SIZE -1 /* Invalidate all TLB entries */
151 mts rtlbhi, r0 /* flush: ensure V is clear */
152 bgtid r3, _invalidate /* loop for all entries */
156 /* Setup the kernel PID */
157 mts rpid,r0 /* Load the kernel PID */
162 * We should still be executing code at physical address area
163 * RAM_BASEADDR at this point. However, kernel code is at
164 * a virtual address. So, set up a TLB mapping to cover this once
165 * translation is enabled.
168 addik r3,r0, CONFIG_KERNEL_START /* Load the kernel virtual address */
169 tophys(r4,r3) /* Load the kernel physical address */
172 * Configure and load two entries into TLB slots 0 and 1.
173 * In case we are pinning TLBs, these are reserved in by the
174 * other TLB functions. If not reserving, then it doesn't
175 * matter where they are loaded.
177 andi r4,r4,0xfffffc00 /* Mask off the real page number */
178 ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */
180 andi r3,r3,0xfffffc00 /* Mask off the effective page number */
181 ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M))
183 mts rtlbx,r0 /* TLB slow 0 */
185 mts rtlblo,r4 /* Load the data portion of the entry */
186 mts rtlbhi,r3 /* Load the tag portion of the entry */
188 addik r4, r4, 0x01000000 /* Map next 16 M entries */
189 addik r3, r3, 0x01000000
191 ori r6,r0,1 /* TLB slot 1 */
194 mts rtlblo,r4 /* Load the data portion of the entry */
195 mts rtlbhi,r3 /* Load the tag portion of the entry */
198 * Load a TLB entry for LMB, since we need access to
199 * the exception vectors, using a 4k real==virtual mapping.
201 ori r6,r0,3 /* TLB slot 3 */
204 ori r4,r0,(TLB_WR | TLB_EX)
205 ori r3,r0,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K))
207 mts rtlblo,r4 /* Load the data portion of the entry */
208 mts rtlbhi,r3 /* Load the tag portion of the entry */
211 * We now have the lower 16 Meg of RAM mapped into TLB entries, and the
212 * caches ready to work.
215 ori r15,r0,start_here
216 ori r4,r0,MSR_KERNEL_VMS
219 rted r15,0 /* enables MMU */
223 #endif /* CONFIG_MMU */
225 /* Initialize small data anchors */
226 la r13, r0, _KERNEL_SDA_BASE_
227 la r2, r0, _KERNEL_SDA2_BASE_
229 /* Initialize stack pointer */
230 la r1, r0, init_thread_union + THREAD_SIZE - 4
232 /* Initialize r31 with current task address */
233 la r31, r0, init_task
236 * Call platform dependent initialize function.
237 * Please see $(ARCH)/mach-$(SUBARCH)/setup.c for
240 la r9, r0, machine_early_init
245 la r15, r0, machine_halt
250 * Initialize the MMU.
255 /* Go back to running unmapped so we can load up new values
256 * and change to using our exception vectors.
257 * On the MicroBlaze, all we invalidate the used TLB entries to clear
258 * the old 16M byte TLB mappings.
260 ori r15,r0,TOPHYS(kernel_load_context)
268 /* Load up the kernel context */
270 # Keep entry 0 and 1 valid. Entry 3 mapped to LMB can go away.
276 addi r15, r0, machine_halt
277 ori r17, r0, start_kernel
278 ori r4, r0, MSR_KERNEL_VMS
281 rted r17, 0 /* enable MMU and jump to start_kernel */
283 #endif /* CONFIG_MMU */