arch/mips/alchemy/common/irq.c

   1 /*
   2  * Copyright 2001, 2007-2008 MontaVista Software Inc.
   3  * Author: MontaVista Software, Inc. <source@mvista.com>
   4  *
   5  * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
   6  *
   7  *  This program is free software; you can redistribute  it and/or modify it
   8  *  under  the terms of  the GNU General  Public License as published by the
   9  *  Free Software Foundation;  either version 2 of the  License, or (at your
  10  *  option) any later version.
  11  *
  12  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  13  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  14  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  15  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  16  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  17  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  18  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  19  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  20  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  21  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  22  *
  23  *  You should have received a copy of the  GNU General Public License along
  24  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  25  *  675 Mass Ave, Cambridge, MA 02139, USA.
  26  */
  27
  28 #include <linux/bitops.h>
  29 #include <linux/init.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/irq.h>
  32
  33 #include <asm/irq_cpu.h>
  34 #include <asm/mipsregs.h>
  35 #include <asm/mach-au1x00/au1000.h>
  36 #ifdef CONFIG_MIPS_PB1000
  37 #include <asm/mach-pb1x00/pb1000.h>
  38 #endif
  39
  40 static int au1x_ic_settype(unsigned int irq, unsigned int flow_type);
  41
  42 /* NOTE on interrupt priorities: The original writers of this code said:
  43  *
  44  * Because of the tight timing of SETUP token to reply transactions,
  45  * the USB devices-side packet complete interrupt (USB_DEV_REQ_INT)
  46  * needs the highest priority.
  47  */
  48
  49 /* per-processor fixed function irqs */
  50 struct au1xxx_irqmap {
  51         int im_irq;
  52         int im_type;
  53         int im_request;         /* set 1 to get higher priority */
  54 } au1xxx_ic0_map[] __initdata = {
  55 #if defined(CONFIG_SOC_AU1000)
  56         { AU1000_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
  57         { AU1000_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
  58         { AU1000_UART2_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
  59         { AU1000_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
  60         { AU1000_SSI0_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
  61         { AU1000_SSI1_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
  62         { AU1000_DMA_INT_BASE,    IRQ_TYPE_LEVEL_HIGH,  0 },
  63         { AU1000_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  0 },
  64         { AU1000_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  0 },
  65         { AU1000_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  0 },
  66         { AU1000_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  0 },
  67         { AU1000_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  0 },
  68         { AU1000_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  0 },
  69         { AU1000_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  0 },
  70         { AU1000_TOY_INT,         IRQ_TYPE_EDGE_RISING, 0 },
  71         { AU1000_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
  72         { AU1000_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
  73         { AU1000_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },
  74         { AU1000_RTC_INT,         IRQ_TYPE_EDGE_RISING, 0 },
  75         { AU1000_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
  76         { AU1000_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
  77         { AU1000_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },
  78         { AU1000_IRDA_TX_INT,     IRQ_TYPE_LEVEL_HIGH,  0 },
  79         { AU1000_IRDA_RX_INT,     IRQ_TYPE_LEVEL_HIGH,  0 },
  80         { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  1 },
  81         { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
  82         { AU1000_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   0 },
  83         { AU1000_ACSYNC_INT,      IRQ_TYPE_EDGE_RISING, 0 },
  84         { AU1000_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
  85         { AU1000_MAC1_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
  86         { AU1000_AC97C_INT,       IRQ_TYPE_EDGE_RISING, 0 },
  87
  88 #elif defined(CONFIG_SOC_AU1500)
  89
  90         { AU1500_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
  91         { AU1500_PCI_INTA,        IRQ_TYPE_LEVEL_LOW,   0 },
  92         { AU1500_PCI_INTB,        IRQ_TYPE_LEVEL_LOW,   0 },
  93         { AU1500_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
  94         { AU1500_PCI_INTC,        IRQ_TYPE_LEVEL_LOW,   0 },
  95         { AU1500_PCI_INTD,        IRQ_TYPE_LEVEL_LOW,   0 },
  96         { AU1500_DMA_INT_BASE,    IRQ_TYPE_LEVEL_HIGH,  0 },
  97         { AU1500_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  0 },
  98         { AU1500_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  0 },
  99         { AU1500_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  0 },
 100         { AU1500_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  0 },
 101         { AU1500_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  0 },
 102         { AU1500_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  0 },
 103         { AU1500_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  0 },
 104         { AU1500_TOY_INT,         IRQ_TYPE_EDGE_RISING, 0 },
 105         { AU1500_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 106         { AU1500_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 107         { AU1500_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 108         { AU1500_RTC_INT,         IRQ_TYPE_EDGE_RISING, 0 },
 109         { AU1500_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 110         { AU1500_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 111         { AU1500_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },
 112         { AU1500_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  1 },
 113         { AU1500_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
 114         { AU1500_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   0 },
 115         { AU1500_ACSYNC_INT,      IRQ_TYPE_EDGE_RISING, 0 },
 116         { AU1500_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
 117         { AU1500_MAC1_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
 118         { AU1500_AC97C_INT,       IRQ_TYPE_EDGE_RISING, 0 },
 119
 120 #elif defined(CONFIG_SOC_AU1100)
 121
 122         { AU1100_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
 123         { AU1100_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
 124         { AU1100_SD_INT,          IRQ_TYPE_LEVEL_HIGH,  0 },
 125         { AU1100_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
 126         { AU1100_SSI0_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 127         { AU1100_SSI1_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 128         { AU1100_DMA_INT_BASE,    IRQ_TYPE_LEVEL_HIGH,  0 },
 129         { AU1100_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  0 },
 130         { AU1100_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  0 },
 131         { AU1100_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  0 },
 132         { AU1100_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  0 },
 133         { AU1100_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  0 },
 134         { AU1100_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  0 },
 135         { AU1100_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  0 },
 136         { AU1100_TOY_INT,         IRQ_TYPE_EDGE_RISING, 0 },
 137         { AU1100_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 138         { AU1100_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 139         { AU1100_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 140         { AU1100_RTC_INT,         IRQ_TYPE_EDGE_RISING, 0 },
 141         { AU1100_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 142         { AU1100_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 143         { AU1100_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },
 144         { AU1100_IRDA_TX_INT,     IRQ_TYPE_LEVEL_HIGH,  0 },
 145         { AU1100_IRDA_RX_INT,     IRQ_TYPE_LEVEL_HIGH,  0 },
 146         { AU1100_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  1 },
 147         { AU1100_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
 148         { AU1100_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   0 },
 149         { AU1100_ACSYNC_INT,      IRQ_TYPE_EDGE_RISING, 0 },
 150         { AU1100_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
 151         { AU1100_LCD_INT,         IRQ_TYPE_LEVEL_HIGH,  0 },
 152         { AU1100_AC97C_INT,       IRQ_TYPE_EDGE_RISING, 0 },
 153
 154 #elif defined(CONFIG_SOC_AU1550)
 155
 156         { AU1550_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
 157         { AU1550_PCI_INTA,        IRQ_TYPE_LEVEL_LOW,   0 },
 158         { AU1550_PCI_INTB,        IRQ_TYPE_LEVEL_LOW,   0 },
 159         { AU1550_DDMA_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 160         { AU1550_CRYPTO_INT,      IRQ_TYPE_LEVEL_HIGH,  0 },
 161         { AU1550_PCI_INTC,        IRQ_TYPE_LEVEL_LOW,   0 },
 162         { AU1550_PCI_INTD,        IRQ_TYPE_LEVEL_LOW,   0 },
 163         { AU1550_PCI_RST_INT,     IRQ_TYPE_LEVEL_LOW,   0 },
 164         { AU1550_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
 165         { AU1550_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
 166         { AU1550_PSC0_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 167         { AU1550_PSC1_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 168         { AU1550_PSC2_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 169         { AU1550_PSC3_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 170         { AU1550_TOY_INT,         IRQ_TYPE_EDGE_RISING, 0 },
 171         { AU1550_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 172         { AU1550_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 173         { AU1550_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 174         { AU1550_RTC_INT,         IRQ_TYPE_EDGE_RISING, 0 },
 175         { AU1550_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 176         { AU1550_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 177         { AU1550_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },
 178         { AU1550_NAND_INT,        IRQ_TYPE_EDGE_RISING, 0 },
 179         { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  1 },
 180         { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
 181         { AU1550_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   0 },
 182         { AU1550_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
 183         { AU1550_MAC1_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
 184
 185 #elif defined(CONFIG_SOC_AU1200)
 186
 187         { AU1200_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
 188         { AU1200_SWT_INT,         IRQ_TYPE_EDGE_RISING, 0 },
 189         { AU1200_SD_INT,          IRQ_TYPE_LEVEL_HIGH,  0 },
 190         { AU1200_DDMA_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 191         { AU1200_MAE_BE_INT,      IRQ_TYPE_LEVEL_HIGH,  0 },
 192         { AU1200_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
 193         { AU1200_MAE_FE_INT,      IRQ_TYPE_LEVEL_HIGH,  0 },
 194         { AU1200_PSC0_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 195         { AU1200_PSC1_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 196         { AU1200_AES_INT,         IRQ_TYPE_LEVEL_HIGH,  0 },
 197         { AU1200_CAMERA_INT,      IRQ_TYPE_LEVEL_HIGH,  0 },
 198         { AU1200_TOY_INT,         IRQ_TYPE_EDGE_RISING, 0 },
 199         { AU1200_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 200         { AU1200_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 201         { AU1200_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 202         { AU1200_RTC_INT,         IRQ_TYPE_EDGE_RISING, 0 },
 203         { AU1200_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 204         { AU1200_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 205         { AU1200_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },
 206         { AU1200_NAND_INT,        IRQ_TYPE_EDGE_RISING, 0 },
 207         { AU1200_USB_INT,         IRQ_TYPE_LEVEL_HIGH,  0 },
 208         { AU1200_LCD_INT,         IRQ_TYPE_LEVEL_HIGH,  0 },
 209         { AU1200_MAE_BOTH_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
 210
 211 #else
 212 #error "Error: Unknown Alchemy SOC"
 213 #endif
 214 };
 215
 216
 217 #ifdef CONFIG_PM
 218
 219 /*
 220  * Save/restore the interrupt controller state.
 221  * Called from the save/restore core registers as part of the
 222  * au_sleep function in power.c.....maybe I should just pm_register()
 223  * them instead?
 224  */
 225 static unsigned int     sleep_intctl_config0[2];
 226 static unsigned int     sleep_intctl_config1[2];
 227 static unsigned int     sleep_intctl_config2[2];
 228 static unsigned int     sleep_intctl_src[2];
 229 static unsigned int     sleep_intctl_assign[2];
 230 static unsigned int     sleep_intctl_wake[2];
 231 static unsigned int     sleep_intctl_mask[2];
 232
 233 void save_au1xxx_intctl(void)
 234 {
 235         sleep_intctl_config0[0] = au_readl(IC0_CFG0RD);
 236         sleep_intctl_config1[0] = au_readl(IC0_CFG1RD);
 237         sleep_intctl_config2[0] = au_readl(IC0_CFG2RD);
 238         sleep_intctl_src[0] = au_readl(IC0_SRCRD);
 239         sleep_intctl_assign[0] = au_readl(IC0_ASSIGNRD);
 240         sleep_intctl_wake[0] = au_readl(IC0_WAKERD);
 241         sleep_intctl_mask[0] = au_readl(IC0_MASKRD);
 242
 243         sleep_intctl_config0[1] = au_readl(IC1_CFG0RD);
 244         sleep_intctl_config1[1] = au_readl(IC1_CFG1RD);
 245         sleep_intctl_config2[1] = au_readl(IC1_CFG2RD);
 246         sleep_intctl_src[1] = au_readl(IC1_SRCRD);
 247         sleep_intctl_assign[1] = au_readl(IC1_ASSIGNRD);
 248         sleep_intctl_wake[1] = au_readl(IC1_WAKERD);
 249         sleep_intctl_mask[1] = au_readl(IC1_MASKRD);
 250 }
 251
 252 /*
 253  * For most restore operations, we clear the entire register and
 254  * then set the bits we found during the save.
 255  */
 256 void restore_au1xxx_intctl(void)
 257 {
 258         au_writel(0xffffffff, IC0_MASKCLR); au_sync();
 259
 260         au_writel(0xffffffff, IC0_CFG0CLR); au_sync();
 261         au_writel(sleep_intctl_config0[0], IC0_CFG0SET); au_sync();
 262         au_writel(0xffffffff, IC0_CFG1CLR); au_sync();
 263         au_writel(sleep_intctl_config1[0], IC0_CFG1SET); au_sync();
 264         au_writel(0xffffffff, IC0_CFG2CLR); au_sync();
 265         au_writel(sleep_intctl_config2[0], IC0_CFG2SET); au_sync();
 266         au_writel(0xffffffff, IC0_SRCCLR); au_sync();
 267         au_writel(sleep_intctl_src[0], IC0_SRCSET); au_sync();
 268         au_writel(0xffffffff, IC0_ASSIGNCLR); au_sync();
 269         au_writel(sleep_intctl_assign[0], IC0_ASSIGNSET); au_sync();
 270         au_writel(0xffffffff, IC0_WAKECLR); au_sync();
 271         au_writel(sleep_intctl_wake[0], IC0_WAKESET); au_sync();
 272         au_writel(0xffffffff, IC0_RISINGCLR); au_sync();
 273         au_writel(0xffffffff, IC0_FALLINGCLR); au_sync();
 274         au_writel(0x00000000, IC0_TESTBIT); au_sync();
 275
 276         au_writel(0xffffffff, IC1_MASKCLR); au_sync();
 277
 278         au_writel(0xffffffff, IC1_CFG0CLR); au_sync();
 279         au_writel(sleep_intctl_config0[1], IC1_CFG0SET); au_sync();
 280         au_writel(0xffffffff, IC1_CFG1CLR); au_sync();
 281         au_writel(sleep_intctl_config1[1], IC1_CFG1SET); au_sync();
 282         au_writel(0xffffffff, IC1_CFG2CLR); au_sync();
 283         au_writel(sleep_intctl_config2[1], IC1_CFG2SET); au_sync();
 284         au_writel(0xffffffff, IC1_SRCCLR); au_sync();
 285         au_writel(sleep_intctl_src[1], IC1_SRCSET); au_sync();
 286         au_writel(0xffffffff, IC1_ASSIGNCLR); au_sync();
 287         au_writel(sleep_intctl_assign[1], IC1_ASSIGNSET); au_sync();
 288         au_writel(0xffffffff, IC1_WAKECLR); au_sync();
 289         au_writel(sleep_intctl_wake[1], IC1_WAKESET); au_sync();
 290         au_writel(0xffffffff, IC1_RISINGCLR); au_sync();
 291         au_writel(0xffffffff, IC1_FALLINGCLR); au_sync();
 292         au_writel(0x00000000, IC1_TESTBIT); au_sync();
 293
 294         au_writel(sleep_intctl_mask[1], IC1_MASKSET); au_sync();
 295
 296         au_writel(sleep_intctl_mask[0], IC0_MASKSET); au_sync();
 297 }
 298 #endif /* CONFIG_PM */
 299
 300
 301 static void au1x_ic0_unmask(unsigned int irq_nr)
 302 {
 303         unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
 304         au_writel(1 << bit, IC0_MASKSET);
 305         au_writel(1 << bit, IC0_WAKESET);
 306         au_sync();
 307 }
 308
 309 static void au1x_ic1_unmask(unsigned int irq_nr)
 310 {
 311         unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
 312         au_writel(1 << bit, IC1_MASKSET);
 313         au_writel(1 << bit, IC1_WAKESET);
 314
 315 /* very hacky. does the pb1000 cpld auto-disable this int?
 316  * nowhere in the current kernel sources is it disabled.        --mlau
 317  */
 318 #if defined(CONFIG_MIPS_PB1000)
 319         if (irq_nr == AU1000_GPIO15_INT)
 320                 au_writel(0x4000, PB1000_MDR); /* enable int */
 321 #endif
 322         au_sync();
 323 }
 324
 325 static void au1x_ic0_mask(unsigned int irq_nr)
 326 {
 327         unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
 328         au_writel(1 << bit, IC0_MASKCLR);
 329         au_writel(1 << bit, IC0_WAKECLR);
 330         au_sync();
 331 }
 332
 333 static void au1x_ic1_mask(unsigned int irq_nr)
 334 {
 335         unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
 336         au_writel(1 << bit, IC1_MASKCLR);
 337         au_writel(1 << bit, IC1_WAKECLR);
 338         au_sync();
 339 }
 340
 341 static void au1x_ic0_ack(unsigned int irq_nr)
 342 {
 343         unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
 344
 345         /*
 346          * This may assume that we don't get interrupts from
 347          * both edges at once, or if we do, that we don't care.
 348          */
 349         au_writel(1 << bit, IC0_FALLINGCLR);
 350         au_writel(1 << bit, IC0_RISINGCLR);
 351         au_sync();
 352 }
 353
 354 static void au1x_ic1_ack(unsigned int irq_nr)
 355 {
 356         unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
 357
 358         /*
 359          * This may assume that we don't get interrupts from
 360          * both edges at once, or if we do, that we don't care.
 361          */
 362         au_writel(1 << bit, IC1_FALLINGCLR);
 363         au_writel(1 << bit, IC1_RISINGCLR);
 364         au_sync();
 365 }
 366
 367 static void au1x_ic0_maskack(unsigned int irq_nr)
 368 {
 369         unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
 370
 371         au_writel(1 << bit, IC0_WAKECLR);
 372         au_writel(1 << bit, IC0_MASKCLR);
 373         au_writel(1 << bit, IC0_RISINGCLR);
 374         au_writel(1 << bit, IC0_FALLINGCLR);
 375         au_sync();
 376 }
 377
 378 static void au1x_ic1_maskack(unsigned int irq_nr)
 379 {
 380         unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
 381
 382         au_writel(1 << bit, IC1_WAKECLR);
 383         au_writel(1 << bit, IC1_MASKCLR);
 384         au_writel(1 << bit, IC1_RISINGCLR);
 385         au_writel(1 << bit, IC1_FALLINGCLR);
 386         au_sync();
 387 }
 388
 389 static int au1x_ic1_setwake(unsigned int irq, unsigned int on)
 390 {
 391         int bit = irq - AU1000_INTC1_INT_BASE;
 392         unsigned long wakemsk, flags;
 393
 394         /* only GPIO 0-7 can act as wakeup source.  Fortunately these
 395          * are wired up identically on all supported variants.
 396          */
 397         if ((bit < 0) || (bit > 7))
 398                 return -EINVAL;
 399
 400         local_irq_save(flags);
 401         wakemsk = au_readl(SYS_WAKEMSK);
 402         if (on)
 403                 wakemsk |= 1 << bit;
 404         else
 405                 wakemsk &= ~(1 << bit);
 406         au_writel(wakemsk, SYS_WAKEMSK);
 407         au_sync();
 408         local_irq_restore(flags);
 409
 410         return 0;
 411 }
 412
 413 /*
 414  * irq_chips for both ICs; this way the mask handlers can be
 415  * as short as possible.
 416  */
 417 static struct irq_chip au1x_ic0_chip = {
 418         .name           = "Alchemy-IC0",
 419         .ack            = au1x_ic0_ack,
 420         .mask           = au1x_ic0_mask,
 421         .mask_ack       = au1x_ic0_maskack,
 422         .unmask         = au1x_ic0_unmask,
 423         .set_type       = au1x_ic_settype,
 424 };
 425
 426 static struct irq_chip au1x_ic1_chip = {
 427         .name           = "Alchemy-IC1",
 428         .ack            = au1x_ic1_ack,
 429         .mask           = au1x_ic1_mask,
 430         .mask_ack       = au1x_ic1_maskack,
 431         .unmask         = au1x_ic1_unmask,
 432         .set_type       = au1x_ic_settype,
 433         .set_wake       = au1x_ic1_setwake,
 434 };
 435
 436 static int au1x_ic_settype(unsigned int irq, unsigned int flow_type)
 437 {
 438         struct irq_chip *chip;
 439         unsigned long icr[6];
 440         unsigned int bit, ic;
 441         int ret;
 442
 443         if (irq >= AU1000_INTC1_INT_BASE) {
 444                 bit = irq - AU1000_INTC1_INT_BASE;
 445                 chip = &au1x_ic1_chip;
 446                 ic = 1;
 447         } else {
 448                 bit = irq - AU1000_INTC0_INT_BASE;
 449                 chip = &au1x_ic0_chip;
 450                 ic = 0;
 451         }
 452
 453         if (bit > 31)
 454                 return -EINVAL;
 455
 456         icr[0] = ic ? IC1_CFG0SET : IC0_CFG0SET;
 457         icr[1] = ic ? IC1_CFG1SET : IC0_CFG1SET;
 458         icr[2] = ic ? IC1_CFG2SET : IC0_CFG2SET;
 459         icr[3] = ic ? IC1_CFG0CLR : IC0_CFG0CLR;
 460         icr[4] = ic ? IC1_CFG1CLR : IC0_CFG1CLR;
 461         icr[5] = ic ? IC1_CFG2CLR : IC0_CFG2CLR;
 462
 463         ret = 0;
 464
 465         switch (flow_type) {    /* cfgregs 2:1:0 */
 466         case IRQ_TYPE_EDGE_RISING:      /* 0:0:1 */
 467                 au_writel(1 << bit, icr[5]);
 468                 au_writel(1 << bit, icr[4]);
 469                 au_writel(1 << bit, icr[0]);
 470                 set_irq_chip_and_handler_name(irq, chip,
 471                                 handle_edge_irq, "riseedge");
 472                 break;
 473         case IRQ_TYPE_EDGE_FALLING:     /* 0:1:0 */
 474                 au_writel(1 << bit, icr[5]);
 475                 au_writel(1 << bit, icr[1]);
 476                 au_writel(1 << bit, icr[3]);
 477                 set_irq_chip_and_handler_name(irq, chip,
 478                                 handle_edge_irq, "falledge");
 479                 break;
 480         case IRQ_TYPE_EDGE_BOTH:        /* 0:1:1 */
 481                 au_writel(1 << bit, icr[5]);
 482                 au_writel(1 << bit, icr[1]);
 483                 au_writel(1 << bit, icr[0]);
 484                 set_irq_chip_and_handler_name(irq, chip,
 485                                 handle_edge_irq, "bothedge");
 486                 break;
 487         case IRQ_TYPE_LEVEL_HIGH:       /* 1:0:1 */
 488                 au_writel(1 << bit, icr[2]);
 489                 au_writel(1 << bit, icr[4]);
 490                 au_writel(1 << bit, icr[0]);
 491                 set_irq_chip_and_handler_name(irq, chip,
 492                                 handle_level_irq, "hilevel");
 493                 break;
 494         case IRQ_TYPE_LEVEL_LOW:        /* 1:1:0 */
 495                 au_writel(1 << bit, icr[2]);
 496                 au_writel(1 << bit, icr[1]);
 497                 au_writel(1 << bit, icr[3]);
 498                 set_irq_chip_and_handler_name(irq, chip,
 499                                 handle_level_irq, "lowlevel");
 500                 break;
 501         case IRQ_TYPE_NONE:             /* 0:0:0 */
 502                 au_writel(1 << bit, icr[5]);
 503                 au_writel(1 << bit, icr[4]);
 504                 au_writel(1 << bit, icr[3]);
 505                 /* set at least chip so we can call set_irq_type() on it */
 506                 set_irq_chip(irq, chip);
 507                 break;
 508         default:
 509                 ret = -EINVAL;
 510         }
 511         au_sync();
 512
 513         return ret;
 514 }
 515
 516 asmlinkage void plat_irq_dispatch(void)
 517 {
 518         unsigned int pending = read_c0_status() & read_c0_cause();
 519         unsigned long s, off;
 520
 521         if (pending & CAUSEF_IP7) {
 522                 off = MIPS_CPU_IRQ_BASE + 7;
 523                 goto handle;
 524         } else if (pending & CAUSEF_IP2) {
 525                 s = IC0_REQ0INT;
 526                 off = AU1000_INTC0_INT_BASE;
 527         } else if (pending & CAUSEF_IP3) {
 528                 s = IC0_REQ1INT;
 529                 off = AU1000_INTC0_INT_BASE;
 530         } else if (pending & CAUSEF_IP4) {
 531                 s = IC1_REQ0INT;
 532                 off = AU1000_INTC1_INT_BASE;
 533         } else if (pending & CAUSEF_IP5) {
 534                 s = IC1_REQ1INT;
 535                 off = AU1000_INTC1_INT_BASE;
 536         } else
 537                 goto spurious;
 538
 539         s = au_readl(s);
 540         if (unlikely(!s)) {
 541 spurious:
 542                 spurious_interrupt();
 543                 return;
 544         }
 545         off += __ffs(s);
 546 handle:
 547         do_IRQ(off);
 548 }
 549
 550 /* setup edge/level and assign request 0/1 */
 551 static void __init setup_irqmap(struct au1xxx_irqmap *map, int count)
 552 {
 553         unsigned int bit, irq_nr;
 554
 555         while (count--) {
 556                 irq_nr = map[count].im_irq;
 557
 558                 if (((irq_nr < AU1000_INTC0_INT_BASE) ||
 559                      (irq_nr >= AU1000_INTC0_INT_BASE + 32)) &&
 560                     ((irq_nr < AU1000_INTC1_INT_BASE) ||
 561                      (irq_nr >= AU1000_INTC1_INT_BASE + 32)))
 562                         continue;
 563
 564                 if (irq_nr >= AU1000_INTC1_INT_BASE) {
 565                         bit = irq_nr - AU1000_INTC1_INT_BASE;
 566                         if (map[count].im_request)
 567                                 au_writel(1 << bit, IC1_ASSIGNSET);
 568                 } else {
 569                         bit = irq_nr - AU1000_INTC0_INT_BASE;
 570                         if (map[count].im_request)
 571                                 au_writel(1 << bit, IC0_ASSIGNSET);
 572                 }
 573
 574                 au1x_ic_settype(irq_nr, map[count].im_type);
 575         }
 576 }
 577
 578 void __init arch_init_irq(void)
 579 {
 580         int i;
 581
 582         /*
 583          * Initialize interrupt controllers to a safe state.
 584          */
 585         au_writel(0xffffffff, IC0_CFG0CLR);
 586         au_writel(0xffffffff, IC0_CFG1CLR);
 587         au_writel(0xffffffff, IC0_CFG2CLR);
 588         au_writel(0xffffffff, IC0_MASKCLR);
 589         au_writel(0xffffffff, IC0_ASSIGNCLR);
 590         au_writel(0xffffffff, IC0_WAKECLR);
 591         au_writel(0xffffffff, IC0_SRCSET);
 592         au_writel(0xffffffff, IC0_FALLINGCLR);
 593         au_writel(0xffffffff, IC0_RISINGCLR);
 594         au_writel(0x00000000, IC0_TESTBIT);
 595
 596         au_writel(0xffffffff, IC1_CFG0CLR);
 597         au_writel(0xffffffff, IC1_CFG1CLR);
 598         au_writel(0xffffffff, IC1_CFG2CLR);
 599         au_writel(0xffffffff, IC1_MASKCLR);
 600         au_writel(0xffffffff, IC1_ASSIGNCLR);
 601         au_writel(0xffffffff, IC1_WAKECLR);
 602         au_writel(0xffffffff, IC1_SRCSET);
 603         au_writel(0xffffffff, IC1_FALLINGCLR);
 604         au_writel(0xffffffff, IC1_RISINGCLR);
 605         au_writel(0x00000000, IC1_TESTBIT);
 606
 607         mips_cpu_irq_init();
 608
 609         /* register all 64 possible IC0+IC1 irq sources as type "none".
 610          * Use set_irq_type() to set edge/level behaviour at runtime.
 611          */
 612         for (i = AU1000_INTC0_INT_BASE;
 613              (i < AU1000_INTC0_INT_BASE + 32); i++)
 614                 au1x_ic_settype(i, IRQ_TYPE_NONE);
 615
 616         for (i = AU1000_INTC1_INT_BASE;
 617              (i < AU1000_INTC1_INT_BASE + 32); i++)
 618                 au1x_ic_settype(i, IRQ_TYPE_NONE);
 619
 620         /*
 621          * Initialize IC0, which is fixed per processor.
 622          */
 623         setup_irqmap(au1xxx_ic0_map, ARRAY_SIZE(au1xxx_ic0_map));
 624
 625         set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3);
 626 }