2 * Alchemy Db1550 board support
4 * (c) 2011 Manuel Lauss <manuel.lauss@googlemail.com>
7 #include <linux/dma-mapping.h>
8 #include <linux/gpio.h>
10 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/mtd/mtd.h>
14 #include <linux/mtd/nand.h>
15 #include <linux/mtd/partitions.h>
16 #include <linux/platform_device.h>
18 #include <linux/spi/spi.h>
19 #include <linux/spi/flash.h>
20 #include <asm/mach-au1x00/au1000.h>
21 #include <asm/mach-au1x00/au1xxx_eth.h>
22 #include <asm/mach-au1x00/au1xxx_dbdma.h>
23 #include <asm/mach-au1x00/au1xxx_psc.h>
24 #include <asm/mach-au1x00/au1550_spi.h>
25 #include <asm/mach-db1x00/bcsr.h>
30 const char *get_system_type(void)
35 static void __init db1550_hw_setup(void)
39 alchemy_gpio_direction_output(203, 0); /* red led on */
41 /* complete SPI setup: link psc0_intclk to a 48MHz source,
42 * and assign GPIO16 to PSC0_SYNC1 (SPI cs# line)
44 base = (void __iomem *)SYS_CLKSRC;
45 __raw_writel(__raw_readl(base) | 0x000001e0, base);
46 base = (void __iomem *)SYS_PINFUNC;
47 __raw_writel(__raw_readl(base) | 1, base);
50 /* reset the AC97 codec now, the reset time in the psc-ac97 driver
51 * is apparently too short although it's ridiculous as it is.
53 base = (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR);
54 __raw_writel(PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE,
55 base + PSC_SEL_OFFSET);
56 __raw_writel(PSC_CTRL_DISABLE, base + PSC_CTRL_OFFSET);
58 __raw_writel(PSC_AC97RST_RST, base + PSC_AC97RST_OFFSET);
61 alchemy_gpio_direction_output(202, 0); /* green led on */
64 void __init board_setup(void)
66 unsigned short whoami;
68 bcsr_init(DB1550_BCSR_PHYS_ADDR,
69 DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS);
71 whoami = bcsr_read(BCSR_WHOAMI);
72 printk(KERN_INFO "Alchemy/AMD DB1550 Board, CPLD Rev %d"
73 " Board-ID %d Daughtercard ID %d\n",
74 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
79 /*****************************************************************************/
81 static struct mtd_partition db1550_spiflash_parts[] = {
85 .size = MTDPART_SIZ_FULL,
89 static struct flash_platform_data db1550_spiflash_data = {
91 .parts = db1550_spiflash_parts,
92 .nr_parts = ARRAY_SIZE(db1550_spiflash_parts),
96 static struct spi_board_info db1550_spi_devs[] __initdata = {
98 /* TI TMP121AIDBVR temp sensor */
100 .max_speed_hz = 2400000,
106 /* Spansion S25FL001D0FMA SPI flash */
107 .modalias = "m25p80",
108 .max_speed_hz = 2400000,
112 .platform_data = &db1550_spiflash_data,
116 static struct i2c_board_info db1550_i2c_devs[] __initdata = {
117 { I2C_BOARD_INFO("24c04", 0x52),}, /* AT24C04-10 I2C eeprom */
118 { I2C_BOARD_INFO("ne1619", 0x2d),}, /* adm1025-compat hwmon */
119 { I2C_BOARD_INFO("wm8731", 0x1b),}, /* I2S audio codec WM8731 */
122 /**********************************************************************/
124 static void au1550_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
127 struct nand_chip *this = mtd->priv;
128 unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
130 ioaddr &= 0xffffff00;
132 if (ctrl & NAND_CLE) {
133 ioaddr += MEM_STNAND_CMD;
134 } else if (ctrl & NAND_ALE) {
135 ioaddr += MEM_STNAND_ADDR;
137 /* assume we want to r/w real data by default */
138 ioaddr += MEM_STNAND_DATA;
140 this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
141 if (cmd != NAND_CMD_NONE) {
142 __raw_writeb(cmd, this->IO_ADDR_W);
147 static int au1550_nand_device_ready(struct mtd_info *mtd)
149 return __raw_readl((void __iomem *)MEM_STSTAT) & 1;
152 static struct mtd_partition db1550_nand_parts[] = {
156 .size = 8 * 1024 * 1024,
160 .offset = MTDPART_OFS_APPEND,
161 .size = MTDPART_SIZ_FULL
165 struct platform_nand_data db1550_nand_platdata = {
169 .nr_partitions = ARRAY_SIZE(db1550_nand_parts),
170 .partitions = db1550_nand_parts,
174 .dev_ready = au1550_nand_device_ready,
175 .cmd_ctrl = au1550_nand_cmd_ctrl,
179 static struct resource db1550_nand_res[] = {
183 .flags = IORESOURCE_MEM,
187 static struct platform_device db1550_nand_dev = {
189 .num_resources = ARRAY_SIZE(db1550_nand_res),
190 .resource = db1550_nand_res,
193 .platform_data = &db1550_nand_platdata,
197 /**********************************************************************/
199 static struct resource au1550_psc0_res[] = {
201 .start = AU1550_PSC0_PHYS_ADDR,
202 .end = AU1550_PSC0_PHYS_ADDR + 0xfff,
203 .flags = IORESOURCE_MEM,
206 .start = AU1550_PSC0_INT,
207 .end = AU1550_PSC0_INT,
208 .flags = IORESOURCE_IRQ,
211 .start = AU1550_DSCR_CMD0_PSC0_TX,
212 .end = AU1550_DSCR_CMD0_PSC0_TX,
213 .flags = IORESOURCE_DMA,
216 .start = AU1550_DSCR_CMD0_PSC0_RX,
217 .end = AU1550_DSCR_CMD0_PSC0_RX,
218 .flags = IORESOURCE_DMA,
222 static void db1550_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
225 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SPISEL);
227 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SPISEL, 0);
230 static struct au1550_spi_info db1550_spi_platdata = {
231 .mainclk_hz = 48000000, /* PSC0 clock: max. 2.4MHz SPI clk */
233 .activate_cs = db1550_spi_cs_en,
236 static u64 spi_dmamask = DMA_BIT_MASK(32);
238 static struct platform_device db1550_spi_dev = {
240 .dma_mask = &spi_dmamask,
241 .coherent_dma_mask = DMA_BIT_MASK(32),
242 .platform_data = &db1550_spi_platdata,
244 .name = "au1550-spi",
245 .id = 0, /* bus number */
246 .num_resources = ARRAY_SIZE(au1550_psc0_res),
247 .resource = au1550_psc0_res,
250 /**********************************************************************/
252 static struct resource au1550_psc1_res[] = {
254 .start = AU1550_PSC1_PHYS_ADDR,
255 .end = AU1550_PSC1_PHYS_ADDR + 0xfff,
256 .flags = IORESOURCE_MEM,
259 .start = AU1550_PSC1_INT,
260 .end = AU1550_PSC1_INT,
261 .flags = IORESOURCE_IRQ,
264 .start = AU1550_DSCR_CMD0_PSC1_TX,
265 .end = AU1550_DSCR_CMD0_PSC1_TX,
266 .flags = IORESOURCE_DMA,
269 .start = AU1550_DSCR_CMD0_PSC1_RX,
270 .end = AU1550_DSCR_CMD0_PSC1_RX,
271 .flags = IORESOURCE_DMA,
275 static struct platform_device db1550_ac97_dev = {
276 .name = "au1xpsc_ac97",
277 .id = 1, /* PSC ID */
278 .num_resources = ARRAY_SIZE(au1550_psc1_res),
279 .resource = au1550_psc1_res,
283 static struct resource au1550_psc2_res[] = {
285 .start = AU1550_PSC2_PHYS_ADDR,
286 .end = AU1550_PSC2_PHYS_ADDR + 0xfff,
287 .flags = IORESOURCE_MEM,
290 .start = AU1550_PSC2_INT,
291 .end = AU1550_PSC2_INT,
292 .flags = IORESOURCE_IRQ,
295 .start = AU1550_DSCR_CMD0_PSC2_TX,
296 .end = AU1550_DSCR_CMD0_PSC2_TX,
297 .flags = IORESOURCE_DMA,
300 .start = AU1550_DSCR_CMD0_PSC2_RX,
301 .end = AU1550_DSCR_CMD0_PSC2_RX,
302 .flags = IORESOURCE_DMA,
306 static struct platform_device db1550_i2c_dev = {
307 .name = "au1xpsc_smbus",
308 .id = 0, /* bus number */
309 .num_resources = ARRAY_SIZE(au1550_psc2_res),
310 .resource = au1550_psc2_res,
313 /**********************************************************************/
315 static struct resource au1550_psc3_res[] = {
317 .start = AU1550_PSC3_PHYS_ADDR,
318 .end = AU1550_PSC3_PHYS_ADDR + 0xfff,
319 .flags = IORESOURCE_MEM,
322 .start = AU1550_PSC3_INT,
323 .end = AU1550_PSC3_INT,
324 .flags = IORESOURCE_IRQ,
327 .start = AU1550_DSCR_CMD0_PSC3_TX,
328 .end = AU1550_DSCR_CMD0_PSC3_TX,
329 .flags = IORESOURCE_DMA,
332 .start = AU1550_DSCR_CMD0_PSC3_RX,
333 .end = AU1550_DSCR_CMD0_PSC3_RX,
334 .flags = IORESOURCE_DMA,
338 static struct platform_device db1550_i2s_dev = {
339 .name = "au1xpsc_i2s",
340 .id = 3, /* PSC ID */
341 .num_resources = ARRAY_SIZE(au1550_psc3_res),
342 .resource = au1550_psc3_res,
345 /**********************************************************************/
347 static struct platform_device db1550_stac_dev = {
348 .name = "ac97-codec",
349 .id = 1, /* on PSC1 */
352 static struct platform_device db1550_ac97dma_dev = {
353 .name = "au1xpsc-pcm",
354 .id = 1, /* on PSC3 */
357 static struct platform_device db1550_i2sdma_dev = {
358 .name = "au1xpsc-pcm",
359 .id = 3, /* on PSC3 */
362 static struct platform_device db1550_sndac97_dev = {
363 .name = "db1550-ac97",
366 static struct platform_device db1550_sndi2s_dev = {
367 .name = "db1550-i2s",
370 /**********************************************************************/
372 static int db1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
374 if ((slot < 11) || (slot > 13) || pin == 0)
377 return (pin == 1) ? AU1550_PCI_INTC : 0xff;
380 case 1: return AU1550_PCI_INTB;
381 case 2: return AU1550_PCI_INTC;
382 case 3: return AU1550_PCI_INTD;
383 case 4: return AU1550_PCI_INTA;
388 case 1: return AU1550_PCI_INTA;
389 case 2: return AU1550_PCI_INTB;
390 case 3: return AU1550_PCI_INTC;
391 case 4: return AU1550_PCI_INTD;
397 static struct resource alchemy_pci_host_res[] = {
399 .start = AU1500_PCI_PHYS_ADDR,
400 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
401 .flags = IORESOURCE_MEM,
405 static struct alchemy_pci_platdata db1550_pci_pd = {
406 .board_map_irq = db1550_map_pci_irq,
409 static struct platform_device db1550_pci_host_dev = {
410 .dev.platform_data = &db1550_pci_pd,
411 .name = "alchemy-pci",
413 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
414 .resource = alchemy_pci_host_res,
417 /**********************************************************************/
419 static struct platform_device *db1550_devs[] __initdata = {
432 /* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
433 static int __init db1550_pci_init(void)
435 return platform_device_register(&db1550_pci_host_dev);
437 arch_initcall(db1550_pci_init);
439 static int __init db1550_dev_init(void)
443 irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_EDGE_BOTH); /* CD0# */
444 irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_EDGE_BOTH); /* CD1# */
445 irq_set_irq_type(AU1550_GPIO3_INT, IRQ_TYPE_LEVEL_LOW); /* CARD0# */
446 irq_set_irq_type(AU1550_GPIO5_INT, IRQ_TYPE_LEVEL_LOW); /* CARD1# */
447 irq_set_irq_type(AU1550_GPIO21_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG0# */
448 irq_set_irq_type(AU1550_GPIO22_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG1# */
450 i2c_register_board_info(0, db1550_i2c_devs,
451 ARRAY_SIZE(db1550_i2c_devs));
452 spi_register_board_info(db1550_spi_devs,
453 ARRAY_SIZE(db1550_i2c_devs));
455 /* Audio PSC clock is supplied by codecs (PSC1, 3) FIXME: platdata!! */
456 __raw_writel(PSC_SEL_CLK_SERCLK,
457 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
459 __raw_writel(PSC_SEL_CLK_SERCLK,
460 (void __iomem *)KSEG1ADDR(AU1550_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET);
462 /* SPI/I2C use internally supplied 50MHz source */
463 __raw_writel(PSC_SEL_CLK_INTCLK,
464 (void __iomem *)KSEG1ADDR(AU1550_PSC0_PHYS_ADDR) + PSC_SEL_OFFSET);
466 __raw_writel(PSC_SEL_CLK_INTCLK,
467 (void __iomem *)KSEG1ADDR(AU1550_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET);
470 db1x_register_pcmcia_socket(
471 AU1000_PCMCIA_ATTR_PHYS_ADDR,
472 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
473 AU1000_PCMCIA_MEM_PHYS_ADDR,
474 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
475 AU1000_PCMCIA_IO_PHYS_ADDR,
476 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
477 AU1550_GPIO3_INT, AU1550_GPIO0_INT,
478 /*AU1550_GPIO21_INT*/0, 0, 0);
480 db1x_register_pcmcia_socket(
481 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
482 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
483 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
484 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
485 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
486 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
487 AU1550_GPIO5_INT, AU1550_GPIO1_INT,
488 /*AU1550_GPIO22_INT*/0, 0, 1);
490 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
491 db1x_register_norflash(128 << 20, 4, swapped);
493 return platform_add_devices(db1550_devs, ARRAY_SIZE(db1550_devs));
495 device_initcall(db1550_dev_init);