2 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
3 * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
4 * Copyright (C) 2009-2010 Florian Fainelli <florian@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <linux/module.h>
22 #include <linux/gpio.h>
24 #include <asm/mach-ar7/ar7.h>
26 #define AR7_GPIO_MAX 32
27 #define TITAN_GPIO_MAX 51
29 struct ar7_gpio_chip {
31 struct gpio_chip chip;
34 static int ar7_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
36 struct ar7_gpio_chip *gpch =
37 container_of(chip, struct ar7_gpio_chip, chip);
38 void __iomem *gpio_in = gpch->regs + AR7_GPIO_INPUT;
40 return readl(gpio_in) & (1 << gpio);
43 static int titan_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
45 struct ar7_gpio_chip *gpch =
46 container_of(chip, struct ar7_gpio_chip, chip);
47 void __iomem *gpio_in0 = gpch->regs + TITAN_GPIO_INPUT_0;
48 void __iomem *gpio_in1 = gpch->regs + TITAN_GPIO_INPUT_1;
50 return readl(gpio >> 5 ? gpio_in1 : gpio_in0) & (1 << (gpio & 0x1f));
53 static void ar7_gpio_set_value(struct gpio_chip *chip,
54 unsigned gpio, int value)
56 struct ar7_gpio_chip *gpch =
57 container_of(chip, struct ar7_gpio_chip, chip);
58 void __iomem *gpio_out = gpch->regs + AR7_GPIO_OUTPUT;
61 tmp = readl(gpio_out) & ~(1 << gpio);
64 writel(tmp, gpio_out);
67 static void titan_gpio_set_value(struct gpio_chip *chip,
68 unsigned gpio, int value)
70 struct ar7_gpio_chip *gpch =
71 container_of(chip, struct ar7_gpio_chip, chip);
72 void __iomem *gpio_out0 = gpch->regs + TITAN_GPIO_OUTPUT_0;
73 void __iomem *gpio_out1 = gpch->regs + TITAN_GPIO_OUTPUT_1;
76 tmp = readl(gpio >> 5 ? gpio_out1 : gpio_out0) & ~(1 << (gpio & 0x1f));
78 tmp |= 1 << (gpio & 0x1f);
79 writel(tmp, gpio >> 5 ? gpio_out1 : gpio_out0);
82 static int ar7_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
84 struct ar7_gpio_chip *gpch =
85 container_of(chip, struct ar7_gpio_chip, chip);
86 void __iomem *gpio_dir = gpch->regs + AR7_GPIO_DIR;
88 writel(readl(gpio_dir) | (1 << gpio), gpio_dir);
93 static int titan_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
95 struct ar7_gpio_chip *gpch =
96 container_of(chip, struct ar7_gpio_chip, chip);
97 void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0;
98 void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1;
100 if (gpio >= TITAN_GPIO_MAX)
103 writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) | (1 << (gpio & 0x1f)),
104 gpio >> 5 ? gpio_dir1 : gpio_dir0);
108 static int ar7_gpio_direction_output(struct gpio_chip *chip,
109 unsigned gpio, int value)
111 struct ar7_gpio_chip *gpch =
112 container_of(chip, struct ar7_gpio_chip, chip);
113 void __iomem *gpio_dir = gpch->regs + AR7_GPIO_DIR;
115 ar7_gpio_set_value(chip, gpio, value);
116 writel(readl(gpio_dir) & ~(1 << gpio), gpio_dir);
121 static int titan_gpio_direction_output(struct gpio_chip *chip,
122 unsigned gpio, int value)
124 struct ar7_gpio_chip *gpch =
125 container_of(chip, struct ar7_gpio_chip, chip);
126 void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0;
127 void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1;
129 if (gpio >= TITAN_GPIO_MAX)
132 titan_gpio_set_value(chip, gpio, value);
133 writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) & ~(1 <<
134 (gpio & 0x1f)), gpio >> 5 ? gpio_dir1 : gpio_dir0);
139 static struct ar7_gpio_chip ar7_gpio_chip = {
142 .direction_input = ar7_gpio_direction_input,
143 .direction_output = ar7_gpio_direction_output,
144 .set = ar7_gpio_set_value,
145 .get = ar7_gpio_get_value,
147 .ngpio = AR7_GPIO_MAX,
151 static struct ar7_gpio_chip titan_gpio_chip = {
153 .label = "titan-gpio",
154 .direction_input = titan_gpio_direction_input,
155 .direction_output = titan_gpio_direction_output,
156 .set = titan_gpio_set_value,
157 .get = titan_gpio_get_value,
159 .ngpio = TITAN_GPIO_MAX,
163 static inline int ar7_gpio_enable_ar7(unsigned gpio)
165 void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
167 writel(readl(gpio_en) | (1 << gpio), gpio_en);
172 static inline int ar7_gpio_enable_titan(unsigned gpio)
174 void __iomem *gpio_en0 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_0;
175 void __iomem *gpio_en1 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_1;
177 writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) | (1 << (gpio & 0x1f)),
178 gpio >> 5 ? gpio_en1 : gpio_en0);
183 int ar7_gpio_enable(unsigned gpio)
185 return ar7_is_titan() ? ar7_gpio_enable_titan(gpio) :
186 ar7_gpio_enable_ar7(gpio);
188 EXPORT_SYMBOL(ar7_gpio_enable);
190 static inline int ar7_gpio_disable_ar7(unsigned gpio)
192 void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
194 writel(readl(gpio_en) & ~(1 << gpio), gpio_en);
199 static inline int ar7_gpio_disable_titan(unsigned gpio)
201 void __iomem *gpio_en0 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_0;
202 void __iomem *gpio_en1 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_1;
204 writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) & ~(1 << (gpio & 0x1f)),
205 gpio >> 5 ? gpio_en1 : gpio_en0);
210 int ar7_gpio_disable(unsigned gpio)
212 return ar7_is_titan() ? ar7_gpio_disable_titan(gpio) :
213 ar7_gpio_disable_ar7(gpio);
215 EXPORT_SYMBOL(ar7_gpio_disable);
217 struct titan_gpio_cfg {
223 static const struct titan_gpio_cfg titan_gpio_table[] = {
224 /* reg, start bit, mux value */
279 static int titan_gpio_pinsel(unsigned gpio)
281 struct titan_gpio_cfg gpio_cfg;
282 u32 mux_status, pin_sel_reg, tmp;
283 void __iomem *pin_sel = (void __iomem *)KSEG1ADDR(AR7_REGS_PINSEL);
285 if (gpio >= ARRAY_SIZE(titan_gpio_table))
288 gpio_cfg = titan_gpio_table[gpio];
289 pin_sel_reg = gpio_cfg.reg - 1;
291 mux_status = (readl(pin_sel + pin_sel_reg) >> gpio_cfg.shift) & 0x3;
293 /* Check the mux status */
294 if (!((mux_status == 0) || (mux_status == gpio_cfg.func)))
297 /* Set the pin sel value */
298 tmp = readl(pin_sel + pin_sel_reg);
299 tmp |= ((gpio_cfg.func & 0x3) << gpio_cfg.shift);
300 writel(tmp, pin_sel + pin_sel_reg);
305 /* Perform minimal Titan GPIO configuration */
306 static void titan_gpio_init(void)
310 for (i = 44; i < 48; i++) {
311 titan_gpio_pinsel(i);
312 ar7_gpio_enable_titan(i);
313 titan_gpio_direction_input(&titan_gpio_chip.chip, i);
317 int __init ar7_gpio_init(void)
320 struct ar7_gpio_chip *gpch;
323 if (!ar7_is_titan()) {
324 gpch = &ar7_gpio_chip;
327 gpch = &titan_gpio_chip;
331 gpch->regs = ioremap_nocache(AR7_REGS_GPIO, size);
333 printk(KERN_ERR "%s: failed to ioremap regs\n",
338 ret = gpiochip_add(&gpch->chip);
340 printk(KERN_ERR "%s: failed to add gpiochip\n",
344 printk(KERN_INFO "%s: registered %d GPIOs\n",
345 gpch->chip.label, gpch->chip.ngpio);