3 * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com>
4 * Copied and modified Carsten Langgaard's time.c
6 * Carsten Langgaard, carstenl@mips.com
7 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
9 * ########################################################################
11 * This program is free software; you can distribute it and/or modify it
12 * under the terms of the GNU General Public License (Version 2) as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
24 * ########################################################################
26 * Setting up the clock on the MIPS boards.
28 * Update. Always configure the kernel with CONFIG_NEW_TIME_C. This
29 * will use the user interface gettimeofday() functions from the
30 * arch/mips/kernel/time.c, and we provide the clock interrupt processing
31 * and the timer offset compute functions. If CONFIG_PM is selected,
32 * we also ensure the 32KHz timer is available. -- Dan
35 #include <linux/types.h>
36 #include <linux/init.h>
37 #include <linux/kernel_stat.h>
38 #include <linux/sched.h>
39 #include <linux/spinlock.h>
40 #include <linux/hardirq.h>
42 #include <asm/compiler.h>
43 #include <asm/mipsregs.h>
45 #include <asm/div64.h>
46 #include <asm/mach-au1x00/au1000.h>
48 #include <linux/mc146818rtc.h>
49 #include <linux/timex.h>
51 static int no_au1xxx_32khz;
52 extern int allow_au1k_wait; /* default off for CP0 Counter */
55 #if HZ < 100 || HZ > 1000
56 #error "unsupported HZ value! Must be in [100,1000]"
58 #define MATCH20_INC (328*100/HZ) /* magic number 328 is for HZ=100... */
59 extern void startup_match20_interrupt(irq_handler_t handler);
60 static unsigned long last_pc0, last_match20;
63 static DEFINE_SPINLOCK(time_lock);
68 static irqreturn_t counter0_irq(int irq, void *dev_id)
72 static int jiffie_drift = 0;
74 if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) {
75 /* should never happen! */
76 printk(KERN_WARNING "counter 0 w status error\n");
80 pc0 = au_readl(SYS_TOYREAD);
81 if (pc0 < last_match20) {
82 /* counter overflowed */
83 time_elapsed = (0xffffffff - last_match20) + pc0;
86 time_elapsed = pc0 - last_match20;
89 while (time_elapsed > 0) {
92 update_process_times(user_mode(get_irq_regs()));
94 time_elapsed -= MATCH20_INC;
95 last_match20 += MATCH20_INC;
100 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
103 /* our counter ticks at 10.009765625 ms/tick, we we're running
104 * almost 10uS too slow per tick.
107 if (jiffie_drift >= 999) {
109 do_timer(1); /* increment jiffies by one */
111 update_process_times(user_mode(get_irq_regs()));
118 struct irqaction counter0_action = {
119 .handler = counter0_irq,
120 .flags = IRQF_DISABLED,
121 .name = "alchemy-toy",
125 /* When we wakeup from sleep, we have to "catch up" on all of the
126 * timer ticks we have missed.
129 wakeup_counter0_adjust(void)
134 pc0 = au_readl(SYS_TOYREAD);
135 if (pc0 < last_match20) {
136 /* counter overflowed */
137 time_elapsed = (0xffffffff - last_match20) + pc0;
140 time_elapsed = pc0 - last_match20;
143 while (time_elapsed > 0) {
144 time_elapsed -= MATCH20_INC;
145 last_match20 += MATCH20_INC;
149 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
154 /* This is just for debugging to set the timer for a sleep delay.
157 wakeup_counter0_set(int ticks)
161 pc0 = au_readl(SYS_TOYREAD);
163 au_writel(last_match20 + (MATCH20_INC * ticks), SYS_TOYMATCH2);
168 /* I haven't found anyone that doesn't use a 12 MHz source clock,
169 * but just in case.....
171 #define AU1000_SRC_CLK 12000000
174 * We read the real processor speed from the PLL. This is important
175 * because it is more accurate than computing it from the 32KHz
176 * counter, if it exists. If we don't have an accurate processor
177 * speed, all of the peripherals that derive their clocks based on
178 * this advertised speed will introduce error and sometimes not work
179 * properly. This function is futher convoluted to still allow configurations
180 * to do that in case they have really, really old silicon with a
181 * write-only PLL register, that we need the 32KHz when power management
182 * "wait" is enabled, and we need to detect if the 32KHz isn't present
183 * but requested......got it? :-) -- Dan
185 unsigned long calc_clock(void)
187 unsigned long cpu_speed;
189 unsigned long counter;
191 spin_lock_irqsave(&time_lock, flags);
193 /* Power management cares if we don't have a 32KHz counter.
196 counter = au_readl(SYS_COUNTER_CNTRL);
197 if (counter & SYS_CNTRL_E0) {
198 int trim_divide = 16;
200 au_writel(counter | SYS_CNTRL_EN1, SYS_COUNTER_CNTRL);
202 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
203 /* RTC now ticks at 32.768/16 kHz */
204 au_writel(trim_divide-1, SYS_RTCTRIM);
205 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
207 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
208 au_writel(0, SYS_TOYWRITE);
209 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
214 * On early Au1000, sys_cpupll was write-only. Since these
215 * silicon versions of Au1000 are not sold by AMD, we don't bend
216 * over backwards trying to determine the frequency.
218 if (cur_cpu_spec[0]->cpu_pll_wo)
219 #ifdef CONFIG_SOC_AU1000_FREQUENCY
220 cpu_speed = CONFIG_SOC_AU1000_FREQUENCY;
222 cpu_speed = 396000000;
225 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
226 mips_hpt_frequency = cpu_speed;
227 // Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16)
228 set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));
229 spin_unlock_irqrestore(&time_lock, flags);
233 void __init plat_time_init(void)
235 unsigned int est_freq = calc_clock();
237 est_freq += 5000; /* round */
238 est_freq -= est_freq%10000;
239 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
240 (est_freq%1000000)*100/1000000);
241 set_au1x00_speed(est_freq);
242 set_au1x00_lcd_clock(); // program the LCD clock
246 * setup counter 0, since it keeps ticking after a
247 * 'wait' instruction has been executed. The CP0 timer and
248 * counter 1 do NOT continue running after 'wait'
250 * It's too early to call request_irq() here, so we handle
251 * counter 0 interrupt as a special irq and it doesn't show
252 * up under /proc/interrupts.
254 * Check to ensure we really have a 32KHz oscillator before
258 printk("WARNING: no 32KHz clock found.\n");
260 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
261 au_writel(0, SYS_TOYWRITE);
262 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
264 au_writel(au_readl(SYS_WAKEMSK) | (1<<8), SYS_WAKEMSK);
265 au_writel(~0, SYS_WAKESRC);
267 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
269 /* setup match20 to interrupt once every HZ */
270 last_pc0 = last_match20 = au_readl(SYS_TOYREAD);
271 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
273 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
274 setup_irq(AU1000_TOY_MATCH2_INT, &counter0_action);
276 /* We can use the real 'wait' instruction.