2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
10 #include <linux/init.h>
11 #include <linux/bitops.h>
12 #include <linux/bootmem.h>
13 #include <linux/clk-provider.h>
14 #include <linux/ioport.h>
15 #include <linux/kernel.h>
18 #include <linux/of_fdt.h>
19 #include <linux/of_platform.h>
20 #include <linux/smp.h>
21 #include <asm/addrspace.h>
22 #include <asm/bmips.h>
23 #include <asm/bootinfo.h>
24 #include <asm/cpu-type.h>
25 #include <asm/mipsregs.h>
27 #include <asm/smp-ops.h>
29 #include <asm/traps.h>
31 #define RELO_NORMAL_VEC BIT(18)
33 #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c))
34 #define BCM6328_TP1_DISABLED BIT(9)
36 static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;
39 const char *compatible;
40 void (*quirk_fn)(void);
43 static void kbase_setup(void)
45 __raw_writel(kbase | RELO_NORMAL_VEC,
46 BMIPS_GET_CBR() + BMIPS_RELO_VECTOR_CONTROL_1);
50 static void bcm3384_viper_quirks(void)
53 * Some experimental CM boxes are set up to let CM own the Viper TP0
54 * and let Linux own TP1. This requires moving the kernel
55 * load address to a non-conflicting region (e.g. via
56 * CONFIG_PHYSICAL_START) and supplying an alternate DTB.
57 * If we detect this condition, we need to move the MIPS exception
58 * vectors up to an area that we own.
60 * This is distinct from the OTHER special case mentioned in
61 * smp-bmips.c (boot on TP1, but enable SMP, then TP0 becomes our
62 * logical CPU#1). For the Viper TP1 case, SMP is off limits.
64 * Also note that many BMIPS435x CPUs do not have a
65 * BMIPS_RELO_VECTOR_CONTROL_1 register, so it isn't safe to just
66 * write VMLINUX_LOAD_ADDRESS into that register on every SoC.
68 board_ebase_setup = &kbase_setup;
69 bmips_smp_enabled = 0;
72 static void bcm63xx_fixup_cpu1(void)
75 * The bootloader has set up the CPU1 reset vector at
77 * This conflicts with the special interrupt vector (IV).
78 * The bootloader has also set up CPU1 to respond to the wrong
80 * Here we will start up CPU1 in the background and ask it to
81 * reconfigure itself then go back to sleep.
83 memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20);
86 cpumask_set_cpu(1, &bmips_booted_mask);
89 static void bcm6328_quirks(void)
91 /* Check CPU1 status in OTP (it is usually disabled) */
92 if (__raw_readl(REG_BCM6328_OTP) & BCM6328_TP1_DISABLED)
93 bmips_smp_enabled = 0;
98 static void bcm6368_quirks(void)
100 bcm63xx_fixup_cpu1();
103 static const struct bmips_quirk bmips_quirk_list[] = {
104 { "brcm,bcm3384-viper", &bcm3384_viper_quirks },
105 { "brcm,bcm33843-viper", &bcm3384_viper_quirks },
106 { "brcm,bcm6328", &bcm6328_quirks },
107 { "brcm,bcm6368", &bcm6368_quirks },
108 { "brcm,bcm63168", &bcm6368_quirks },
112 void __init prom_init(void)
114 register_bmips_smp_ops();
117 void __init prom_free_prom_memory(void)
121 const char *get_system_type(void)
123 return "Generic BMIPS kernel";
126 void __init plat_time_init(void)
128 struct device_node *np;
131 np = of_find_node_by_name(NULL, "cpus");
133 panic("missing 'cpus' DT node");
134 if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
135 panic("missing 'mips-hpt-frequency' property");
138 mips_hpt_frequency = freq;
141 void __init plat_mem_setup(void)
144 const struct bmips_quirk *q;
147 ioport_resource.start = 0;
148 ioport_resource.end = ~0;
150 /* intended to somewhat resemble ARM; see Documentation/arm/Booting */
151 if (fw_arg0 == 0 && fw_arg1 == 0xffffffff)
152 dtb = phys_to_virt(fw_arg2);
153 else if (fw_arg0 == -2) /* UHI interface */
154 dtb = (void *)fw_arg1;
155 else if (__dtb_start != __dtb_end)
156 dtb = (void *)__dtb_start;
158 panic("no dtb found");
160 __dt_setup_arch(dtb);
162 for (q = bmips_quirk_list; q->quirk_fn; q++) {
163 if (of_flat_dt_is_compatible(of_get_flat_dt_root(),
170 void __init device_tree_init(void)
172 struct device_node *np;
174 unflatten_and_copy_device_tree();
176 /* Disable SMP boot unless both CPUs are listed in DT and !disabled */
177 np = of_find_node_by_name(NULL, "cpus");
178 if (np && of_get_available_child_count(np) <= 1)
179 bmips_smp_enabled = 0;
183 int __init plat_of_setup(void)
185 return __dt_register_buses("simple-bus", NULL);
188 arch_initcall(plat_of_setup);
190 static int __init plat_dev_init(void)
196 device_initcall(plat_dev_init);