4 compatible = "brcm,bcm7360";
10 mips-hpt-frequency = <375000000>;
13 compatible = "brcm,bmips3300";
27 compatible = "mti,cpu-interrupt-controller";
30 #interrupt-cells = <1>;
35 compatible = "fixed-clock";
37 clock-frequency = <81000000>;
45 compatible = "simple-bus";
46 ranges = <0 0x10000000 0x01000000>;
48 periph_intc: periph_intc@411400 {
49 compatible = "brcm,bcm7038-l1-intc";
50 reg = <0x411400 0x30>;
53 #interrupt-cells = <1>;
55 interrupt-parent = <&cpu_intc>;
59 sun_l2_intc: sun_l2_intc@403000 {
60 compatible = "brcm,l2-intc";
61 reg = <0x403000 0x30>;
63 #interrupt-cells = <1>;
64 interrupt-parent = <&periph_intc>;
69 compatible = "brcm,bcm7400-gisb-arb";
70 reg = <0x400000 0xdc>;
72 interrupt-parent = <&sun_l2_intc>;
73 interrupts = <0>, <2>;
74 brcm,gisb-arb-master-mask = <0x2f3>;
75 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
80 upg_irq0_intc: upg_irq0_intc@406600 {
81 compatible = "brcm,bcm7120-l2-intc";
84 brcm,int-map-mask = <0x44>, <0x7000000>;
85 brcm,int-fwd-mask = <0x70000>;
88 #interrupt-cells = <1>;
90 interrupt-parent = <&periph_intc>;
91 interrupts = <56>, <54>;
92 interrupt-names = "upg_main", "upg_bsc";
95 upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
96 compatible = "brcm,bcm7120-l2-intc";
99 brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
100 brcm,int-fwd-mask = <0>;
103 interrupt-controller;
104 #interrupt-cells = <1>;
106 interrupt-parent = <&periph_intc>;
107 interrupts = <57>, <55>, <59>;
108 interrupt-names = "upg_main_aon", "upg_bsc_aon",
112 sun_top_ctrl: syscon@404000 {
113 compatible = "brcm,bcm7360-sun-top-ctrl", "syscon";
114 reg = <0x404000 0x51c>;
119 compatible = "brcm,brcmstb-reboot";
120 syscon = <&sun_top_ctrl 0x304 0x308>;
123 uart0: serial@406800 {
124 compatible = "ns16550a";
125 reg = <0x406800 0x20>;
126 reg-io-width = <0x4>;
129 interrupt-parent = <&periph_intc>;
131 clocks = <&uart_clk>;
135 uart1: serial@406840 {
136 compatible = "ns16550a";
137 reg = <0x406840 0x20>;
138 reg-io-width = <0x4>;
141 interrupt-parent = <&periph_intc>;
143 clocks = <&uart_clk>;
147 uart2: serial@406880 {
148 compatible = "ns16550a";
149 reg = <0x406880 0x20>;
150 reg-io-width = <0x4>;
153 interrupt-parent = <&periph_intc>;
155 clocks = <&uart_clk>;
160 clock-frequency = <390000>;
161 compatible = "brcm,brcmstb-i2c";
162 interrupt-parent = <&upg_irq0_intc>;
163 reg = <0x406200 0x58>;
165 interrupt-names = "upg_bsca";
170 clock-frequency = <390000>;
171 compatible = "brcm,brcmstb-i2c";
172 interrupt-parent = <&upg_irq0_intc>;
173 reg = <0x406280 0x58>;
175 interrupt-names = "upg_bscb";
180 clock-frequency = <390000>;
181 compatible = "brcm,brcmstb-i2c";
182 interrupt-parent = <&upg_irq0_intc>;
183 reg = <0x406300 0x58>;
185 interrupt-names = "upg_bscc";
190 clock-frequency = <390000>;
191 compatible = "brcm,brcmstb-i2c";
192 interrupt-parent = <&upg_aon_irq0_intc>;
193 reg = <0x408980 0x58>;
195 interrupt-names = "upg_bscd";
199 enet0: ethernet@430000 {
200 phy-mode = "internal";
201 phy-handle = <&phy1>;
202 mac-address = [ 00 10 18 36 23 1a ];
203 compatible = "brcm,genet-v2";
204 #address-cells = <0x1>;
206 reg = <0x430000 0x4c8c>;
207 interrupts = <24>, <25>;
208 interrupt-parent = <&periph_intc>;
212 compatible = "brcm,genet-mdio-v2";
213 #address-cells = <0x1>;
217 phy1: ethernet-phy@1 {
220 compatible = "brcm,40nm-ephy",
221 "ethernet-phy-ieee802.3-c22";
227 compatible = "brcm,bcm7360-ehci", "generic-ehci";
228 reg = <0x480300 0x100>;
230 interrupt-parent = <&periph_intc>;
236 compatible = "brcm,bcm7360-ohci", "generic-ohci";
237 reg = <0x480400 0x100>;
240 interrupt-parent = <&periph_intc>;