4 compatible = "brcm,bcm7362";
10 mips-hpt-frequency = <375000000>;
13 compatible = "brcm,bmips4380";
19 compatible = "brcm,bmips4380";
33 compatible = "mti,cpu-interrupt-controller";
36 #interrupt-cells = <1>;
41 compatible = "fixed-clock";
43 clock-frequency = <81000000>;
51 compatible = "simple-bus";
52 ranges = <0 0x10000000 0x01000000>;
54 periph_intc: periph_intc@411400 {
55 compatible = "brcm,bcm7038-l1-intc";
56 reg = <0x411400 0x30>, <0x411600 0x30>;
59 #interrupt-cells = <1>;
61 interrupt-parent = <&cpu_intc>;
62 interrupts = <2>, <3>;
65 sun_l2_intc: sun_l2_intc@403000 {
66 compatible = "brcm,l2-intc";
67 reg = <0x403000 0x30>;
69 #interrupt-cells = <1>;
70 interrupt-parent = <&periph_intc>;
75 compatible = "brcm,bcm7400-gisb-arb";
76 reg = <0x400000 0xdc>;
78 interrupt-parent = <&sun_l2_intc>;
79 interrupts = <0>, <2>;
80 brcm,gisb-arb-master-mask = <0x2f3>;
81 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
86 upg_irq0_intc: upg_irq0_intc@406600 {
87 compatible = "brcm,bcm7120-l2-intc";
90 brcm,int-map-mask = <0x44>, <0x7000000>;
91 brcm,int-fwd-mask = <0x70000>;
94 #interrupt-cells = <1>;
96 interrupt-parent = <&periph_intc>;
97 interrupts = <56>, <54>;
98 interrupt-names = "upg_main", "upg_bsc";
101 upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
102 compatible = "brcm,bcm7120-l2-intc";
103 reg = <0x408b80 0x8>;
105 brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
106 brcm,int-fwd-mask = <0>;
109 interrupt-controller;
110 #interrupt-cells = <1>;
112 interrupt-parent = <&periph_intc>;
113 interrupts = <57>, <55>, <59>;
114 interrupt-names = "upg_main_aon", "upg_bsc_aon",
118 sun_top_ctrl: syscon@404000 {
119 compatible = "brcm,bcm7362-sun-top-ctrl", "syscon";
120 reg = <0x404000 0x51c>;
124 compatible = "brcm,brcmstb-reboot";
125 syscon = <&sun_top_ctrl 0x304 0x308>;
128 uart0: serial@406800 {
129 compatible = "ns16550a";
130 reg = <0x406800 0x20>;
131 reg-io-width = <0x4>;
134 interrupt-parent = <&periph_intc>;
136 clocks = <&uart_clk>;
140 uart1: serial@406840 {
141 compatible = "ns16550a";
142 reg = <0x406840 0x20>;
143 reg-io-width = <0x4>;
146 interrupt-parent = <&periph_intc>;
148 clocks = <&uart_clk>;
152 uart2: serial@406880 {
153 compatible = "ns16550a";
154 reg = <0x406880 0x20>;
155 reg-io-width = <0x4>;
158 interrupt-parent = <&periph_intc>;
160 clocks = <&uart_clk>;
165 clock-frequency = <390000>;
166 compatible = "brcm,brcmstb-i2c";
167 interrupt-parent = <&upg_irq0_intc>;
168 reg = <0x406200 0x58>;
170 interrupt-names = "upg_bsca";
175 clock-frequency = <390000>;
176 compatible = "brcm,brcmstb-i2c";
177 interrupt-parent = <&upg_irq0_intc>;
178 reg = <0x406280 0x58>;
180 interrupt-names = "upg_bscb";
185 clock-frequency = <390000>;
186 compatible = "brcm,brcmstb-i2c";
187 interrupt-parent = <&upg_aon_irq0_intc>;
188 reg = <0x408980 0x58>;
190 interrupt-names = "upg_bscd";
194 enet0: ethernet@430000 {
195 phy-mode = "internal";
196 phy-handle = <&phy1>;
197 mac-address = [ 00 10 18 36 23 1a ];
198 compatible = "brcm,genet-v2";
199 #address-cells = <0x1>;
201 reg = <0x430000 0x4c8c>;
202 interrupts = <24>, <25>;
203 interrupt-parent = <&periph_intc>;
207 compatible = "brcm,genet-mdio-v2";
208 #address-cells = <0x1>;
212 phy1: ethernet-phy@1 {
215 compatible = "brcm,40nm-ephy",
216 "ethernet-phy-ieee802.3-c22";
222 compatible = "brcm,bcm7362-ehci", "generic-ehci";
223 reg = <0x480300 0x100>;
225 interrupt-parent = <&periph_intc>;
231 compatible = "brcm,bcm7362-ohci", "generic-ohci";
232 reg = <0x480400 0x100>;
235 interrupt-parent = <&periph_intc>;
241 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
242 reg-names = "ahci", "top-ctrl";
243 reg = <0x181000 0xa9c>, <0x180020 0x1c>;
244 interrupt-parent = <&periph_intc>;
246 #address-cells = <1>;
263 sata_phy: sata-phy@1800000 {
264 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
265 reg = <0x180100 0x0eff>;
267 #address-cells = <1>;
271 sata_phy0: sata-phy@0 {
276 sata_phy1: sata-phy@1 {