arch/mips/boot/dts/brcm/bcm7362.dtsi

   1 / {
   2         #address-cells = <1>;
   3         #size-cells = <1>;
   4         compatible = "brcm,bcm7362";
   5
   6         cpus {
   7                 #address-cells = <1>;
   8                 #size-cells = <0>;
   9
  10                 mips-hpt-frequency = <375000000>;
  11
  12                 cpu@0 {
  13                         compatible = "brcm,bmips4380";
  14                         device_type = "cpu";
  15                         reg = <0>;
  16                 };
  17
  18                 cpu@1 {
  19                         compatible = "brcm,bmips4380";
  20                         device_type = "cpu";
  21                         reg = <1>;
  22                 };
  23         };
  24
  25         aliases {
  26                 uart0 = &uart0;
  27                 uart1 = &uart1;
  28                 uart2 = &uart2;
  29         };
  30
  31         cpu_intc: cpu_intc {
  32                 #address-cells = <0>;
  33                 compatible = "mti,cpu-interrupt-controller";
  34
  35                 interrupt-controller;
  36                 #interrupt-cells = <1>;
  37         };
  38
  39         clocks {
  40                 uart_clk: uart_clk {
  41                         compatible = "fixed-clock";
  42                         #clock-cells = <0>;
  43                         clock-frequency = <81000000>;
  44                 };
  45         };
  46
  47         rdb {
  48                 #address-cells = <1>;
  49                 #size-cells = <1>;
  50
  51                 compatible = "simple-bus";
  52                 ranges = <0 0x10000000 0x01000000>;
  53
  54                 periph_intc: periph_intc@411400 {
  55                         compatible = "brcm,bcm7038-l1-intc";
  56                         reg = <0x411400 0x30>, <0x411600 0x30>;
  57
  58                         interrupt-controller;
  59                         #interrupt-cells = <1>;
  60
  61                         interrupt-parent = <&cpu_intc>;
  62                         interrupts = <2>, <3>;
  63                 };
  64
  65                 sun_l2_intc: sun_l2_intc@403000 {
  66                         compatible = "brcm,l2-intc";
  67                         reg = <0x403000 0x30>;
  68                         interrupt-controller;
  69                         #interrupt-cells = <1>;
  70                         interrupt-parent = <&periph_intc>;
  71                         interrupts = <48>;
  72                 };
  73
  74                 gisb-arb@400000 {
  75                         compatible = "brcm,bcm7400-gisb-arb";
  76                         reg = <0x400000 0xdc>;
  77                         native-endian;
  78                         interrupt-parent = <&sun_l2_intc>;
  79                         interrupts = <0>, <2>;
  80                         brcm,gisb-arb-master-mask = <0x2f3>;
  81                         brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
  82                                                      "rdc_0", "raaga_0",
  83                                                      "avd_0", "jtag_0";
  84                 };
  85
  86                 upg_irq0_intc: upg_irq0_intc@406600 {
  87                         compatible = "brcm,bcm7120-l2-intc";
  88                         reg = <0x406600 0x8>;
  89
  90                         brcm,int-map-mask = <0x44>, <0x7000000>;
  91                         brcm,int-fwd-mask = <0x70000>;
  92
  93                         interrupt-controller;
  94                         #interrupt-cells = <1>;
  95
  96                         interrupt-parent = <&periph_intc>;
  97                         interrupts = <56>, <54>;
  98                         interrupt-names = "upg_main", "upg_bsc";
  99                 };
 100
 101                 upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
 102                         compatible = "brcm,bcm7120-l2-intc";
 103                         reg = <0x408b80 0x8>;
 104
 105                         brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
 106                         brcm,int-fwd-mask = <0>;
 107                         brcm,irq-can-wake;
 108
 109                         interrupt-controller;
 110                         #interrupt-cells = <1>;
 111
 112                         interrupt-parent = <&periph_intc>;
 113                         interrupts = <57>, <55>, <59>;
 114                         interrupt-names = "upg_main_aon", "upg_bsc_aon",
 115                                           "upg_spi";
 116                 };
 117
 118                 sun_top_ctrl: syscon@404000 {
 119                         compatible = "brcm,bcm7362-sun-top-ctrl", "syscon";
 120                         reg = <0x404000 0x51c>;
 121                 };
 122
 123                 reboot {
 124                         compatible = "brcm,brcmstb-reboot";
 125                         syscon = <&sun_top_ctrl 0x304 0x308>;
 126                 };
 127
 128                 uart0: serial@406800 {
 129                         compatible = "ns16550a";
 130                         reg = <0x406800 0x20>;
 131                         reg-io-width = <0x4>;
 132                         reg-shift = <0x2>;
 133                         native-endian;
 134                         interrupt-parent = <&periph_intc>;
 135                         interrupts = <61>;
 136                         clocks = <&uart_clk>;
 137                         status = "disabled";
 138                 };
 139
 140                 uart1: serial@406840 {
 141                         compatible = "ns16550a";
 142                         reg = <0x406840 0x20>;
 143                         reg-io-width = <0x4>;
 144                         reg-shift = <0x2>;
 145                         native-endian;
 146                         interrupt-parent = <&periph_intc>;
 147                         interrupts = <62>;
 148                         clocks = <&uart_clk>;
 149                         status = "disabled";
 150                 };
 151
 152                 uart2: serial@406880 {
 153                         compatible = "ns16550a";
 154                         reg = <0x406880 0x20>;
 155                         reg-io-width = <0x4>;
 156                         reg-shift = <0x2>;
 157                         native-endian;
 158                         interrupt-parent = <&periph_intc>;
 159                         interrupts = <63>;
 160                         clocks = <&uart_clk>;
 161                         status = "disabled";
 162                 };
 163
 164                 bsca: i2c@406200 {
 165                       clock-frequency = <390000>;
 166                       compatible = "brcm,brcmstb-i2c";
 167                       interrupt-parent = <&upg_irq0_intc>;
 168                       reg = <0x406200 0x58>;
 169                       interrupts = <24>;
 170                       interrupt-names = "upg_bsca";
 171                       status = "disabled";
 172                 };
 173
 174                 bscb: i2c@406280 {
 175                       clock-frequency = <390000>;
 176                       compatible = "brcm,brcmstb-i2c";
 177                       interrupt-parent = <&upg_irq0_intc>;
 178                       reg = <0x406280 0x58>;
 179                       interrupts = <25>;
 180                       interrupt-names = "upg_bscb";
 181                       status = "disabled";
 182                 };
 183
 184                 bscd: i2c@408980 {
 185                       clock-frequency = <390000>;
 186                       compatible = "brcm,brcmstb-i2c";
 187                       interrupt-parent = <&upg_aon_irq0_intc>;
 188                       reg = <0x408980 0x58>;
 189                       interrupts = <27>;
 190                       interrupt-names = "upg_bscd";
 191                       status = "disabled";
 192                 };
 193
 194                 enet0: ethernet@430000 {
 195                         phy-mode = "internal";
 196                         phy-handle = <&phy1>;
 197                         mac-address = [ 00 10 18 36 23 1a ];
 198                         compatible = "brcm,genet-v2";
 199                         #address-cells = <0x1>;
 200                         #size-cells = <0x1>;
 201                         reg = <0x430000 0x4c8c>;
 202                         interrupts = <24>, <25>;
 203                         interrupt-parent = <&periph_intc>;
 204                         status = "disabled";
 205
 206                         mdio@e14 {
 207                                 compatible = "brcm,genet-mdio-v2";
 208                                 #address-cells = <0x1>;
 209                                 #size-cells = <0x0>;
 210                                 reg = <0xe14 0x8>;
 211
 212                                 phy1: ethernet-phy@1 {
 213                                         max-speed = <100>;
 214                                         reg = <0x1>;
 215                                         compatible = "brcm,40nm-ephy",
 216                                                 "ethernet-phy-ieee802.3-c22";
 217                                 };
 218                         };
 219                 };
 220
 221                 ehci0: usb@480300 {
 222                         compatible = "brcm,bcm7362-ehci", "generic-ehci";
 223                         reg = <0x480300 0x100>;
 224                         native-endian;
 225                         interrupt-parent = <&periph_intc>;
 226                         interrupts = <65>;
 227                         status = "disabled";
 228                 };
 229
 230                 ohci0: usb@480400 {
 231                         compatible = "brcm,bcm7362-ohci", "generic-ohci";
 232                         reg = <0x480400 0x100>;
 233                         native-endian;
 234                         no-big-frame-no;
 235                         interrupt-parent = <&periph_intc>;
 236                         interrupts = <66>;
 237                         status = "disabled";
 238                 };
 239
 240                 sata: sata@181000 {
 241                         compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
 242                         reg-names = "ahci", "top-ctrl";
 243                         reg = <0x181000 0xa9c>, <0x180020 0x1c>;
 244                         interrupt-parent = <&periph_intc>;
 245                         interrupts = <86>;
 246                         #address-cells = <1>;
 247                         #size-cells = <0>;
 248                         brcm,broken-ncq;
 249                         brcm,broken-phy;
 250                         status = "disabled";
 251
 252                         sata0: sata-port@0 {
 253                                 reg = <0>;
 254                                 phys = <&sata_phy0>;
 255                         };
 256
 257                         sata1: sata-port@1 {
 258                                 reg = <1>;
 259                                 phys = <&sata_phy1>;
 260                         };
 261                 };
 262
 263                 sata_phy: sata-phy@1800000 {
 264                         compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
 265                         reg = <0x180100 0x0eff>;
 266                         reg-names = "phy";
 267                         #address-cells = <1>;
 268                         #size-cells = <0>;
 269                         status = "disabled";
 270
 271                         sata_phy0: sata-phy@0 {
 272                                 reg = <0>;
 273                                 #phy-cells = <0>;
 274                         };
 275
 276                         sata_phy1: sata-phy@1 {
 277                                 reg = <1>;
 278                                 #phy-cells = <0>;
 279                         };
 280                 };
 281         };
 282 };