4 compatible = "brcm,bcm7362";
10 mips-hpt-frequency = <375000000>;
13 compatible = "brcm,bmips4380";
19 compatible = "brcm,bmips4380";
29 cpu_intc: interrupt-controller {
31 compatible = "mti,cpu-interrupt-controller";
34 #interrupt-cells = <1>;
39 compatible = "fixed-clock";
41 clock-frequency = <81000000>;
45 compatible = "fixed-clock";
47 clock-frequency = <27000000>;
55 compatible = "simple-bus";
56 ranges = <0 0x10000000 0x01000000>;
58 periph_intc: interrupt-controller@411400 {
59 compatible = "brcm,bcm7038-l1-intc";
60 reg = <0x411400 0x30>, <0x411600 0x30>;
63 #interrupt-cells = <1>;
65 interrupt-parent = <&cpu_intc>;
66 interrupts = <2>, <3>;
69 sun_l2_intc: interrupt-controller@403000 {
70 compatible = "brcm,l2-intc";
71 reg = <0x403000 0x30>;
73 #interrupt-cells = <1>;
74 interrupt-parent = <&periph_intc>;
79 compatible = "brcm,bcm7400-gisb-arb";
80 reg = <0x400000 0xdc>;
82 interrupt-parent = <&sun_l2_intc>;
83 interrupts = <0>, <2>;
84 brcm,gisb-arb-master-mask = <0x2f3>;
85 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
90 upg_irq0_intc: interrupt-controller@406600 {
91 compatible = "brcm,bcm7120-l2-intc";
94 brcm,int-map-mask = <0x44>, <0x7000000>;
95 brcm,int-fwd-mask = <0x70000>;
98 #interrupt-cells = <1>;
100 interrupt-parent = <&periph_intc>;
101 interrupts = <56>, <54>;
102 interrupt-names = "upg_main", "upg_bsc";
105 upg_aon_irq0_intc: interrupt-controller@408b80 {
106 compatible = "brcm,bcm7120-l2-intc";
107 reg = <0x408b80 0x8>;
109 brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
110 brcm,int-fwd-mask = <0>;
113 interrupt-controller;
114 #interrupt-cells = <1>;
116 interrupt-parent = <&periph_intc>;
117 interrupts = <57>, <55>, <59>;
118 interrupt-names = "upg_main_aon", "upg_bsc_aon",
122 sun_top_ctrl: syscon@404000 {
123 compatible = "brcm,bcm7362-sun-top-ctrl", "syscon";
124 reg = <0x404000 0x51c>;
129 compatible = "brcm,brcmstb-reboot";
130 syscon = <&sun_top_ctrl 0x304 0x308>;
133 uart0: serial@406800 {
134 compatible = "ns16550a";
135 reg = <0x406800 0x20>;
136 reg-io-width = <0x4>;
139 interrupt-parent = <&periph_intc>;
141 clocks = <&uart_clk>;
145 uart1: serial@406840 {
146 compatible = "ns16550a";
147 reg = <0x406840 0x20>;
148 reg-io-width = <0x4>;
151 interrupt-parent = <&periph_intc>;
153 clocks = <&uart_clk>;
157 uart2: serial@406880 {
158 compatible = "ns16550a";
159 reg = <0x406880 0x20>;
160 reg-io-width = <0x4>;
163 interrupt-parent = <&periph_intc>;
165 clocks = <&uart_clk>;
170 clock-frequency = <390000>;
171 compatible = "brcm,brcmstb-i2c";
172 interrupt-parent = <&upg_irq0_intc>;
173 reg = <0x406200 0x58>;
175 interrupt-names = "upg_bsca";
180 clock-frequency = <390000>;
181 compatible = "brcm,brcmstb-i2c";
182 interrupt-parent = <&upg_irq0_intc>;
183 reg = <0x406280 0x58>;
185 interrupt-names = "upg_bscb";
190 clock-frequency = <390000>;
191 compatible = "brcm,brcmstb-i2c";
192 interrupt-parent = <&upg_aon_irq0_intc>;
193 reg = <0x408980 0x58>;
195 interrupt-names = "upg_bscd";
200 compatible = "brcm,bcm7038-pwm";
201 reg = <0x406400 0x28>;
207 aon_pm_l2_intc: interrupt-controller@408440 {
208 compatible = "brcm,l2-intc";
209 reg = <0x408440 0x30>;
210 interrupt-controller;
211 #interrupt-cells = <1>;
212 interrupt-parent = <&periph_intc>;
217 upg_gio: gpio@406500 {
218 compatible = "brcm,brcmstb-gpio";
219 reg = <0x406500 0xa0>;
221 #interrupt-cells = <2>;
223 interrupt-controller;
224 interrupt-parent = <&upg_irq0_intc>;
226 brcm,gpio-bank-widths = <32 32 32 29 4>;
229 upg_gio_aon: gpio@408c00 {
230 compatible = "brcm,brcmstb-gpio";
231 reg = <0x408c00 0x60>;
233 #interrupt-cells = <2>;
235 interrupt-controller;
236 interrupt-parent = <&upg_aon_irq0_intc>;
238 interrupts-extended = <&upg_aon_irq0_intc 6>,
241 brcm,gpio-bank-widths = <21 32 2>;
244 enet0: ethernet@430000 {
245 phy-mode = "internal";
246 phy-handle = <&phy1>;
247 mac-address = [ 00 10 18 36 23 1a ];
248 compatible = "brcm,genet-v2";
249 #address-cells = <0x1>;
251 reg = <0x430000 0x4c8c>;
252 interrupts = <24>, <25>;
253 interrupt-parent = <&periph_intc>;
257 compatible = "brcm,genet-mdio-v2";
258 #address-cells = <0x1>;
262 phy1: ethernet-phy@1 {
265 compatible = "brcm,40nm-ephy",
266 "ethernet-phy-ieee802.3-c22";
272 compatible = "brcm,bcm7362-ehci", "generic-ehci";
273 reg = <0x480300 0x100>;
275 interrupt-parent = <&periph_intc>;
281 compatible = "brcm,bcm7362-ohci", "generic-ohci";
282 reg = <0x480400 0x100>;
285 interrupt-parent = <&periph_intc>;
290 hif_l2_intc: interrupt-controller@411000 {
291 compatible = "brcm,l2-intc";
292 reg = <0x411000 0x30>;
293 interrupt-controller;
294 #interrupt-cells = <1>;
295 interrupt-parent = <&periph_intc>;
300 compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
301 #address-cells = <1>;
304 reg = <0x412800 0x400>;
305 interrupt-parent = <&hif_l2_intc>;
311 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
312 reg-names = "ahci", "top-ctrl";
313 reg = <0x181000 0xa9c>, <0x180020 0x1c>;
314 interrupt-parent = <&periph_intc>;
316 #address-cells = <1>;
331 sata_phy: sata-phy@180100 {
332 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
333 reg = <0x180100 0x0eff>;
335 #address-cells = <1>;
339 sata_phy0: sata-phy@0 {
344 sata_phy1: sata-phy@1 {
350 sdhci0: sdhci@410000 {
351 compatible = "brcm,bcm7425-sdhci";
352 reg = <0x410000 0x100>;
353 interrupt-parent = <&periph_intc>;