3 /memreserve/ 0x00000000 0x00001000; // reserved
4 /memreserve/ 0x00001000 0x000ef000; // ROM data
5 /memreserve/ 0x000f0000 0x004cc000; // reserved
7 #include <dt-bindings/interrupt-controller/mips-gic.h>
12 compatible = "mti,sead-3";
13 interrupt-parent = <&gic>;
16 stdout-path = "uart1:115200";
26 compatible = "mti,mips14KEc", "mti,mips14Kc";
31 device_type = "memory";
32 reg = <0x0 0x08000000>;
35 cpu_intc: interrupt-controller {
36 compatible = "mti,cpu-interrupt-controller";
39 #interrupt-cells = <1>;
42 gic: interrupt-controller@1b1c0000 {
43 compatible = "mti,gic";
44 reg = <0x1b1c0000 0x20000>;
47 #interrupt-cells = <3>;
50 * Declare the interrupt-parent even though the mti,gic
51 * binding doesn't require it, such that the kernel can
52 * figure out that cpu_intc is the root interrupt
53 * controller & should be probed first.
55 interrupt-parent = <&cpu_intc>;
58 compatible = "mti,gic-timer";
59 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
64 compatible = "generic-ehci";
65 reg = <0x1b200000 0x1000>;
67 interrupts = <0>; /* GIC 0 or CPU 6 */
69 has-transaction-translator;
72 /* UART connected to FTDI & miniUSB socket */
73 uart0: uart@1f000900 {
74 compatible = "ns16550a";
75 reg = <0x1f000900 0x20>;
79 clock-frequency = <14745600>;
81 interrupts = <3>; /* GIC 3 or CPU 4 */
86 /* UART connected to RS232 socket */
87 uart1: uart@1f000800 {
88 compatible = "ns16550a";
89 reg = <0x1f000800 0x20>;
93 clock-frequency = <14745600>;
95 interrupts = <2>; /* GIC 2 or CPU 4 */
101 compatible = "smsc,lan9115";
102 reg = <0x1f010000 0x10000>;
105 interrupts = <0>; /* GIC 0 or CPU 6 */
109 smsc,save-mac-address;