arch/mips/boot/dts/mti/sead3.dts

   1 /dts-v1/;
   2
   3 /memreserve/ 0x00000000 0x00001000;     // reserved
   4 /memreserve/ 0x00001000 0x000ef000;     // ROM data
   5 /memreserve/ 0x000f0000 0x004cc000;     // reserved
   6
   7 #include <dt-bindings/interrupt-controller/mips-gic.h>
   8
   9 / {
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12         compatible = "mti,sead-3";
  13         interrupt-parent = <&gic>;
  14
  15         chosen {
  16                 stdout-path = "uart1:115200";
  17         };
  18
  19         aliases {
  20                 uart0 = &uart0;
  21                 uart1 = &uart1;
  22         };
  23
  24         cpus {
  25                 cpu@0 {
  26                         compatible = "mti,mips14KEc", "mti,mips14Kc";
  27                 };
  28         };
  29
  30         memory {
  31                 device_type = "memory";
  32                 reg = <0x0 0x08000000>;
  33         };
  34
  35         cpu_intc: interrupt-controller {
  36                 compatible = "mti,cpu-interrupt-controller";
  37
  38                 interrupt-controller;
  39                 #interrupt-cells = <1>;
  40         };
  41
  42         gic: interrupt-controller@1b1c0000 {
  43                 compatible = "mti,gic";
  44                 reg = <0x1b1c0000 0x20000>;
  45
  46                 interrupt-controller;
  47                 #interrupt-cells = <3>;
  48
  49                 /*
  50                  * Declare the interrupt-parent even though the mti,gic
  51                  * binding doesn't require it, such that the kernel can
  52                  * figure out that cpu_intc is the root interrupt
  53                  * controller & should be probed first.
  54                  */
  55                 interrupt-parent = <&cpu_intc>;
  56
  57                 timer {
  58                         compatible = "mti,gic-timer";
  59                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
  60                 };
  61         };
  62
  63         ehci@1b200000 {
  64                 compatible = "generic-ehci";
  65                 reg = <0x1b200000 0x1000>;
  66
  67                 interrupts = <0>; /* GIC 0 or CPU 6 */
  68
  69                 has-transaction-translator;
  70         };
  71
  72         flash@1c000000 {
  73                 compatible = "intel,28f128j3", "cfi-flash";
  74                 reg = <0x1c000000 0x2000000>;
  75                 #address-cells = <1>;
  76                 #size-cells = <1>;
  77                 bank-width = <4>;
  78
  79                 partitions {
  80                         compatible = "fixed-partitions";
  81                         #address-cells = <1>;
  82                         #size-cells = <1>;
  83
  84                         user-fs@0 {
  85                                 label = "User FS";
  86                                 reg = <0x0 0x1fc0000>;
  87                         };
  88
  89                         board-config@3e0000 {
  90                                 label = "Board Config";
  91                                 reg = <0x1fc0000 0x40000>;
  92                         };
  93                 };
  94         };
  95
  96         /* UART connected to FTDI & miniUSB socket */
  97         uart0: uart@1f000900 {
  98                 compatible = "ns16550a";
  99                 reg = <0x1f000900 0x20>;
 100                 reg-io-width = <4>;
 101                 reg-shift = <2>;
 102
 103                 clock-frequency = <14745600>;
 104
 105                 interrupts = <3>; /* GIC 3 or CPU 4 */
 106
 107                 no-loopback-test;
 108         };
 109
 110         /* UART connected to RS232 socket */
 111         uart1: uart@1f000800 {
 112                 compatible = "ns16550a";
 113                 reg = <0x1f000800 0x20>;
 114                 reg-io-width = <4>;
 115                 reg-shift = <2>;
 116
 117                 clock-frequency = <14745600>;
 118
 119                 interrupts = <2>; /* GIC 2 or CPU 4 */
 120
 121                 no-loopback-test;
 122         };
 123
 124         eth@1f010000 {
 125                 compatible = "smsc,lan9115";
 126                 reg = <0x1f010000 0x10000>;
 127                 reg-io-width = <4>;
 128
 129                 interrupts = <0>; /* GIC 0 or CPU 6 */
 130
 131                 phy-mode = "mii";
 132                 smsc,irq-push-pull;
 133                 smsc,save-mac-address;
 134         };
 135 };