2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2004-2014 Cavium, Inc.
9 #include <linux/of_address.h>
10 #include <linux/interrupt.h>
11 #include <linux/irqdomain.h>
12 #include <linux/bitops.h>
13 #include <linux/of_irq.h>
14 #include <linux/percpu.h>
15 #include <linux/slab.h>
16 #include <linux/irq.h>
17 #include <linux/smp.h>
20 #include <asm/octeon/octeon.h>
21 #include <asm/octeon/cvmx-ciu2-defs.h>
23 static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu0_en_mirror);
24 static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu1_en_mirror);
25 static DEFINE_PER_CPU(raw_spinlock_t, octeon_irq_ciu_spinlock);
27 struct octeon_irq_ciu_domain_data {
28 int num_sum; /* number of sum registers (2 or 3). */
31 static __read_mostly u8 octeon_irq_ciu_to_irq[8][64];
33 struct octeon_ciu_chip_data {
35 struct { /* only used for ciu3 */
39 struct { /* only used for ciu/ciu2 */
45 int current_cpu; /* Next CPU expected to take this irq */
48 struct octeon_core_chip_data {
49 struct mutex core_irq_mutex;
55 #define MIPS_CORE_IRQ_LINES 8
57 static struct octeon_core_chip_data octeon_irq_core_chip_data[MIPS_CORE_IRQ_LINES];
59 static int octeon_irq_set_ciu_mapping(int irq, int line, int bit, int gpio_line,
60 struct irq_chip *chip,
61 irq_flow_handler_t handler)
63 struct octeon_ciu_chip_data *cd;
65 cd = kzalloc(sizeof(*cd), GFP_KERNEL);
69 irq_set_chip_and_handler(irq, chip, handler);
73 cd->gpio_line = gpio_line;
75 irq_set_chip_data(irq, cd);
76 octeon_irq_ciu_to_irq[line][bit] = irq;
80 static void octeon_irq_free_cd(struct irq_domain *d, unsigned int irq)
82 struct irq_data *data = irq_get_irq_data(irq);
83 struct octeon_ciu_chip_data *cd = irq_data_get_irq_chip_data(data);
85 irq_set_chip_data(irq, NULL);
89 static int octeon_irq_force_ciu_mapping(struct irq_domain *domain,
90 int irq, int line, int bit)
92 return irq_domain_associate(domain, irq, line << 6 | bit);
95 static int octeon_coreid_for_cpu(int cpu)
98 return cpu_logical_map(cpu);
100 return cvmx_get_core_num();
104 static int octeon_cpu_for_coreid(int coreid)
107 return cpu_number_map(coreid);
109 return smp_processor_id();
113 static void octeon_irq_core_ack(struct irq_data *data)
115 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
116 unsigned int bit = cd->bit;
119 * We don't need to disable IRQs to make these atomic since
120 * they are already disabled earlier in the low level
123 clear_c0_status(0x100 << bit);
124 /* The two user interrupts must be cleared manually. */
126 clear_c0_cause(0x100 << bit);
129 static void octeon_irq_core_eoi(struct irq_data *data)
131 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
134 * We don't need to disable IRQs to make these atomic since
135 * they are already disabled earlier in the low level
138 set_c0_status(0x100 << cd->bit);
141 static void octeon_irq_core_set_enable_local(void *arg)
143 struct irq_data *data = arg;
144 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
145 unsigned int mask = 0x100 << cd->bit;
148 * Interrupts are already disabled, so these are atomic.
153 clear_c0_status(mask);
157 static void octeon_irq_core_disable(struct irq_data *data)
159 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
160 cd->desired_en = false;
163 static void octeon_irq_core_enable(struct irq_data *data)
165 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
166 cd->desired_en = true;
169 static void octeon_irq_core_bus_lock(struct irq_data *data)
171 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
173 mutex_lock(&cd->core_irq_mutex);
176 static void octeon_irq_core_bus_sync_unlock(struct irq_data *data)
178 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
180 if (cd->desired_en != cd->current_en) {
181 on_each_cpu(octeon_irq_core_set_enable_local, data, 1);
183 cd->current_en = cd->desired_en;
186 mutex_unlock(&cd->core_irq_mutex);
189 static struct irq_chip octeon_irq_chip_core = {
191 .irq_enable = octeon_irq_core_enable,
192 .irq_disable = octeon_irq_core_disable,
193 .irq_ack = octeon_irq_core_ack,
194 .irq_eoi = octeon_irq_core_eoi,
195 .irq_bus_lock = octeon_irq_core_bus_lock,
196 .irq_bus_sync_unlock = octeon_irq_core_bus_sync_unlock,
198 .irq_cpu_online = octeon_irq_core_eoi,
199 .irq_cpu_offline = octeon_irq_core_ack,
200 .flags = IRQCHIP_ONOFFLINE_ENABLED,
203 static void __init octeon_irq_init_core(void)
207 struct octeon_core_chip_data *cd;
209 for (i = 0; i < MIPS_CORE_IRQ_LINES; i++) {
210 cd = &octeon_irq_core_chip_data[i];
211 cd->current_en = false;
212 cd->desired_en = false;
214 mutex_init(&cd->core_irq_mutex);
216 irq = OCTEON_IRQ_SW0 + i;
217 irq_set_chip_data(irq, cd);
218 irq_set_chip_and_handler(irq, &octeon_irq_chip_core,
223 static int next_cpu_for_irq(struct irq_data *data)
228 int weight = cpumask_weight(data->affinity);
229 struct octeon_ciu_chip_data *cd = irq_data_get_irq_chip_data(data);
232 cpu = cd->current_cpu;
234 cpu = cpumask_next(cpu, data->affinity);
235 if (cpu >= nr_cpu_ids) {
238 } else if (cpumask_test_cpu(cpu, cpu_online_mask)) {
242 } else if (weight == 1) {
243 cpu = cpumask_first(data->affinity);
245 cpu = smp_processor_id();
247 cd->current_cpu = cpu;
250 return smp_processor_id();
254 static void octeon_irq_ciu_enable(struct irq_data *data)
256 int cpu = next_cpu_for_irq(data);
257 int coreid = octeon_coreid_for_cpu(cpu);
260 struct octeon_ciu_chip_data *cd;
261 raw_spinlock_t *lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
263 cd = irq_data_get_irq_chip_data(data);
265 raw_spin_lock_irqsave(lock, flags);
267 pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
268 __set_bit(cd->bit, pen);
270 * Must be visible to octeon_irq_ip{2,3}_ciu() before
274 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
276 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
277 __set_bit(cd->bit, pen);
279 * Must be visible to octeon_irq_ip{2,3}_ciu() before
283 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
285 raw_spin_unlock_irqrestore(lock, flags);
288 static void octeon_irq_ciu_enable_local(struct irq_data *data)
292 struct octeon_ciu_chip_data *cd;
293 raw_spinlock_t *lock = this_cpu_ptr(&octeon_irq_ciu_spinlock);
295 cd = irq_data_get_irq_chip_data(data);
297 raw_spin_lock_irqsave(lock, flags);
299 pen = this_cpu_ptr(&octeon_irq_ciu0_en_mirror);
300 __set_bit(cd->bit, pen);
302 * Must be visible to octeon_irq_ip{2,3}_ciu() before
306 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen);
308 pen = this_cpu_ptr(&octeon_irq_ciu1_en_mirror);
309 __set_bit(cd->bit, pen);
311 * Must be visible to octeon_irq_ip{2,3}_ciu() before
315 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen);
317 raw_spin_unlock_irqrestore(lock, flags);
320 static void octeon_irq_ciu_disable_local(struct irq_data *data)
324 struct octeon_ciu_chip_data *cd;
325 raw_spinlock_t *lock = this_cpu_ptr(&octeon_irq_ciu_spinlock);
327 cd = irq_data_get_irq_chip_data(data);
329 raw_spin_lock_irqsave(lock, flags);
331 pen = this_cpu_ptr(&octeon_irq_ciu0_en_mirror);
332 __clear_bit(cd->bit, pen);
334 * Must be visible to octeon_irq_ip{2,3}_ciu() before
338 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen);
340 pen = this_cpu_ptr(&octeon_irq_ciu1_en_mirror);
341 __clear_bit(cd->bit, pen);
343 * Must be visible to octeon_irq_ip{2,3}_ciu() before
347 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen);
349 raw_spin_unlock_irqrestore(lock, flags);
352 static void octeon_irq_ciu_disable_all(struct irq_data *data)
357 struct octeon_ciu_chip_data *cd;
358 raw_spinlock_t *lock;
360 cd = irq_data_get_irq_chip_data(data);
362 for_each_online_cpu(cpu) {
363 int coreid = octeon_coreid_for_cpu(cpu);
364 lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
366 pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
368 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
370 raw_spin_lock_irqsave(lock, flags);
371 __clear_bit(cd->bit, pen);
373 * Must be visible to octeon_irq_ip{2,3}_ciu() before
378 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
380 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
381 raw_spin_unlock_irqrestore(lock, flags);
385 static void octeon_irq_ciu_enable_all(struct irq_data *data)
390 struct octeon_ciu_chip_data *cd;
391 raw_spinlock_t *lock;
393 cd = irq_data_get_irq_chip_data(data);
395 for_each_online_cpu(cpu) {
396 int coreid = octeon_coreid_for_cpu(cpu);
397 lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
399 pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
401 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
403 raw_spin_lock_irqsave(lock, flags);
404 __set_bit(cd->bit, pen);
406 * Must be visible to octeon_irq_ip{2,3}_ciu() before
411 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
413 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
414 raw_spin_unlock_irqrestore(lock, flags);
419 * Enable the irq on the next core in the affinity set for chips that
420 * have the EN*_W1{S,C} registers.
422 static void octeon_irq_ciu_enable_v2(struct irq_data *data)
425 int cpu = next_cpu_for_irq(data);
426 struct octeon_ciu_chip_data *cd;
428 cd = irq_data_get_irq_chip_data(data);
429 mask = 1ull << (cd->bit);
432 * Called under the desc lock, so these should never get out
436 int index = octeon_coreid_for_cpu(cpu) * 2;
437 set_bit(cd->bit, &per_cpu(octeon_irq_ciu0_en_mirror, cpu));
438 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
440 int index = octeon_coreid_for_cpu(cpu) * 2 + 1;
441 set_bit(cd->bit, &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
442 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
447 * Enable the irq in the sum2 registers.
449 static void octeon_irq_ciu_enable_sum2(struct irq_data *data)
452 int cpu = next_cpu_for_irq(data);
453 int index = octeon_coreid_for_cpu(cpu);
454 struct octeon_ciu_chip_data *cd;
456 cd = irq_data_get_irq_chip_data(data);
457 mask = 1ull << (cd->bit);
459 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1S(index), mask);
463 * Disable the irq in the sum2 registers.
465 static void octeon_irq_ciu_disable_local_sum2(struct irq_data *data)
468 int cpu = next_cpu_for_irq(data);
469 int index = octeon_coreid_for_cpu(cpu);
470 struct octeon_ciu_chip_data *cd;
472 cd = irq_data_get_irq_chip_data(data);
473 mask = 1ull << (cd->bit);
475 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1C(index), mask);
478 static void octeon_irq_ciu_ack_sum2(struct irq_data *data)
481 int cpu = next_cpu_for_irq(data);
482 int index = octeon_coreid_for_cpu(cpu);
483 struct octeon_ciu_chip_data *cd;
485 cd = irq_data_get_irq_chip_data(data);
486 mask = 1ull << (cd->bit);
488 cvmx_write_csr(CVMX_CIU_SUM2_PPX_IP4(index), mask);
491 static void octeon_irq_ciu_disable_all_sum2(struct irq_data *data)
494 struct octeon_ciu_chip_data *cd;
497 cd = irq_data_get_irq_chip_data(data);
498 mask = 1ull << (cd->bit);
500 for_each_online_cpu(cpu) {
501 int coreid = octeon_coreid_for_cpu(cpu);
503 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1C(coreid), mask);
508 * Enable the irq on the current CPU for chips that
509 * have the EN*_W1{S,C} registers.
511 static void octeon_irq_ciu_enable_local_v2(struct irq_data *data)
514 struct octeon_ciu_chip_data *cd;
516 cd = irq_data_get_irq_chip_data(data);
517 mask = 1ull << (cd->bit);
520 int index = cvmx_get_core_num() * 2;
521 set_bit(cd->bit, this_cpu_ptr(&octeon_irq_ciu0_en_mirror));
522 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
524 int index = cvmx_get_core_num() * 2 + 1;
525 set_bit(cd->bit, this_cpu_ptr(&octeon_irq_ciu1_en_mirror));
526 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
530 static void octeon_irq_ciu_disable_local_v2(struct irq_data *data)
533 struct octeon_ciu_chip_data *cd;
535 cd = irq_data_get_irq_chip_data(data);
536 mask = 1ull << (cd->bit);
539 int index = cvmx_get_core_num() * 2;
540 clear_bit(cd->bit, this_cpu_ptr(&octeon_irq_ciu0_en_mirror));
541 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
543 int index = cvmx_get_core_num() * 2 + 1;
544 clear_bit(cd->bit, this_cpu_ptr(&octeon_irq_ciu1_en_mirror));
545 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
550 * Write to the W1C bit in CVMX_CIU_INTX_SUM0 to clear the irq.
552 static void octeon_irq_ciu_ack(struct irq_data *data)
555 struct octeon_ciu_chip_data *cd;
557 cd = irq_data_get_irq_chip_data(data);
558 mask = 1ull << (cd->bit);
561 int index = cvmx_get_core_num() * 2;
562 cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
564 cvmx_write_csr(CVMX_CIU_INT_SUM1, mask);
569 * Disable the irq on the all cores for chips that have the EN*_W1{S,C}
572 static void octeon_irq_ciu_disable_all_v2(struct irq_data *data)
576 struct octeon_ciu_chip_data *cd;
578 cd = irq_data_get_irq_chip_data(data);
579 mask = 1ull << (cd->bit);
582 for_each_online_cpu(cpu) {
583 int index = octeon_coreid_for_cpu(cpu) * 2;
585 &per_cpu(octeon_irq_ciu0_en_mirror, cpu));
586 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
589 for_each_online_cpu(cpu) {
590 int index = octeon_coreid_for_cpu(cpu) * 2 + 1;
592 &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
593 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
599 * Enable the irq on the all cores for chips that have the EN*_W1{S,C}
602 static void octeon_irq_ciu_enable_all_v2(struct irq_data *data)
606 struct octeon_ciu_chip_data *cd;
608 cd = irq_data_get_irq_chip_data(data);
609 mask = 1ull << (cd->bit);
612 for_each_online_cpu(cpu) {
613 int index = octeon_coreid_for_cpu(cpu) * 2;
615 &per_cpu(octeon_irq_ciu0_en_mirror, cpu));
616 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
619 for_each_online_cpu(cpu) {
620 int index = octeon_coreid_for_cpu(cpu) * 2 + 1;
622 &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
623 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
628 static void octeon_irq_gpio_setup(struct irq_data *data)
630 union cvmx_gpio_bit_cfgx cfg;
631 struct octeon_ciu_chip_data *cd;
632 u32 t = irqd_get_trigger_type(data);
634 cd = irq_data_get_irq_chip_data(data);
638 cfg.s.int_type = (t & IRQ_TYPE_EDGE_BOTH) != 0;
639 cfg.s.rx_xor = (t & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) != 0;
641 /* 140 nS glitch filter*/
645 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), cfg.u64);
648 static void octeon_irq_ciu_enable_gpio_v2(struct irq_data *data)
650 octeon_irq_gpio_setup(data);
651 octeon_irq_ciu_enable_v2(data);
654 static void octeon_irq_ciu_enable_gpio(struct irq_data *data)
656 octeon_irq_gpio_setup(data);
657 octeon_irq_ciu_enable(data);
660 static int octeon_irq_ciu_gpio_set_type(struct irq_data *data, unsigned int t)
662 irqd_set_trigger_type(data, t);
663 octeon_irq_gpio_setup(data);
665 return IRQ_SET_MASK_OK;
668 static void octeon_irq_ciu_disable_gpio_v2(struct irq_data *data)
670 struct octeon_ciu_chip_data *cd;
672 cd = irq_data_get_irq_chip_data(data);
673 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0);
675 octeon_irq_ciu_disable_all_v2(data);
678 static void octeon_irq_ciu_disable_gpio(struct irq_data *data)
680 struct octeon_ciu_chip_data *cd;
682 cd = irq_data_get_irq_chip_data(data);
683 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0);
685 octeon_irq_ciu_disable_all(data);
688 static void octeon_irq_ciu_gpio_ack(struct irq_data *data)
690 struct octeon_ciu_chip_data *cd;
693 cd = irq_data_get_irq_chip_data(data);
694 mask = 1ull << (cd->gpio_line);
696 cvmx_write_csr(CVMX_GPIO_INT_CLR, mask);
699 static void octeon_irq_handle_trigger(unsigned int irq, struct irq_desc *desc)
701 struct irq_data *data = irq_desc_get_irq_data(desc);
703 if (irqd_get_trigger_type(data) & IRQ_TYPE_EDGE_BOTH)
704 handle_edge_irq(irq, desc);
706 handle_level_irq(irq, desc);
711 static void octeon_irq_cpu_offline_ciu(struct irq_data *data)
713 int cpu = smp_processor_id();
714 cpumask_t new_affinity;
716 if (!cpumask_test_cpu(cpu, data->affinity))
719 if (cpumask_weight(data->affinity) > 1) {
721 * It has multi CPU affinity, just remove this CPU
722 * from the affinity set.
724 cpumask_copy(&new_affinity, data->affinity);
725 cpumask_clear_cpu(cpu, &new_affinity);
727 /* Otherwise, put it on lowest numbered online CPU. */
728 cpumask_clear(&new_affinity);
729 cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity);
731 irq_set_affinity_locked(data, &new_affinity, false);
734 static int octeon_irq_ciu_set_affinity(struct irq_data *data,
735 const struct cpumask *dest, bool force)
738 bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data);
740 struct octeon_ciu_chip_data *cd;
742 raw_spinlock_t *lock;
744 cd = irq_data_get_irq_chip_data(data);
747 * For non-v2 CIU, we will allow only single CPU affinity.
748 * This removes the need to do locking in the .ack/.eoi
751 if (cpumask_weight(dest) != 1)
758 for_each_online_cpu(cpu) {
759 int coreid = octeon_coreid_for_cpu(cpu);
761 lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
762 raw_spin_lock_irqsave(lock, flags);
765 pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
767 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
769 if (cpumask_test_cpu(cpu, dest) && enable_one) {
771 __set_bit(cd->bit, pen);
773 __clear_bit(cd->bit, pen);
776 * Must be visible to octeon_irq_ip{2,3}_ciu() before
782 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
784 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
786 raw_spin_unlock_irqrestore(lock, flags);
792 * Set affinity for the irq for chips that have the EN*_W1{S,C}
795 static int octeon_irq_ciu_set_affinity_v2(struct irq_data *data,
796 const struct cpumask *dest,
800 bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data);
802 struct octeon_ciu_chip_data *cd;
807 cd = irq_data_get_irq_chip_data(data);
808 mask = 1ull << cd->bit;
811 for_each_online_cpu(cpu) {
812 unsigned long *pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
813 int index = octeon_coreid_for_cpu(cpu) * 2;
814 if (cpumask_test_cpu(cpu, dest) && enable_one) {
816 set_bit(cd->bit, pen);
817 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
819 clear_bit(cd->bit, pen);
820 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
824 for_each_online_cpu(cpu) {
825 unsigned long *pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
826 int index = octeon_coreid_for_cpu(cpu) * 2 + 1;
827 if (cpumask_test_cpu(cpu, dest) && enable_one) {
829 set_bit(cd->bit, pen);
830 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
832 clear_bit(cd->bit, pen);
833 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
840 static int octeon_irq_ciu_set_affinity_sum2(struct irq_data *data,
841 const struct cpumask *dest,
845 bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data);
847 struct octeon_ciu_chip_data *cd;
852 cd = irq_data_get_irq_chip_data(data);
853 mask = 1ull << cd->bit;
855 for_each_online_cpu(cpu) {
856 int index = octeon_coreid_for_cpu(cpu);
858 if (cpumask_test_cpu(cpu, dest) && enable_one) {
860 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1S(index), mask);
862 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1C(index), mask);
870 * Newer octeon chips have support for lockless CIU operation.
872 static struct irq_chip octeon_irq_chip_ciu_v2 = {
874 .irq_enable = octeon_irq_ciu_enable_v2,
875 .irq_disable = octeon_irq_ciu_disable_all_v2,
876 .irq_mask = octeon_irq_ciu_disable_local_v2,
877 .irq_unmask = octeon_irq_ciu_enable_v2,
879 .irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
880 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
884 static struct irq_chip octeon_irq_chip_ciu_v2_edge = {
886 .irq_enable = octeon_irq_ciu_enable_v2,
887 .irq_disable = octeon_irq_ciu_disable_all_v2,
888 .irq_ack = octeon_irq_ciu_ack,
889 .irq_mask = octeon_irq_ciu_disable_local_v2,
890 .irq_unmask = octeon_irq_ciu_enable_v2,
892 .irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
893 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
898 * Newer octeon chips have support for lockless CIU operation.
900 static struct irq_chip octeon_irq_chip_ciu_sum2 = {
902 .irq_enable = octeon_irq_ciu_enable_sum2,
903 .irq_disable = octeon_irq_ciu_disable_all_sum2,
904 .irq_mask = octeon_irq_ciu_disable_local_sum2,
905 .irq_unmask = octeon_irq_ciu_enable_sum2,
907 .irq_set_affinity = octeon_irq_ciu_set_affinity_sum2,
908 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
912 static struct irq_chip octeon_irq_chip_ciu_sum2_edge = {
914 .irq_enable = octeon_irq_ciu_enable_sum2,
915 .irq_disable = octeon_irq_ciu_disable_all_sum2,
916 .irq_ack = octeon_irq_ciu_ack_sum2,
917 .irq_mask = octeon_irq_ciu_disable_local_sum2,
918 .irq_unmask = octeon_irq_ciu_enable_sum2,
920 .irq_set_affinity = octeon_irq_ciu_set_affinity_sum2,
921 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
925 static struct irq_chip octeon_irq_chip_ciu = {
927 .irq_enable = octeon_irq_ciu_enable,
928 .irq_disable = octeon_irq_ciu_disable_all,
929 .irq_mask = octeon_irq_ciu_disable_local,
930 .irq_unmask = octeon_irq_ciu_enable,
932 .irq_set_affinity = octeon_irq_ciu_set_affinity,
933 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
937 static struct irq_chip octeon_irq_chip_ciu_edge = {
939 .irq_enable = octeon_irq_ciu_enable,
940 .irq_disable = octeon_irq_ciu_disable_all,
941 .irq_ack = octeon_irq_ciu_ack,
942 .irq_mask = octeon_irq_ciu_disable_local,
943 .irq_unmask = octeon_irq_ciu_enable,
945 .irq_set_affinity = octeon_irq_ciu_set_affinity,
946 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
950 /* The mbox versions don't do any affinity or round-robin. */
951 static struct irq_chip octeon_irq_chip_ciu_mbox_v2 = {
953 .irq_enable = octeon_irq_ciu_enable_all_v2,
954 .irq_disable = octeon_irq_ciu_disable_all_v2,
955 .irq_ack = octeon_irq_ciu_disable_local_v2,
956 .irq_eoi = octeon_irq_ciu_enable_local_v2,
958 .irq_cpu_online = octeon_irq_ciu_enable_local_v2,
959 .irq_cpu_offline = octeon_irq_ciu_disable_local_v2,
960 .flags = IRQCHIP_ONOFFLINE_ENABLED,
963 static struct irq_chip octeon_irq_chip_ciu_mbox = {
965 .irq_enable = octeon_irq_ciu_enable_all,
966 .irq_disable = octeon_irq_ciu_disable_all,
967 .irq_ack = octeon_irq_ciu_disable_local,
968 .irq_eoi = octeon_irq_ciu_enable_local,
970 .irq_cpu_online = octeon_irq_ciu_enable_local,
971 .irq_cpu_offline = octeon_irq_ciu_disable_local,
972 .flags = IRQCHIP_ONOFFLINE_ENABLED,
975 static struct irq_chip octeon_irq_chip_ciu_gpio_v2 = {
977 .irq_enable = octeon_irq_ciu_enable_gpio_v2,
978 .irq_disable = octeon_irq_ciu_disable_gpio_v2,
979 .irq_ack = octeon_irq_ciu_gpio_ack,
980 .irq_mask = octeon_irq_ciu_disable_local_v2,
981 .irq_unmask = octeon_irq_ciu_enable_v2,
982 .irq_set_type = octeon_irq_ciu_gpio_set_type,
984 .irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
985 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
987 .flags = IRQCHIP_SET_TYPE_MASKED,
990 static struct irq_chip octeon_irq_chip_ciu_gpio = {
992 .irq_enable = octeon_irq_ciu_enable_gpio,
993 .irq_disable = octeon_irq_ciu_disable_gpio,
994 .irq_mask = octeon_irq_ciu_disable_local,
995 .irq_unmask = octeon_irq_ciu_enable,
996 .irq_ack = octeon_irq_ciu_gpio_ack,
997 .irq_set_type = octeon_irq_ciu_gpio_set_type,
999 .irq_set_affinity = octeon_irq_ciu_set_affinity,
1000 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
1002 .flags = IRQCHIP_SET_TYPE_MASKED,
1006 * Watchdog interrupts are special. They are associated with a single
1007 * core, so we hardwire the affinity to that core.
1009 static void octeon_irq_ciu_wd_enable(struct irq_data *data)
1011 unsigned long flags;
1013 int coreid = data->irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
1014 int cpu = octeon_cpu_for_coreid(coreid);
1015 raw_spinlock_t *lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
1017 raw_spin_lock_irqsave(lock, flags);
1018 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
1019 __set_bit(coreid, pen);
1021 * Must be visible to octeon_irq_ip{2,3}_ciu() before enabling
1025 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
1026 raw_spin_unlock_irqrestore(lock, flags);
1030 * Watchdog interrupts are special. They are associated with a single
1031 * core, so we hardwire the affinity to that core.
1033 static void octeon_irq_ciu1_wd_enable_v2(struct irq_data *data)
1035 int coreid = data->irq - OCTEON_IRQ_WDOG0;
1036 int cpu = octeon_cpu_for_coreid(coreid);
1038 set_bit(coreid, &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
1039 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(coreid * 2 + 1), 1ull << coreid);
1043 static struct irq_chip octeon_irq_chip_ciu_wd_v2 = {
1045 .irq_enable = octeon_irq_ciu1_wd_enable_v2,
1046 .irq_disable = octeon_irq_ciu_disable_all_v2,
1047 .irq_mask = octeon_irq_ciu_disable_local_v2,
1048 .irq_unmask = octeon_irq_ciu_enable_local_v2,
1051 static struct irq_chip octeon_irq_chip_ciu_wd = {
1053 .irq_enable = octeon_irq_ciu_wd_enable,
1054 .irq_disable = octeon_irq_ciu_disable_all,
1055 .irq_mask = octeon_irq_ciu_disable_local,
1056 .irq_unmask = octeon_irq_ciu_enable_local,
1059 static bool octeon_irq_ciu_is_edge(unsigned int line, unsigned int bit)
1065 case 48 ... 49: /* GMX DRP */
1066 case 50: /* IPD_DRP */
1067 case 52 ... 55: /* Timers */
1074 else /* line == 1 */
1085 struct octeon_irq_gpio_domain_data {
1086 unsigned int base_hwirq;
1089 static int octeon_irq_gpio_xlat(struct irq_domain *d,
1090 struct device_node *node,
1092 unsigned int intsize,
1093 unsigned long *out_hwirq,
1094 unsigned int *out_type)
1098 unsigned int trigger;
1100 if (d->of_node != node)
1110 trigger = intspec[1];
1114 type = IRQ_TYPE_EDGE_RISING;
1117 type = IRQ_TYPE_EDGE_FALLING;
1120 type = IRQ_TYPE_LEVEL_HIGH;
1123 type = IRQ_TYPE_LEVEL_LOW;
1126 pr_err("Error: (%s) Invalid irq trigger specification: %x\n",
1129 type = IRQ_TYPE_LEVEL_LOW;
1138 static int octeon_irq_ciu_xlat(struct irq_domain *d,
1139 struct device_node *node,
1141 unsigned int intsize,
1142 unsigned long *out_hwirq,
1143 unsigned int *out_type)
1145 unsigned int ciu, bit;
1146 struct octeon_irq_ciu_domain_data *dd = d->host_data;
1151 if (ciu >= dd->num_sum || bit > 63)
1154 *out_hwirq = (ciu << 6) | bit;
1160 static struct irq_chip *octeon_irq_ciu_chip;
1161 static struct irq_chip *octeon_irq_ciu_chip_edge;
1162 static struct irq_chip *octeon_irq_gpio_chip;
1164 static bool octeon_irq_virq_in_range(unsigned int virq)
1166 /* We cannot let it overflow the mapping array. */
1167 if (virq < (1ul << 8 * sizeof(octeon_irq_ciu_to_irq[0][0])))
1170 WARN_ONCE(true, "virq out of range %u.\n", virq);
1174 static int octeon_irq_ciu_map(struct irq_domain *d,
1175 unsigned int virq, irq_hw_number_t hw)
1178 unsigned int line = hw >> 6;
1179 unsigned int bit = hw & 63;
1180 struct octeon_irq_ciu_domain_data *dd = d->host_data;
1182 if (!octeon_irq_virq_in_range(virq))
1185 /* Don't map irq if it is reserved for GPIO. */
1186 if (line == 0 && bit >= 16 && bit <32)
1189 if (line >= dd->num_sum || octeon_irq_ciu_to_irq[line][bit] != 0)
1193 if (octeon_irq_ciu_is_edge(line, bit))
1194 rv = octeon_irq_set_ciu_mapping(virq, line, bit, 0,
1195 &octeon_irq_chip_ciu_sum2_edge,
1198 rv = octeon_irq_set_ciu_mapping(virq, line, bit, 0,
1199 &octeon_irq_chip_ciu_sum2,
1202 if (octeon_irq_ciu_is_edge(line, bit))
1203 rv = octeon_irq_set_ciu_mapping(virq, line, bit, 0,
1204 octeon_irq_ciu_chip_edge,
1207 rv = octeon_irq_set_ciu_mapping(virq, line, bit, 0,
1208 octeon_irq_ciu_chip,
1214 static int octeon_irq_gpio_map(struct irq_domain *d,
1215 unsigned int virq, irq_hw_number_t hw)
1217 struct octeon_irq_gpio_domain_data *gpiod = d->host_data;
1218 unsigned int line, bit;
1221 if (!octeon_irq_virq_in_range(virq))
1224 line = (hw + gpiod->base_hwirq) >> 6;
1225 bit = (hw + gpiod->base_hwirq) & 63;
1226 if (line > ARRAY_SIZE(octeon_irq_ciu_to_irq) ||
1227 octeon_irq_ciu_to_irq[line][bit] != 0)
1230 r = octeon_irq_set_ciu_mapping(virq, line, bit, hw,
1231 octeon_irq_gpio_chip, octeon_irq_handle_trigger);
1235 static struct irq_domain_ops octeon_irq_domain_ciu_ops = {
1236 .map = octeon_irq_ciu_map,
1237 .unmap = octeon_irq_free_cd,
1238 .xlate = octeon_irq_ciu_xlat,
1241 static struct irq_domain_ops octeon_irq_domain_gpio_ops = {
1242 .map = octeon_irq_gpio_map,
1243 .unmap = octeon_irq_free_cd,
1244 .xlate = octeon_irq_gpio_xlat,
1247 static void octeon_irq_ip2_ciu(void)
1249 const unsigned long core_id = cvmx_get_core_num();
1250 u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core_id * 2));
1252 ciu_sum &= __this_cpu_read(octeon_irq_ciu0_en_mirror);
1253 if (likely(ciu_sum)) {
1254 int bit = fls64(ciu_sum) - 1;
1255 int irq = octeon_irq_ciu_to_irq[0][bit];
1259 spurious_interrupt();
1261 spurious_interrupt();
1265 static void octeon_irq_ip3_ciu(void)
1267 u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1);
1269 ciu_sum &= __this_cpu_read(octeon_irq_ciu1_en_mirror);
1270 if (likely(ciu_sum)) {
1271 int bit = fls64(ciu_sum) - 1;
1272 int irq = octeon_irq_ciu_to_irq[1][bit];
1276 spurious_interrupt();
1278 spurious_interrupt();
1282 static void octeon_irq_ip4_ciu(void)
1284 int coreid = cvmx_get_core_num();
1285 u64 ciu_sum = cvmx_read_csr(CVMX_CIU_SUM2_PPX_IP4(coreid));
1286 u64 ciu_en = cvmx_read_csr(CVMX_CIU_EN2_PPX_IP4(coreid));
1289 if (likely(ciu_sum)) {
1290 int bit = fls64(ciu_sum) - 1;
1291 int irq = octeon_irq_ciu_to_irq[2][bit];
1296 spurious_interrupt();
1298 spurious_interrupt();
1302 static bool octeon_irq_use_ip4;
1304 static void octeon_irq_local_enable_ip4(void *arg)
1306 set_c0_status(STATUSF_IP4);
1309 static void octeon_irq_ip4_mask(void)
1311 clear_c0_status(STATUSF_IP4);
1312 spurious_interrupt();
1315 static void (*octeon_irq_ip2)(void);
1316 static void (*octeon_irq_ip3)(void);
1317 static void (*octeon_irq_ip4)(void);
1319 void (*octeon_irq_setup_secondary)(void);
1321 void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t h)
1324 octeon_irq_use_ip4 = true;
1325 on_each_cpu(octeon_irq_local_enable_ip4, NULL, 1);
1328 static void octeon_irq_percpu_enable(void)
1333 static void octeon_irq_init_ciu_percpu(void)
1335 int coreid = cvmx_get_core_num();
1338 __this_cpu_write(octeon_irq_ciu0_en_mirror, 0);
1339 __this_cpu_write(octeon_irq_ciu1_en_mirror, 0);
1341 raw_spin_lock_init(this_cpu_ptr(&octeon_irq_ciu_spinlock));
1343 * Disable All CIU Interrupts. The ones we need will be
1344 * enabled later. Read the SUM register so we know the write
1347 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0);
1348 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);
1349 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);
1350 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);
1351 cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2)));
1354 static void octeon_irq_init_ciu2_percpu(void)
1357 int coreid = cvmx_get_core_num();
1358 u64 base = CVMX_CIU2_EN_PPX_IP2_WRKQ(coreid);
1361 * Disable All CIU2 Interrupts. The ones we need will be
1362 * enabled later. Read the SUM register so we know the write
1365 * There are 9 registers and 3 IPX levels with strides 0x1000
1366 * and 0x200 respectivly. Use loops to clear them.
1368 for (regx = 0; regx <= 0x8000; regx += 0x1000) {
1369 for (ipx = 0; ipx <= 0x400; ipx += 0x200)
1370 cvmx_write_csr(base + regx + ipx, 0);
1373 cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid));
1376 static void octeon_irq_setup_secondary_ciu(void)
1378 octeon_irq_init_ciu_percpu();
1379 octeon_irq_percpu_enable();
1381 /* Enable the CIU lines */
1382 set_c0_status(STATUSF_IP3 | STATUSF_IP2);
1383 if (octeon_irq_use_ip4)
1384 set_c0_status(STATUSF_IP4);
1386 clear_c0_status(STATUSF_IP4);
1389 static void octeon_irq_setup_secondary_ciu2(void)
1391 octeon_irq_init_ciu2_percpu();
1392 octeon_irq_percpu_enable();
1394 /* Enable the CIU lines */
1395 set_c0_status(STATUSF_IP3 | STATUSF_IP2);
1396 if (octeon_irq_use_ip4)
1397 set_c0_status(STATUSF_IP4);
1399 clear_c0_status(STATUSF_IP4);
1402 static int __init octeon_irq_init_ciu(
1403 struct device_node *ciu_node, struct device_node *parent)
1406 struct irq_chip *chip;
1407 struct irq_chip *chip_edge;
1408 struct irq_chip *chip_mbox;
1409 struct irq_chip *chip_wd;
1410 struct irq_domain *ciu_domain = NULL;
1411 struct octeon_irq_ciu_domain_data *dd;
1413 dd = kzalloc(sizeof(*dd), GFP_KERNEL);
1417 octeon_irq_init_ciu_percpu();
1418 octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu;
1420 octeon_irq_ip2 = octeon_irq_ip2_ciu;
1421 octeon_irq_ip3 = octeon_irq_ip3_ciu;
1422 if ((OCTEON_IS_OCTEON2() || OCTEON_IS_OCTEON3())
1423 && !OCTEON_IS_MODEL(OCTEON_CN63XX)) {
1424 octeon_irq_ip4 = octeon_irq_ip4_ciu;
1426 octeon_irq_use_ip4 = true;
1428 octeon_irq_ip4 = octeon_irq_ip4_mask;
1430 octeon_irq_use_ip4 = false;
1432 if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) ||
1433 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
1434 OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) ||
1435 OCTEON_IS_OCTEON2() || OCTEON_IS_OCTEON3()) {
1436 chip = &octeon_irq_chip_ciu_v2;
1437 chip_edge = &octeon_irq_chip_ciu_v2_edge;
1438 chip_mbox = &octeon_irq_chip_ciu_mbox_v2;
1439 chip_wd = &octeon_irq_chip_ciu_wd_v2;
1440 octeon_irq_gpio_chip = &octeon_irq_chip_ciu_gpio_v2;
1442 chip = &octeon_irq_chip_ciu;
1443 chip_edge = &octeon_irq_chip_ciu_edge;
1444 chip_mbox = &octeon_irq_chip_ciu_mbox;
1445 chip_wd = &octeon_irq_chip_ciu_wd;
1446 octeon_irq_gpio_chip = &octeon_irq_chip_ciu_gpio;
1448 octeon_irq_ciu_chip = chip;
1449 octeon_irq_ciu_chip_edge = chip_edge;
1452 octeon_irq_init_core();
1454 ciu_domain = irq_domain_add_tree(
1455 ciu_node, &octeon_irq_domain_ciu_ops, dd);
1456 irq_set_default_host(ciu_domain);
1459 for (i = 0; i < 16; i++) {
1460 r = octeon_irq_force_ciu_mapping(
1461 ciu_domain, i + OCTEON_IRQ_WORKQ0, 0, i + 0);
1466 r = octeon_irq_set_ciu_mapping(
1467 OCTEON_IRQ_MBOX0, 0, 32, 0, chip_mbox, handle_percpu_irq);
1470 r = octeon_irq_set_ciu_mapping(
1471 OCTEON_IRQ_MBOX1, 0, 33, 0, chip_mbox, handle_percpu_irq);
1475 for (i = 0; i < 4; i++) {
1476 r = octeon_irq_force_ciu_mapping(
1477 ciu_domain, i + OCTEON_IRQ_PCI_INT0, 0, i + 36);
1481 for (i = 0; i < 4; i++) {
1482 r = octeon_irq_force_ciu_mapping(
1483 ciu_domain, i + OCTEON_IRQ_PCI_MSI0, 0, i + 40);
1488 r = octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_TWSI, 0, 45);
1492 r = octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_RML, 0, 46);
1496 for (i = 0; i < 4; i++) {
1497 r = octeon_irq_force_ciu_mapping(
1498 ciu_domain, i + OCTEON_IRQ_TIMER0, 0, i + 52);
1503 r = octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB0, 0, 56);
1507 r = octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_TWSI2, 0, 59);
1512 for (i = 0; i < 16; i++) {
1513 r = octeon_irq_set_ciu_mapping(
1514 i + OCTEON_IRQ_WDOG0, 1, i + 0, 0, chip_wd,
1520 r = octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB1, 1, 17);
1524 /* Enable the CIU lines */
1525 set_c0_status(STATUSF_IP3 | STATUSF_IP2);
1526 if (octeon_irq_use_ip4)
1527 set_c0_status(STATUSF_IP4);
1529 clear_c0_status(STATUSF_IP4);
1536 static int __init octeon_irq_init_gpio(
1537 struct device_node *gpio_node, struct device_node *parent)
1539 struct octeon_irq_gpio_domain_data *gpiod;
1540 u32 interrupt_cells;
1541 unsigned int base_hwirq;
1544 r = of_property_read_u32(parent, "#interrupt-cells", &interrupt_cells);
1548 if (interrupt_cells == 1) {
1551 r = of_property_read_u32_index(gpio_node, "interrupts", 0, &v);
1553 pr_warn("No \"interrupts\" property.\n");
1557 } else if (interrupt_cells == 2) {
1560 r = of_property_read_u32_index(gpio_node, "interrupts", 0, &v0);
1562 pr_warn("No \"interrupts\" property.\n");
1565 r = of_property_read_u32_index(gpio_node, "interrupts", 1, &v1);
1567 pr_warn("No \"interrupts\" property.\n");
1570 base_hwirq = (v0 << 6) | v1;
1572 pr_warn("Bad \"#interrupt-cells\" property: %u\n",
1577 gpiod = kzalloc(sizeof(*gpiod), GFP_KERNEL);
1579 /* gpio domain host_data is the base hwirq number. */
1580 gpiod->base_hwirq = base_hwirq;
1581 irq_domain_add_linear(
1582 gpio_node, 16, &octeon_irq_domain_gpio_ops, gpiod);
1584 pr_warn("Cannot allocate memory for GPIO irq_domain.\n");
1591 * Watchdog interrupts are special. They are associated with a single
1592 * core, so we hardwire the affinity to that core.
1594 static void octeon_irq_ciu2_wd_enable(struct irq_data *data)
1598 int coreid = data->irq - OCTEON_IRQ_WDOG0;
1599 struct octeon_ciu_chip_data *cd;
1601 cd = irq_data_get_irq_chip_data(data);
1602 mask = 1ull << (cd->bit);
1604 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(coreid) +
1605 (0x1000ull * cd->line);
1606 cvmx_write_csr(en_addr, mask);
1610 static void octeon_irq_ciu2_enable(struct irq_data *data)
1614 int cpu = next_cpu_for_irq(data);
1615 int coreid = octeon_coreid_for_cpu(cpu);
1616 struct octeon_ciu_chip_data *cd;
1618 cd = irq_data_get_irq_chip_data(data);
1619 mask = 1ull << (cd->bit);
1621 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(coreid) +
1622 (0x1000ull * cd->line);
1623 cvmx_write_csr(en_addr, mask);
1626 static void octeon_irq_ciu2_enable_local(struct irq_data *data)
1630 int coreid = cvmx_get_core_num();
1631 struct octeon_ciu_chip_data *cd;
1633 cd = irq_data_get_irq_chip_data(data);
1634 mask = 1ull << (cd->bit);
1636 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(coreid) +
1637 (0x1000ull * cd->line);
1638 cvmx_write_csr(en_addr, mask);
1642 static void octeon_irq_ciu2_disable_local(struct irq_data *data)
1646 int coreid = cvmx_get_core_num();
1647 struct octeon_ciu_chip_data *cd;
1649 cd = irq_data_get_irq_chip_data(data);
1650 mask = 1ull << (cd->bit);
1652 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(coreid) +
1653 (0x1000ull * cd->line);
1654 cvmx_write_csr(en_addr, mask);
1658 static void octeon_irq_ciu2_ack(struct irq_data *data)
1662 int coreid = cvmx_get_core_num();
1663 struct octeon_ciu_chip_data *cd;
1665 cd = irq_data_get_irq_chip_data(data);
1666 mask = 1ull << (cd->bit);
1668 en_addr = CVMX_CIU2_RAW_PPX_IP2_WRKQ(coreid) + (0x1000ull * cd->line);
1669 cvmx_write_csr(en_addr, mask);
1673 static void octeon_irq_ciu2_disable_all(struct irq_data *data)
1677 struct octeon_ciu_chip_data *cd;
1679 cd = irq_data_get_irq_chip_data(data);
1680 mask = 1ull << (cd->bit);
1682 for_each_online_cpu(cpu) {
1683 u64 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(
1684 octeon_coreid_for_cpu(cpu)) + (0x1000ull * cd->line);
1685 cvmx_write_csr(en_addr, mask);
1689 static void octeon_irq_ciu2_mbox_enable_all(struct irq_data *data)
1694 mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0);
1696 for_each_online_cpu(cpu) {
1697 u64 en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(
1698 octeon_coreid_for_cpu(cpu));
1699 cvmx_write_csr(en_addr, mask);
1703 static void octeon_irq_ciu2_mbox_disable_all(struct irq_data *data)
1708 mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0);
1710 for_each_online_cpu(cpu) {
1711 u64 en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(
1712 octeon_coreid_for_cpu(cpu));
1713 cvmx_write_csr(en_addr, mask);
1717 static void octeon_irq_ciu2_mbox_enable_local(struct irq_data *data)
1721 int coreid = cvmx_get_core_num();
1723 mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0);
1724 en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(coreid);
1725 cvmx_write_csr(en_addr, mask);
1728 static void octeon_irq_ciu2_mbox_disable_local(struct irq_data *data)
1732 int coreid = cvmx_get_core_num();
1734 mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0);
1735 en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(coreid);
1736 cvmx_write_csr(en_addr, mask);
1740 static int octeon_irq_ciu2_set_affinity(struct irq_data *data,
1741 const struct cpumask *dest, bool force)
1744 bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data);
1746 struct octeon_ciu_chip_data *cd;
1751 cd = irq_data_get_irq_chip_data(data);
1752 mask = 1ull << cd->bit;
1754 for_each_online_cpu(cpu) {
1756 if (cpumask_test_cpu(cpu, dest) && enable_one) {
1758 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(
1759 octeon_coreid_for_cpu(cpu)) +
1760 (0x1000ull * cd->line);
1762 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(
1763 octeon_coreid_for_cpu(cpu)) +
1764 (0x1000ull * cd->line);
1766 cvmx_write_csr(en_addr, mask);
1773 static void octeon_irq_ciu2_enable_gpio(struct irq_data *data)
1775 octeon_irq_gpio_setup(data);
1776 octeon_irq_ciu2_enable(data);
1779 static void octeon_irq_ciu2_disable_gpio(struct irq_data *data)
1781 struct octeon_ciu_chip_data *cd;
1783 cd = irq_data_get_irq_chip_data(data);
1785 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0);
1787 octeon_irq_ciu2_disable_all(data);
1790 static struct irq_chip octeon_irq_chip_ciu2 = {
1792 .irq_enable = octeon_irq_ciu2_enable,
1793 .irq_disable = octeon_irq_ciu2_disable_all,
1794 .irq_mask = octeon_irq_ciu2_disable_local,
1795 .irq_unmask = octeon_irq_ciu2_enable,
1797 .irq_set_affinity = octeon_irq_ciu2_set_affinity,
1798 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
1802 static struct irq_chip octeon_irq_chip_ciu2_edge = {
1804 .irq_enable = octeon_irq_ciu2_enable,
1805 .irq_disable = octeon_irq_ciu2_disable_all,
1806 .irq_ack = octeon_irq_ciu2_ack,
1807 .irq_mask = octeon_irq_ciu2_disable_local,
1808 .irq_unmask = octeon_irq_ciu2_enable,
1810 .irq_set_affinity = octeon_irq_ciu2_set_affinity,
1811 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
1815 static struct irq_chip octeon_irq_chip_ciu2_mbox = {
1817 .irq_enable = octeon_irq_ciu2_mbox_enable_all,
1818 .irq_disable = octeon_irq_ciu2_mbox_disable_all,
1819 .irq_ack = octeon_irq_ciu2_mbox_disable_local,
1820 .irq_eoi = octeon_irq_ciu2_mbox_enable_local,
1822 .irq_cpu_online = octeon_irq_ciu2_mbox_enable_local,
1823 .irq_cpu_offline = octeon_irq_ciu2_mbox_disable_local,
1824 .flags = IRQCHIP_ONOFFLINE_ENABLED,
1827 static struct irq_chip octeon_irq_chip_ciu2_wd = {
1829 .irq_enable = octeon_irq_ciu2_wd_enable,
1830 .irq_disable = octeon_irq_ciu2_disable_all,
1831 .irq_mask = octeon_irq_ciu2_disable_local,
1832 .irq_unmask = octeon_irq_ciu2_enable_local,
1835 static struct irq_chip octeon_irq_chip_ciu2_gpio = {
1837 .irq_enable = octeon_irq_ciu2_enable_gpio,
1838 .irq_disable = octeon_irq_ciu2_disable_gpio,
1839 .irq_ack = octeon_irq_ciu_gpio_ack,
1840 .irq_mask = octeon_irq_ciu2_disable_local,
1841 .irq_unmask = octeon_irq_ciu2_enable,
1842 .irq_set_type = octeon_irq_ciu_gpio_set_type,
1844 .irq_set_affinity = octeon_irq_ciu2_set_affinity,
1845 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
1847 .flags = IRQCHIP_SET_TYPE_MASKED,
1850 static int octeon_irq_ciu2_xlat(struct irq_domain *d,
1851 struct device_node *node,
1853 unsigned int intsize,
1854 unsigned long *out_hwirq,
1855 unsigned int *out_type)
1857 unsigned int ciu, bit;
1862 *out_hwirq = (ciu << 6) | bit;
1868 static bool octeon_irq_ciu2_is_edge(unsigned int line, unsigned int bit)
1872 if (line == 3) /* MIO */
1874 case 2: /* IPD_DRP */
1875 case 8 ... 11: /* Timers */
1882 else if (line == 6) /* PKT */
1884 case 52 ... 53: /* ILK_DRP */
1885 case 8 ... 12: /* GMX_DRP */
1894 static int octeon_irq_ciu2_map(struct irq_domain *d,
1895 unsigned int virq, irq_hw_number_t hw)
1897 unsigned int line = hw >> 6;
1898 unsigned int bit = hw & 63;
1900 if (!octeon_irq_virq_in_range(virq))
1904 * Don't map irq if it is reserved for GPIO.
1905 * (Line 7 are the GPIO lines.)
1910 if (line > 7 || octeon_irq_ciu_to_irq[line][bit] != 0)
1913 if (octeon_irq_ciu2_is_edge(line, bit))
1914 octeon_irq_set_ciu_mapping(virq, line, bit, 0,
1915 &octeon_irq_chip_ciu2_edge,
1918 octeon_irq_set_ciu_mapping(virq, line, bit, 0,
1919 &octeon_irq_chip_ciu2,
1925 static struct irq_domain_ops octeon_irq_domain_ciu2_ops = {
1926 .map = octeon_irq_ciu2_map,
1927 .unmap = octeon_irq_free_cd,
1928 .xlate = octeon_irq_ciu2_xlat,
1931 static void octeon_irq_ciu2(void)
1936 u64 src_reg, src, sum;
1937 const unsigned long core_id = cvmx_get_core_num();
1939 sum = cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(core_id)) & 0xfful;
1944 line = fls64(sum) - 1;
1945 src_reg = CVMX_CIU2_SRC_PPX_IP2_WRKQ(core_id) + (0x1000 * line);
1946 src = cvmx_read_csr(src_reg);
1951 bit = fls64(src) - 1;
1952 irq = octeon_irq_ciu_to_irq[line][bit];
1960 spurious_interrupt();
1962 /* CN68XX pass 1.x has an errata that accessing the ACK registers
1963 can stop interrupts from propagating */
1964 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
1965 cvmx_read_csr(CVMX_CIU2_INTR_CIU_READY);
1967 cvmx_read_csr(CVMX_CIU2_ACK_PPX_IP2(core_id));
1971 static void octeon_irq_ciu2_mbox(void)
1975 const unsigned long core_id = cvmx_get_core_num();
1976 u64 sum = cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP3(core_id)) >> 60;
1981 line = fls64(sum) - 1;
1983 do_IRQ(OCTEON_IRQ_MBOX0 + line);
1987 spurious_interrupt();
1989 /* CN68XX pass 1.x has an errata that accessing the ACK registers
1990 can stop interrupts from propagating */
1991 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
1992 cvmx_read_csr(CVMX_CIU2_INTR_CIU_READY);
1994 cvmx_read_csr(CVMX_CIU2_ACK_PPX_IP3(core_id));
1998 static int __init octeon_irq_init_ciu2(
1999 struct device_node *ciu_node, struct device_node *parent)
2002 struct irq_domain *ciu_domain = NULL;
2004 octeon_irq_init_ciu2_percpu();
2005 octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu2;
2007 octeon_irq_gpio_chip = &octeon_irq_chip_ciu2_gpio;
2008 octeon_irq_ip2 = octeon_irq_ciu2;
2009 octeon_irq_ip3 = octeon_irq_ciu2_mbox;
2010 octeon_irq_ip4 = octeon_irq_ip4_mask;
2013 octeon_irq_init_core();
2015 ciu_domain = irq_domain_add_tree(
2016 ciu_node, &octeon_irq_domain_ciu2_ops, NULL);
2017 irq_set_default_host(ciu_domain);
2020 for (i = 0; i < 64; i++) {
2021 r = octeon_irq_force_ciu_mapping(
2022 ciu_domain, i + OCTEON_IRQ_WORKQ0, 0, i);
2027 for (i = 0; i < 32; i++) {
2028 r = octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i, 0,
2029 &octeon_irq_chip_ciu2_wd, handle_level_irq);
2034 for (i = 0; i < 4; i++) {
2035 r = octeon_irq_force_ciu_mapping(
2036 ciu_domain, i + OCTEON_IRQ_TIMER0, 3, i + 8);
2041 r = octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB0, 3, 44);
2045 for (i = 0; i < 4; i++) {
2046 r = octeon_irq_force_ciu_mapping(
2047 ciu_domain, i + OCTEON_IRQ_PCI_INT0, 4, i);
2052 for (i = 0; i < 4; i++) {
2053 r = octeon_irq_force_ciu_mapping(
2054 ciu_domain, i + OCTEON_IRQ_PCI_MSI0, 4, i + 8);
2059 irq_set_chip_and_handler(OCTEON_IRQ_MBOX0, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq);
2060 irq_set_chip_and_handler(OCTEON_IRQ_MBOX1, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq);
2061 irq_set_chip_and_handler(OCTEON_IRQ_MBOX2, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq);
2062 irq_set_chip_and_handler(OCTEON_IRQ_MBOX3, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq);
2064 /* Enable the CIU lines */
2065 set_c0_status(STATUSF_IP3 | STATUSF_IP2);
2066 clear_c0_status(STATUSF_IP4);
2072 struct octeon_irq_cib_host_data {
2073 raw_spinlock_t lock;
2079 struct octeon_irq_cib_chip_data {
2080 struct octeon_irq_cib_host_data *host_data;
2084 static void octeon_irq_cib_enable(struct irq_data *data)
2086 unsigned long flags;
2088 struct octeon_irq_cib_chip_data *cd = irq_data_get_irq_chip_data(data);
2089 struct octeon_irq_cib_host_data *host_data = cd->host_data;
2091 raw_spin_lock_irqsave(&host_data->lock, flags);
2092 en = cvmx_read_csr(host_data->en_reg);
2093 en |= 1ull << cd->bit;
2094 cvmx_write_csr(host_data->en_reg, en);
2095 raw_spin_unlock_irqrestore(&host_data->lock, flags);
2098 static void octeon_irq_cib_disable(struct irq_data *data)
2100 unsigned long flags;
2102 struct octeon_irq_cib_chip_data *cd = irq_data_get_irq_chip_data(data);
2103 struct octeon_irq_cib_host_data *host_data = cd->host_data;
2105 raw_spin_lock_irqsave(&host_data->lock, flags);
2106 en = cvmx_read_csr(host_data->en_reg);
2107 en &= ~(1ull << cd->bit);
2108 cvmx_write_csr(host_data->en_reg, en);
2109 raw_spin_unlock_irqrestore(&host_data->lock, flags);
2112 static int octeon_irq_cib_set_type(struct irq_data *data, unsigned int t)
2114 irqd_set_trigger_type(data, t);
2115 return IRQ_SET_MASK_OK;
2118 static struct irq_chip octeon_irq_chip_cib = {
2120 .irq_enable = octeon_irq_cib_enable,
2121 .irq_disable = octeon_irq_cib_disable,
2122 .irq_mask = octeon_irq_cib_disable,
2123 .irq_unmask = octeon_irq_cib_enable,
2124 .irq_set_type = octeon_irq_cib_set_type,
2127 static int octeon_irq_cib_xlat(struct irq_domain *d,
2128 struct device_node *node,
2130 unsigned int intsize,
2131 unsigned long *out_hwirq,
2132 unsigned int *out_type)
2134 unsigned int type = 0;
2140 case 0: /* unofficial value, but we might as well let it work. */
2141 case 4: /* official value for level triggering. */
2142 *out_type = IRQ_TYPE_LEVEL_HIGH;
2144 case 1: /* official value for edge triggering. */
2145 *out_type = IRQ_TYPE_EDGE_RISING;
2147 default: /* Nothing else is acceptable. */
2151 *out_hwirq = intspec[0];
2156 static int octeon_irq_cib_map(struct irq_domain *d,
2157 unsigned int virq, irq_hw_number_t hw)
2159 struct octeon_irq_cib_host_data *host_data = d->host_data;
2160 struct octeon_irq_cib_chip_data *cd;
2162 if (hw >= host_data->max_bits) {
2163 pr_err("ERROR: %s mapping %u is to big!\n",
2164 d->of_node->name, (unsigned)hw);
2168 cd = kzalloc(sizeof(*cd), GFP_KERNEL);
2169 cd->host_data = host_data;
2172 irq_set_chip_and_handler(virq, &octeon_irq_chip_cib,
2174 irq_set_chip_data(virq, cd);
2178 static struct irq_domain_ops octeon_irq_domain_cib_ops = {
2179 .map = octeon_irq_cib_map,
2180 .unmap = octeon_irq_free_cd,
2181 .xlate = octeon_irq_cib_xlat,
2184 /* Chain to real handler. */
2185 static irqreturn_t octeon_irq_cib_handler(int my_irq, void *data)
2192 struct irq_domain *cib_domain = data;
2193 struct octeon_irq_cib_host_data *host_data = cib_domain->host_data;
2195 en = cvmx_read_csr(host_data->en_reg);
2196 raw = cvmx_read_csr(host_data->raw_reg);
2200 for (i = 0; i < host_data->max_bits; i++) {
2201 if ((bits & 1ull << i) == 0)
2203 irq = irq_find_mapping(cib_domain, i);
2205 unsigned long flags;
2207 pr_err("ERROR: CIB bit %d@%llx IRQ unhandled, disabling\n",
2208 i, host_data->raw_reg);
2209 raw_spin_lock_irqsave(&host_data->lock, flags);
2210 en = cvmx_read_csr(host_data->en_reg);
2212 cvmx_write_csr(host_data->en_reg, en);
2213 cvmx_write_csr(host_data->raw_reg, 1ull << i);
2214 raw_spin_unlock_irqrestore(&host_data->lock, flags);
2216 struct irq_desc *desc = irq_to_desc(irq);
2217 struct irq_data *irq_data = irq_desc_get_irq_data(desc);
2218 /* If edge, acknowledge the bit we will be sending. */
2219 if (irqd_get_trigger_type(irq_data) &
2221 cvmx_write_csr(host_data->raw_reg, 1ull << i);
2222 generic_handle_irq_desc(irq, desc);
2229 static int __init octeon_irq_init_cib(struct device_node *ciu_node,
2230 struct device_node *parent)
2234 struct octeon_irq_cib_host_data *host_data;
2237 struct irq_domain *cib_domain;
2239 parent_irq = irq_of_parse_and_map(ciu_node, 0);
2241 pr_err("ERROR: Couldn't acquire parent_irq for %s\n.",
2246 host_data = kzalloc(sizeof(*host_data), GFP_KERNEL);
2247 raw_spin_lock_init(&host_data->lock);
2249 addr = of_get_address(ciu_node, 0, NULL, NULL);
2251 pr_err("ERROR: Couldn't acquire reg(0) %s\n.", ciu_node->name);
2254 host_data->raw_reg = (u64)phys_to_virt(
2255 of_translate_address(ciu_node, addr));
2257 addr = of_get_address(ciu_node, 1, NULL, NULL);
2259 pr_err("ERROR: Couldn't acquire reg(1) %s\n.", ciu_node->name);
2262 host_data->en_reg = (u64)phys_to_virt(
2263 of_translate_address(ciu_node, addr));
2265 r = of_property_read_u32(ciu_node, "cavium,max-bits", &val);
2267 pr_err("ERROR: Couldn't read cavium,max-bits from %s\n.",
2271 host_data->max_bits = val;
2273 cib_domain = irq_domain_add_linear(ciu_node, host_data->max_bits,
2274 &octeon_irq_domain_cib_ops,
2277 pr_err("ERROR: Couldn't irq_domain_add_linear()\n.");
2281 cvmx_write_csr(host_data->en_reg, 0); /* disable all IRQs */
2282 cvmx_write_csr(host_data->raw_reg, ~0); /* ack any outstanding */
2284 r = request_irq(parent_irq, octeon_irq_cib_handler,
2285 IRQF_NO_THREAD, "cib", cib_domain);
2287 pr_err("request_irq cib failed %d\n", r);
2290 pr_info("CIB interrupt controller probed: %llx %d\n",
2291 host_data->raw_reg, host_data->max_bits);
2295 static struct of_device_id ciu_types[] __initdata = {
2296 {.compatible = "cavium,octeon-3860-ciu", .data = octeon_irq_init_ciu},
2297 {.compatible = "cavium,octeon-3860-gpio", .data = octeon_irq_init_gpio},
2298 {.compatible = "cavium,octeon-6880-ciu2", .data = octeon_irq_init_ciu2},
2299 {.compatible = "cavium,octeon-7130-cib", .data = octeon_irq_init_cib},
2303 void __init arch_init_irq(void)
2306 /* Set the default affinity to the boot cpu. */
2307 cpumask_clear(irq_default_affinity);
2308 cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
2310 of_irq_init(ciu_types);
2313 asmlinkage void plat_irq_dispatch(void)
2315 unsigned long cop0_cause;
2316 unsigned long cop0_status;
2319 cop0_cause = read_c0_cause();
2320 cop0_status = read_c0_status();
2321 cop0_cause &= cop0_status;
2322 cop0_cause &= ST0_IM;
2324 if (cop0_cause & STATUSF_IP2)
2326 else if (cop0_cause & STATUSF_IP3)
2328 else if (cop0_cause & STATUSF_IP4)
2330 else if (cop0_cause)
2331 do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE);
2337 #ifdef CONFIG_HOTPLUG_CPU
2339 void octeon_fixup_irqs(void)
2344 #endif /* CONFIG_HOTPLUG_CPU */