2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2004-2010 Cavium Networks
7 * Copyright (C) 2008 Wind River Systems
10 #include <linux/init.h>
11 #include <linux/irq.h>
12 #include <linux/i2c.h>
13 #include <linux/usb.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
18 #include <asm/octeon/octeon.h>
19 #include <asm/octeon/cvmx-rnm-defs.h>
21 static struct octeon_cf_data octeon_cf_data;
23 static int __init octeon_cf_device_init(void)
25 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
26 unsigned long base_ptr, region_base, region_size;
27 struct platform_device *pd;
28 struct resource cf_resources[3];
29 unsigned int num_resources;
33 /* Setup octeon-cf platform device if present. */
35 if (octeon_bootinfo->major_version == 1
36 && octeon_bootinfo->minor_version >= 1) {
37 if (octeon_bootinfo->compact_flash_common_base_addr)
39 octeon_bootinfo->compact_flash_common_base_addr;
41 base_ptr = 0x1d000800;
47 /* Find CS0 region. */
48 for (i = 0; i < 8; i++) {
49 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i));
50 region_base = mio_boot_reg_cfg.s.base << 16;
51 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
52 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
53 && base_ptr < region_base + region_size)
57 /* i and i + 1 are CS0 and CS1, both must be less than 8. */
60 octeon_cf_data.base_region = i;
61 octeon_cf_data.is16bit = mio_boot_reg_cfg.s.width;
62 octeon_cf_data.base_region_bias = base_ptr - region_base;
63 memset(cf_resources, 0, sizeof(cf_resources));
65 cf_resources[num_resources].flags = IORESOURCE_MEM;
66 cf_resources[num_resources].start = region_base;
67 cf_resources[num_resources].end = region_base + region_size - 1;
71 if (!(base_ptr & 0xfffful)) {
73 * Boot loader signals availability of DMA (true_ide
74 * mode) by setting low order bits of base_ptr to
78 /* Assume that CS1 immediately follows. */
79 mio_boot_reg_cfg.u64 =
80 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1));
81 region_base = mio_boot_reg_cfg.s.base << 16;
82 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
83 if (!mio_boot_reg_cfg.s.en)
86 cf_resources[num_resources].flags = IORESOURCE_MEM;
87 cf_resources[num_resources].start = region_base;
88 cf_resources[num_resources].end = region_base + region_size - 1;
91 octeon_cf_data.dma_engine = 0;
92 cf_resources[num_resources].flags = IORESOURCE_IRQ;
93 cf_resources[num_resources].start = OCTEON_IRQ_BOOTDMA;
94 cf_resources[num_resources].end = OCTEON_IRQ_BOOTDMA;
97 octeon_cf_data.dma_engine = -1;
100 pd = platform_device_alloc("pata_octeon_cf", -1);
105 pd->dev.platform_data = &octeon_cf_data;
107 ret = platform_device_add_resources(pd, cf_resources, num_resources);
111 ret = platform_device_add(pd);
117 platform_device_put(pd);
121 device_initcall(octeon_cf_device_init);
123 /* Octeon Random Number Generator. */
124 static int __init octeon_rng_device_init(void)
126 struct platform_device *pd;
129 struct resource rng_resources[] = {
131 .flags = IORESOURCE_MEM,
132 .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
133 .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
135 .flags = IORESOURCE_MEM,
136 .start = cvmx_build_io_address(8, 0),
137 .end = cvmx_build_io_address(8, 0) + 0x7
141 pd = platform_device_alloc("octeon_rng", -1);
147 ret = platform_device_add_resources(pd, rng_resources,
148 ARRAY_SIZE(rng_resources));
152 ret = platform_device_add(pd);
158 platform_device_put(pd);
163 device_initcall(octeon_rng_device_init);
165 static struct i2c_board_info __initdata octeon_i2c_devices[] = {
167 I2C_BOARD_INFO("ds1337", 0x68),
171 static int __init octeon_i2c_devices_init(void)
173 return i2c_register_board_info(0, octeon_i2c_devices,
174 ARRAY_SIZE(octeon_i2c_devices));
176 arch_initcall(octeon_i2c_devices_init);
178 #define OCTEON_I2C_IO_BASE 0x1180000001000ull
179 #define OCTEON_I2C_IO_UNIT_OFFSET 0x200
181 static struct octeon_i2c_data octeon_i2c_data[2];
183 static int __init octeon_i2c_device_init(void)
185 struct platform_device *pd;
189 struct resource i2c_resources[] = {
191 .flags = IORESOURCE_MEM,
193 .flags = IORESOURCE_IRQ,
197 if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
202 for (port = 0; port < num_ports; port++) {
203 octeon_i2c_data[port].sys_freq = octeon_get_io_clock_rate();
204 /*FIXME: should be examined. At the moment is set for 100Khz */
205 octeon_i2c_data[port].i2c_freq = 100000;
207 pd = platform_device_alloc("i2c-octeon", port);
213 pd->dev.platform_data = octeon_i2c_data + port;
215 i2c_resources[0].start =
216 OCTEON_I2C_IO_BASE + (port * OCTEON_I2C_IO_UNIT_OFFSET);
217 i2c_resources[0].end = i2c_resources[0].start + 0x1f;
220 i2c_resources[1].start = OCTEON_IRQ_TWSI;
221 i2c_resources[1].end = OCTEON_IRQ_TWSI;
224 i2c_resources[1].start = OCTEON_IRQ_TWSI2;
225 i2c_resources[1].end = OCTEON_IRQ_TWSI2;
231 ret = platform_device_add_resources(pd,
233 ARRAY_SIZE(i2c_resources));
237 ret = platform_device_add(pd);
243 platform_device_put(pd);
247 device_initcall(octeon_i2c_device_init);
249 /* Octeon SMI/MDIO interface. */
250 static int __init octeon_mdiobus_device_init(void)
252 struct platform_device *pd;
255 if (octeon_is_simulation())
256 return 0; /* No mdio in the simulator. */
258 /* The bus number is the platform_device id. */
259 pd = platform_device_alloc("mdio-octeon", 0);
265 ret = platform_device_add(pd);
271 platform_device_put(pd);
277 device_initcall(octeon_mdiobus_device_init);
279 /* Octeon mgmt port Ethernet interface. */
280 static int __init octeon_mgmt_device_init(void)
282 struct platform_device *pd;
286 struct resource mgmt_port_resource = {
287 .flags = IORESOURCE_IRQ,
292 if (!OCTEON_IS_MODEL(OCTEON_CN56XX) && !OCTEON_IS_MODEL(OCTEON_CN52XX))
295 if (OCTEON_IS_MODEL(OCTEON_CN56XX))
300 for (port = 0; port < num_ports; port++) {
301 pd = platform_device_alloc("octeon_mgmt", port);
306 /* No DMA restrictions */
307 pd->dev.coherent_dma_mask = DMA_BIT_MASK(64);
308 pd->dev.dma_mask = &pd->dev.coherent_dma_mask;
312 mgmt_port_resource.start = OCTEON_IRQ_MII0;
315 mgmt_port_resource.start = OCTEON_IRQ_MII1;
320 mgmt_port_resource.end = mgmt_port_resource.start;
322 ret = platform_device_add_resources(pd, &mgmt_port_resource, 1);
327 ret = platform_device_add(pd);
333 platform_device_put(pd);
339 device_initcall(octeon_mgmt_device_init);
343 static int __init octeon_ehci_device_init(void)
345 struct platform_device *pd;
348 struct resource usb_resources[] = {
350 .flags = IORESOURCE_MEM,
352 .flags = IORESOURCE_IRQ,
356 /* Only Octeon2 has ehci/ohci */
357 if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
360 if (octeon_is_simulation() || usb_disabled())
361 return 0; /* No USB in the simulator. */
363 pd = platform_device_alloc("octeon-ehci", 0);
369 usb_resources[0].start = 0x00016F0000000000ULL;
370 usb_resources[0].end = usb_resources[0].start + 0x100;
372 usb_resources[1].start = OCTEON_IRQ_USB0;
373 usb_resources[1].end = OCTEON_IRQ_USB0;
375 ret = platform_device_add_resources(pd, usb_resources,
376 ARRAY_SIZE(usb_resources));
380 ret = platform_device_add(pd);
386 platform_device_put(pd);
390 device_initcall(octeon_ehci_device_init);
392 static int __init octeon_ohci_device_init(void)
394 struct platform_device *pd;
397 struct resource usb_resources[] = {
399 .flags = IORESOURCE_MEM,
401 .flags = IORESOURCE_IRQ,
405 /* Only Octeon2 has ehci/ohci */
406 if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
409 if (octeon_is_simulation() || usb_disabled())
410 return 0; /* No USB in the simulator. */
412 pd = platform_device_alloc("octeon-ohci", 0);
418 usb_resources[0].start = 0x00016F0000000400ULL;
419 usb_resources[0].end = usb_resources[0].start + 0x100;
421 usb_resources[1].start = OCTEON_IRQ_USB0;
422 usb_resources[1].end = OCTEON_IRQ_USB0;
424 ret = platform_device_add_resources(pd, usb_resources,
425 ARRAY_SIZE(usb_resources));
429 ret = platform_device_add(pd);
435 platform_device_put(pd);
439 device_initcall(octeon_ohci_device_init);
441 #endif /* CONFIG_USB */
443 MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
444 MODULE_LICENSE("GPL");
445 MODULE_DESCRIPTION("Platform driver for Octeon SOC");