2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
9 #include <linux/init.h>
10 #include <linux/delay.h>
11 #include <linux/smp.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel_stat.h>
14 #include <linux/sched.h>
15 #include <linux/module.h>
17 #include <asm/mmu_context.h>
19 #include <asm/setup.h>
21 #include <asm/octeon/octeon.h>
23 #include "octeon_boot.h"
25 volatile unsigned long octeon_processor_boot = 0xff;
26 volatile unsigned long octeon_processor_sp;
27 volatile unsigned long octeon_processor_gp;
29 #ifdef CONFIG_HOTPLUG_CPU
30 uint64_t octeon_bootloader_entry_addr;
31 EXPORT_SYMBOL(octeon_bootloader_entry_addr);
34 static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
36 const int coreid = cvmx_get_core_num();
39 /* Load the mailbox register to figure out what we're supposed to do */
40 action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid)) & 0xffff;
42 /* Clear the mailbox to clear the interrupt */
43 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action);
45 if (action & SMP_CALL_FUNCTION)
46 smp_call_function_interrupt();
47 if (action & SMP_RESCHEDULE_YOURSELF)
50 /* Check if we've been told to flush the icache */
51 if (action & SMP_ICACHE_FLUSH)
52 asm volatile ("synci 0($0)\n");
57 * Cause the function described by call_data to be executed on the passed
58 * cpu. When the function has finished, increment the finished field of
61 void octeon_send_ipi_single(int cpu, unsigned int action)
63 int coreid = cpu_logical_map(cpu);
65 pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu,
68 cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
71 static inline void octeon_send_ipi_mask(const struct cpumask *mask,
76 for_each_cpu_mask(i, *mask)
77 octeon_send_ipi_single(i, action);
81 * Detect available CPUs, populate cpu_possible_mask
83 static void octeon_smp_hotplug_setup(void)
85 #ifdef CONFIG_HOTPLUG_CPU
86 struct linux_app_boot_info *labi;
88 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
89 if (labi->labi_signature != LABI_SIGNATURE)
90 panic("The bootloader version on this board is incorrect.");
92 octeon_bootloader_entry_addr = labi->InitTLBStart_addr;
96 static void octeon_smp_setup(void)
98 const int coreid = cvmx_get_core_num();
101 int core_mask = octeon_get_boot_coremask();
102 #ifdef CONFIG_HOTPLUG_CPU
103 unsigned int num_cores = cvmx_octeon_num_cores();
106 /* The present CPUs are initially just the boot cpu (CPU 0). */
107 for (id = 0; id < NR_CPUS; id++) {
108 set_cpu_possible(id, id == 0);
109 set_cpu_present(id, id == 0);
112 __cpu_number_map[coreid] = 0;
113 __cpu_logical_map[0] = coreid;
115 /* The present CPUs get the lowest CPU numbers. */
117 for (id = 0; id < NR_CPUS; id++) {
118 if ((id != coreid) && (core_mask & (1 << id))) {
119 set_cpu_possible(cpus, true);
120 set_cpu_present(cpus, true);
121 __cpu_number_map[id] = cpus;
122 __cpu_logical_map[cpus] = id;
127 #ifdef CONFIG_HOTPLUG_CPU
129 * The possible CPUs are all those present on the chip. We
130 * will assign CPU numbers for possible cores as well. Cores
131 * are always consecutively numberd from 0.
133 for (id = 0; id < num_cores && id < NR_CPUS; id++) {
134 if (!(core_mask & (1 << id))) {
135 set_cpu_possible(cpus, true);
136 __cpu_number_map[id] = cpus;
137 __cpu_logical_map[cpus] = id;
143 octeon_smp_hotplug_setup();
147 * Firmware CPU startup hook
150 static void octeon_boot_secondary(int cpu, struct task_struct *idle)
154 pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu,
155 cpu_logical_map(cpu));
157 octeon_processor_sp = __KSTK_TOS(idle);
158 octeon_processor_gp = (unsigned long)(task_thread_info(idle));
159 octeon_processor_boot = cpu_logical_map(cpu);
163 while (octeon_processor_sp && count) {
164 /* Waiting for processor to get the SP and GP */
169 pr_err("Secondary boot timeout\n");
173 * After we've done initial boot, this function is called to allow the
174 * board code to clean up state, if needed
176 static void octeon_init_secondary(void)
180 sr = set_c0_status(ST0_BEV);
181 write_c0_ebase((u32)ebase);
184 octeon_check_cpu_bist();
185 octeon_init_cvmcount();
187 octeon_irq_setup_secondary();
191 * Callout to firmware before smp_init
194 void octeon_prepare_cpus(unsigned int max_cpus)
196 #ifdef CONFIG_HOTPLUG_CPU
197 struct linux_app_boot_info *labi;
199 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
201 if (labi->labi_signature != LABI_SIGNATURE)
202 panic("The bootloader version on this board is incorrect.");
205 * Only the low order mailbox bits are used for IPIs, leave
206 * the other bits alone.
208 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff);
209 if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt,
210 IRQF_PERCPU | IRQF_NO_THREAD, "SMP-IPI",
211 mailbox_interrupt)) {
212 panic("Cannot request_irq(OCTEON_IRQ_MBOX0)");
217 * Last chance for the board code to finish SMP initialization before
218 * the CPU is "online".
220 static void octeon_smp_finish(void)
222 #ifdef CONFIG_CAVIUM_GDB
224 /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0
225 to be not masked by this core so we know the signal is received by
227 asm volatile ("dmfc0 %0, $22\n"
228 "ori %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp));
231 octeon_user_io_init();
233 /* to generate the first CPU timer interrupt */
234 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
239 * Hook for after all CPUs are online
241 static void octeon_cpus_done(void)
243 #ifdef CONFIG_CAVIUM_GDB
245 /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0
246 to be not masked by this core so we know the signal is received by
248 asm volatile ("dmfc0 %0, $22\n"
249 "ori %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp));
253 #ifdef CONFIG_HOTPLUG_CPU
255 /* State of each CPU. */
256 DEFINE_PER_CPU(int, cpu_state);
258 static int octeon_cpu_disable(void)
260 unsigned int cpu = smp_processor_id();
265 set_cpu_online(cpu, false);
266 cpu_clear(cpu, cpu_callin_map);
272 local_flush_tlb_all();
277 static void octeon_cpu_die(unsigned int cpu)
279 int coreid = cpu_logical_map(cpu);
280 uint32_t mask, new_mask;
281 const struct cvmx_bootmem_named_block_desc *block_desc;
283 while (per_cpu(cpu_state, cpu) != CPU_DEAD)
287 * This is a bit complicated strategics of getting/settig available
288 * cores mask, copied from bootloader
292 /* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
293 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
296 struct linux_app_boot_info *labi;
298 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
300 labi->avail_coremask |= mask;
301 new_mask = labi->avail_coremask;
302 } else { /* alternative, already initialized */
303 uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr +
304 AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
309 pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask);
311 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
312 cvmx_write_csr(CVMX_CIU_PP_RST, 0);
317 int cpu = cpu_number_map(cvmx_get_core_num());
320 octeon_processor_boot = 0xff;
321 per_cpu(cpu_state, cpu) = CPU_DEAD;
325 while (1) /* core will be reset here */
329 extern void kernel_entry(unsigned long arg1, ...);
331 static void start_after_reset(void)
333 kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */
336 static int octeon_update_boot_vector(unsigned int cpu)
339 int coreid = cpu_logical_map(cpu);
340 uint32_t avail_coremask;
341 const struct cvmx_bootmem_named_block_desc *block_desc;
342 struct boot_init_vector *boot_vect =
343 (struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR);
345 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
348 struct linux_app_boot_info *labi;
350 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
352 avail_coremask = labi->avail_coremask;
353 labi->avail_coremask &= ~(1 << coreid);
354 } else { /* alternative, already initialized */
355 avail_coremask = *(uint32_t *)PHYS_TO_XKSEG_CACHED(
356 block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
359 if (!(avail_coremask & (1 << coreid))) {
360 /* core not available, assume, that catched by simple-executive */
361 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
362 cvmx_write_csr(CVMX_CIU_PP_RST, 0);
365 boot_vect[coreid].app_start_func_addr =
366 (uint32_t) (unsigned long) start_after_reset;
367 boot_vect[coreid].code_addr = octeon_bootloader_entry_addr;
371 cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);
376 static int octeon_cpu_callback(struct notifier_block *nfb,
377 unsigned long action, void *hcpu)
379 unsigned int cpu = (unsigned long)hcpu;
383 octeon_update_boot_vector(cpu);
386 pr_info("Cpu %d online\n", cpu);
395 static int register_cavium_notifier(void)
397 hotcpu_notifier(octeon_cpu_callback, 0);
400 late_initcall(register_cavium_notifier);
402 #endif /* CONFIG_HOTPLUG_CPU */
404 struct plat_smp_ops octeon_smp_ops = {
405 .send_ipi_single = octeon_send_ipi_single,
406 .send_ipi_mask = octeon_send_ipi_mask,
407 .init_secondary = octeon_init_secondary,
408 .smp_finish = octeon_smp_finish,
409 .cpus_done = octeon_cpus_done,
410 .boot_secondary = octeon_boot_secondary,
411 .smp_setup = octeon_smp_setup,
412 .prepare_cpus = octeon_prepare_cpus,
413 #ifdef CONFIG_HOTPLUG_CPU
414 .cpu_disable = octeon_cpu_disable,
415 .cpu_die = octeon_cpu_die,