2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
9 #include <linux/delay.h>
10 #include <linux/smp.h>
11 #include <linux/interrupt.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/sched.h>
14 #include <linux/module.h>
16 #include <asm/mmu_context.h>
18 #include <asm/setup.h>
20 #include <asm/octeon/octeon.h>
22 #include "octeon_boot.h"
24 volatile unsigned long octeon_processor_boot = 0xff;
25 volatile unsigned long octeon_processor_sp;
26 volatile unsigned long octeon_processor_gp;
28 #ifdef CONFIG_HOTPLUG_CPU
29 uint64_t octeon_bootloader_entry_addr;
30 EXPORT_SYMBOL(octeon_bootloader_entry_addr);
33 static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
35 const int coreid = cvmx_get_core_num();
38 /* Load the mailbox register to figure out what we're supposed to do */
39 action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid)) & 0xffff;
41 /* Clear the mailbox to clear the interrupt */
42 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action);
44 if (action & SMP_CALL_FUNCTION)
45 smp_call_function_interrupt();
46 if (action & SMP_RESCHEDULE_YOURSELF)
49 /* Check if we've been told to flush the icache */
50 if (action & SMP_ICACHE_FLUSH)
51 asm volatile ("synci 0($0)\n");
56 * Cause the function described by call_data to be executed on the passed
57 * cpu. When the function has finished, increment the finished field of
60 void octeon_send_ipi_single(int cpu, unsigned int action)
62 int coreid = cpu_logical_map(cpu);
64 pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu,
67 cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
70 static inline void octeon_send_ipi_mask(const struct cpumask *mask,
75 for_each_cpu_mask(i, *mask)
76 octeon_send_ipi_single(i, action);
80 * Detect available CPUs, populate cpu_possible_mask
82 static void octeon_smp_hotplug_setup(void)
84 #ifdef CONFIG_HOTPLUG_CPU
85 struct linux_app_boot_info *labi;
90 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
91 if (labi->labi_signature != LABI_SIGNATURE) {
92 pr_info("The bootloader on this board does not support HOTPLUG_CPU.");
96 octeon_bootloader_entry_addr = labi->InitTLBStart_addr;
100 static void octeon_smp_setup(void)
102 const int coreid = cvmx_get_core_num();
105 int core_mask = octeon_get_boot_coremask();
106 #ifdef CONFIG_HOTPLUG_CPU
107 unsigned int num_cores = cvmx_octeon_num_cores();
110 /* The present CPUs are initially just the boot cpu (CPU 0). */
111 for (id = 0; id < NR_CPUS; id++) {
112 set_cpu_possible(id, id == 0);
113 set_cpu_present(id, id == 0);
116 __cpu_number_map[coreid] = 0;
117 __cpu_logical_map[0] = coreid;
119 /* The present CPUs get the lowest CPU numbers. */
121 for (id = 0; id < NR_CPUS; id++) {
122 if ((id != coreid) && (core_mask & (1 << id))) {
123 set_cpu_possible(cpus, true);
124 set_cpu_present(cpus, true);
125 __cpu_number_map[id] = cpus;
126 __cpu_logical_map[cpus] = id;
131 #ifdef CONFIG_HOTPLUG_CPU
133 * The possible CPUs are all those present on the chip. We
134 * will assign CPU numbers for possible cores as well. Cores
135 * are always consecutively numberd from 0.
137 for (id = 0; setup_max_cpus && octeon_bootloader_entry_addr &&
138 id < num_cores && id < NR_CPUS; id++) {
139 if (!(core_mask & (1 << id))) {
140 set_cpu_possible(cpus, true);
141 __cpu_number_map[id] = cpus;
142 __cpu_logical_map[cpus] = id;
148 octeon_smp_hotplug_setup();
152 * Firmware CPU startup hook
155 static void octeon_boot_secondary(int cpu, struct task_struct *idle)
159 pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu,
160 cpu_logical_map(cpu));
162 octeon_processor_sp = __KSTK_TOS(idle);
163 octeon_processor_gp = (unsigned long)(task_thread_info(idle));
164 octeon_processor_boot = cpu_logical_map(cpu);
168 while (octeon_processor_sp && count) {
169 /* Waiting for processor to get the SP and GP */
174 pr_err("Secondary boot timeout\n");
178 * After we've done initial boot, this function is called to allow the
179 * board code to clean up state, if needed
181 static void octeon_init_secondary(void)
185 sr = set_c0_status(ST0_BEV);
186 write_c0_ebase((u32)ebase);
189 octeon_check_cpu_bist();
190 octeon_init_cvmcount();
192 octeon_irq_setup_secondary();
196 * Callout to firmware before smp_init
199 void octeon_prepare_cpus(unsigned int max_cpus)
202 * Only the low order mailbox bits are used for IPIs, leave
203 * the other bits alone.
205 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff);
206 if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt,
207 IRQF_PERCPU | IRQF_NO_THREAD, "SMP-IPI",
208 mailbox_interrupt)) {
209 panic("Cannot request_irq(OCTEON_IRQ_MBOX0)");
214 * Last chance for the board code to finish SMP initialization before
215 * the CPU is "online".
217 static void octeon_smp_finish(void)
219 octeon_user_io_init();
221 /* to generate the first CPU timer interrupt */
222 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
226 #ifdef CONFIG_HOTPLUG_CPU
228 /* State of each CPU. */
229 DEFINE_PER_CPU(int, cpu_state);
231 static int octeon_cpu_disable(void)
233 unsigned int cpu = smp_processor_id();
238 if (!octeon_bootloader_entry_addr)
241 set_cpu_online(cpu, false);
242 cpu_clear(cpu, cpu_callin_map);
246 local_flush_tlb_all();
251 static void octeon_cpu_die(unsigned int cpu)
253 int coreid = cpu_logical_map(cpu);
254 uint32_t mask, new_mask;
255 const struct cvmx_bootmem_named_block_desc *block_desc;
257 while (per_cpu(cpu_state, cpu) != CPU_DEAD)
261 * This is a bit complicated strategics of getting/settig available
262 * cores mask, copied from bootloader
266 /* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
267 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
270 struct linux_app_boot_info *labi;
272 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
274 labi->avail_coremask |= mask;
275 new_mask = labi->avail_coremask;
276 } else { /* alternative, already initialized */
277 uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr +
278 AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
283 pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask);
285 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
286 cvmx_write_csr(CVMX_CIU_PP_RST, 0);
291 int cpu = cpu_number_map(cvmx_get_core_num());
294 octeon_processor_boot = 0xff;
295 per_cpu(cpu_state, cpu) = CPU_DEAD;
299 while (1) /* core will be reset here */
303 extern void kernel_entry(unsigned long arg1, ...);
305 static void start_after_reset(void)
307 kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */
310 static int octeon_update_boot_vector(unsigned int cpu)
313 int coreid = cpu_logical_map(cpu);
314 uint32_t avail_coremask;
315 const struct cvmx_bootmem_named_block_desc *block_desc;
316 struct boot_init_vector *boot_vect =
317 (struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR);
319 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
322 struct linux_app_boot_info *labi;
324 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
326 avail_coremask = labi->avail_coremask;
327 labi->avail_coremask &= ~(1 << coreid);
328 } else { /* alternative, already initialized */
329 avail_coremask = *(uint32_t *)PHYS_TO_XKSEG_CACHED(
330 block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
333 if (!(avail_coremask & (1 << coreid))) {
334 /* core not available, assume, that catched by simple-executive */
335 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
336 cvmx_write_csr(CVMX_CIU_PP_RST, 0);
339 boot_vect[coreid].app_start_func_addr =
340 (uint32_t) (unsigned long) start_after_reset;
341 boot_vect[coreid].code_addr = octeon_bootloader_entry_addr;
345 cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);
350 static int octeon_cpu_callback(struct notifier_block *nfb,
351 unsigned long action, void *hcpu)
353 unsigned int cpu = (unsigned long)hcpu;
357 octeon_update_boot_vector(cpu);
360 pr_info("Cpu %d online\n", cpu);
369 static int register_cavium_notifier(void)
371 hotcpu_notifier(octeon_cpu_callback, 0);
374 late_initcall(register_cavium_notifier);
376 #endif /* CONFIG_HOTPLUG_CPU */
378 struct plat_smp_ops octeon_smp_ops = {
379 .send_ipi_single = octeon_send_ipi_single,
380 .send_ipi_mask = octeon_send_ipi_mask,
381 .init_secondary = octeon_init_secondary,
382 .smp_finish = octeon_smp_finish,
383 .boot_secondary = octeon_boot_secondary,
384 .smp_setup = octeon_smp_setup,
385 .prepare_cpus = octeon_prepare_cpus,
386 #ifdef CONFIG_HOTPLUG_CPU
387 .cpu_disable = octeon_cpu_disable,
388 .cpu_die = octeon_cpu_die,