3 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
5 * Xiangfu Liu <xiangfu@openmobilefree.net>
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/mipsregs.h>
14 #include <asm/cacheops.h>
15 #include <asm/reboot.h>
17 #include <asm/jz4740.h>
19 #define cache_op(op, addr) \
20 __asm__ __volatile__( \
27 : "i" (op), "R" (*(unsigned char *)(addr)))
29 void __attribute__((weak)) _machine_restart(void)
31 struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;
32 struct jz4740_tcu *tcu = (struct jz4740_tcu *)JZ4740_TCU_BASE;
35 /* wdt_select_extalclk() */
36 tmp = readw(&wdt->tcsr);
37 tmp &= ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN);
38 tmp |= WDT_TCSR_EXT_EN;
39 writew(tmp, &wdt->tcsr);
41 /* wdt_select_clk_div64() */
42 tmp = readw(&wdt->tcsr);
43 tmp &= ~WDT_TCSR_PRESCALE_MASK;
44 tmp |= WDT_TCSR_PRESCALE64,
45 writew(tmp, &wdt->tcsr);
47 writew(100, &wdt->tdr); /* wdt_set_data(100) */
48 writew(0, &wdt->tcnt); /* wdt_set_count(0); */
49 writel(TCU_TSSR_WDTSC, &tcu->tscr); /* tcu_start_wdt_clock */
50 writeb(readb(&wdt->tcer) | WDT_TCER_TCEN, &wdt->tcer); /* wdt start */
56 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
60 fprintf(stderr, "*** reset failed ***\n");
64 void flush_cache(ulong start_addr, ulong size)
66 unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
67 unsigned long addr = start_addr & ~(lsize - 1);
68 unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
70 for (; addr <= aend; addr += lsize) {
71 cache_op(HIT_WRITEBACK_INV_D, addr);
72 cache_op(HIT_INVALIDATE_I, addr);
76 void flush_dcache_range(ulong start_addr, ulong stop)
78 unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
79 unsigned long addr = start_addr & ~(lsize - 1);
80 unsigned long aend = (stop - 1) & ~(lsize - 1);
82 for (; addr <= aend; addr += lsize)
83 cache_op(HIT_WRITEBACK_INV_D, addr);
86 void invalidate_dcache_range(ulong start_addr, ulong stop)
88 unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
89 unsigned long addr = start_addr & ~(lsize - 1);
90 unsigned long aend = (stop - 1) & ~(lsize - 1);
92 for (; addr <= aend; addr += lsize)
93 cache_op(HIT_INVALIDATE_D, addr);
96 void flush_icache_all(void)
100 __asm__ __volatile__("mtc0 $0, $28"); /* Clear Taglo */
101 __asm__ __volatile__("mtc0 $0, $29"); /* Clear TagHi */
103 for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_ICACHE_SIZE;
104 addr += CONFIG_SYS_CACHELINE_SIZE) {
105 cache_op(INDEX_STORE_TAG_I, addr);
109 __asm__ __volatile__(
111 "mfc0 %0, $16, 7\n\t"
114 "mtc0 %0, $16, 7\n\t"
120 void flush_dcache_all(void)
124 for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE;
125 addr += CONFIG_SYS_CACHELINE_SIZE) {
126 cache_op(INDEX_WRITEBACK_INV_D, addr);
129 __asm__ __volatile__("sync");
132 void flush_cache_all(void)