arch/mips/include/asm/bmips.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
   7  *
   8  * Definitions for BMIPS processors
   9  */
  10 #ifndef _ASM_BMIPS_H
  11 #define _ASM_BMIPS_H
  12
  13 #include <linux/compiler.h>
  14 #include <linux/linkage.h>
  15 #include <asm/addrspace.h>
  16 #include <asm/mipsregs.h>
  17 #include <asm/hazards.h>
  18
  19 /* NOTE: the CBR register returns a PA, and it can be above 0xff00_0000 */
  20 #define BMIPS_GET_CBR()                 ((void __iomem *)(CKSEG1 | \
  21                                          (unsigned long) \
  22                                          ((read_c0_brcm_cbr() >> 18) << 18)))
  23
  24 #define BMIPS_RAC_CONFIG                0x00000000
  25 #define BMIPS_RAC_ADDRESS_RANGE         0x00000004
  26 #define BMIPS_RAC_CONFIG_1              0x00000008
  27 #define BMIPS_L2_CONFIG                 0x0000000c
  28 #define BMIPS_LMB_CONTROL               0x0000001c
  29 #define BMIPS_SYSTEM_BASE               0x00000020
  30 #define BMIPS_PERF_GLOBAL_CONTROL       0x00020000
  31 #define BMIPS_PERF_CONTROL_0            0x00020004
  32 #define BMIPS_PERF_CONTROL_1            0x00020008
  33 #define BMIPS_PERF_COUNTER_0            0x00020010
  34 #define BMIPS_PERF_COUNTER_1            0x00020014
  35 #define BMIPS_PERF_COUNTER_2            0x00020018
  36 #define BMIPS_PERF_COUNTER_3            0x0002001c
  37 #define BMIPS_RELO_VECTOR_CONTROL_0     0x00030000
  38 #define BMIPS_RELO_VECTOR_CONTROL_1     0x00038000
  39
  40 #define BMIPS_NMI_RESET_VEC             0x80000000
  41 #define BMIPS_WARM_RESTART_VEC          0x80000380
  42
  43 #define ZSCM_REG_BASE                   0x97000000
  44
  45 #if !defined(__ASSEMBLY__)
  46
  47 #include <linux/cpumask.h>
  48 #include <asm/r4kcache.h>
  49
  50 extern struct plat_smp_ops bmips_smp_ops;
  51 extern char bmips_reset_nmi_vec;
  52 extern char bmips_reset_nmi_vec_end;
  53 extern char bmips_smp_movevec;
  54 extern char bmips_smp_int_vec;
  55 extern char bmips_smp_int_vec_end;
  56
  57 extern int bmips_smp_enabled;
  58 extern int bmips_cpu_offset;
  59 extern cpumask_t bmips_booted_mask;
  60
  61 extern void bmips_ebase_setup(void);
  62 extern asmlinkage void plat_wired_tlb_setup(void);
  63
  64 static inline unsigned long bmips_read_zscm_reg(unsigned int offset)
  65 {
  66         unsigned long ret;
  67
  68         __asm__ __volatile__(
  69                 ".set push\n"
  70                 ".set noreorder\n"
  71                 "cache %1, 0(%2)\n"
  72                 "sync\n"
  73                 "_ssnop\n"
  74                 "_ssnop\n"
  75                 "_ssnop\n"
  76                 "_ssnop\n"
  77                 "_ssnop\n"
  78                 "_ssnop\n"
  79                 "_ssnop\n"
  80                 "mfc0 %0, $28, 3\n"
  81                 "_ssnop\n"
  82                 ".set pop\n"
  83                 : "=&r" (ret)
  84                 : "i" (Index_Load_Tag_S), "r" (ZSCM_REG_BASE + offset)
  85                 : "memory");
  86         return ret;
  87 }
  88
  89 static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data)
  90 {
  91         __asm__ __volatile__(
  92                 ".set push\n"
  93                 ".set noreorder\n"
  94                 "mtc0 %0, $28, 3\n"
  95                 "_ssnop\n"
  96                 "_ssnop\n"
  97                 "_ssnop\n"
  98                 "cache %1, 0(%2)\n"
  99                 "_ssnop\n"
 100                 "_ssnop\n"
 101                 "_ssnop\n"
 102                 : /* no outputs */
 103                 : "r" (data),
 104                   "i" (Index_Store_Tag_S), "r" (ZSCM_REG_BASE + offset)
 105                 : "memory");
 106 }
 107
 108 #endif /* !defined(__ASSEMBLY__) */
 109
 110 #endif /* _ASM_BMIPS_H */