2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003, 2004 Ralf Baechle
7 * Copyright (C) 2004 Maciej W. Rozycki
9 #ifndef __ASM_CPU_FEATURES_H
10 #define __ASM_CPU_FEATURES_H
13 #include <asm/cpu-info.h>
14 #include <cpu-feature-overrides.h>
17 * SMP assumption: Options of CPU 0 are a superset of all processors.
18 * This is true for all known MIPS systems.
21 #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
23 #ifndef cpu_has_tlbinv
24 #define cpu_has_tlbinv (cpu_data[0].options & MIPS_CPU_TLBINV)
26 #ifndef cpu_has_segments
27 #define cpu_has_segments (cpu_data[0].options & MIPS_CPU_SEGMENTS)
30 #define cpu_has_eva (cpu_data[0].options & MIPS_CPU_EVA)
34 * For the moment we don't consider R6000 and R8000 so we can assume that
35 * anything that doesn't support R4000-style exceptions and interrupts is
36 * R3000-like. Users should still treat these two macro definitions as
40 #define cpu_has_3kex (!cpu_has_4kex)
43 #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
45 #ifndef cpu_has_3k_cache
46 #define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
48 #define cpu_has_6k_cache 0
49 #define cpu_has_8k_cache 0
50 #ifndef cpu_has_4k_cache
51 #define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
53 #ifndef cpu_has_tx39_cache
54 #define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
56 #ifndef cpu_has_octeon_cache
57 #define cpu_has_octeon_cache 0
60 #define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
61 #define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
63 #define raw_cpu_has_fpu cpu_has_fpu
66 #define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
68 #ifndef cpu_has_counter
69 #define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
72 #define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
75 #define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
78 #define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
80 #ifndef cpu_has_cache_cdex_p
81 #define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
83 #ifndef cpu_has_cache_cdex_s
84 #define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
86 #ifndef cpu_has_prefetch
87 #define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
89 #ifndef cpu_has_mcheck
90 #define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
93 #define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
96 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
98 #ifndef kernel_uses_llsc
99 #define kernel_uses_llsc cpu_has_llsc
101 #ifndef cpu_has_mips16
102 #define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
105 #define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
107 #ifndef cpu_has_mips3d
108 #define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
110 #ifndef cpu_has_smartmips
111 #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
114 #define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
116 #ifndef cpu_has_mmips
117 # ifdef CONFIG_SYS_SUPPORTS_MICROMIPS
118 # define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS)
120 # define cpu_has_mmips 0
123 #ifndef cpu_has_vtag_icache
124 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
126 #ifndef cpu_has_dc_aliases
127 #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
129 #ifndef cpu_has_ic_fills_f_dc
130 #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
132 #ifndef cpu_has_pindexed_dcache
133 #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
135 #ifndef cpu_has_local_ebase
136 #define cpu_has_local_ebase 1
140 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
141 * such as the R10000 have I-Caches that snoop local stores; the embedded ones
142 * don't. For maintaining I-cache coherency this means we need to flush the
143 * D-cache all the way back to whever the I-cache does refills from, so the
144 * I-cache has a chance to see the new data at all. Then we have to flush the
146 * Note we may have been rescheduled and may no longer be running on the CPU
147 * that did the store so we can't optimize this into only doing the flush on
150 #ifndef cpu_icache_snoops_remote_store
152 #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
154 #define cpu_icache_snoops_remote_store 1
158 #ifndef cpu_has_mips_2
159 # define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II)
161 #ifndef cpu_has_mips_3
162 # define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III)
164 #ifndef cpu_has_mips_4
165 # define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV)
167 #ifndef cpu_has_mips_5
168 # define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V)
170 #ifndef cpu_has_mips32r1
171 # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
173 #ifndef cpu_has_mips32r2
174 # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
176 #ifndef cpu_has_mips64r1
177 # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
179 #ifndef cpu_has_mips64r2
180 # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
186 #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2)
187 #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2)
188 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
189 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
190 #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
191 cpu_has_mips64r1 | cpu_has_mips64r2)
193 #ifndef cpu_has_mips_r2_exec_hazard
194 #define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2
198 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
199 * pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and
200 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels
201 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
203 #ifndef cpu_has_clo_clz
204 #define cpu_has_clo_clz cpu_has_mips_r
208 #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
212 #define cpu_has_dsp2 (cpu_data[0].ases & MIPS_ASE_DSP2P)
215 #ifndef cpu_has_mipsmt
216 #define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
219 #ifndef cpu_has_userlocal
220 #define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
224 # ifndef cpu_has_nofpuex
225 # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
227 # ifndef cpu_has_64bits
228 # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
230 # ifndef cpu_has_64bit_zero_reg
231 # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
233 # ifndef cpu_has_64bit_gp_regs
234 # define cpu_has_64bit_gp_regs 0
236 # ifndef cpu_has_64bit_addresses
237 # define cpu_has_64bit_addresses 0
240 # define cpu_vmbits 31
245 # ifndef cpu_has_nofpuex
246 # define cpu_has_nofpuex 0
248 # ifndef cpu_has_64bits
249 # define cpu_has_64bits 1
251 # ifndef cpu_has_64bit_zero_reg
252 # define cpu_has_64bit_zero_reg 1
254 # ifndef cpu_has_64bit_gp_regs
255 # define cpu_has_64bit_gp_regs 1
257 # ifndef cpu_has_64bit_addresses
258 # define cpu_has_64bit_addresses 1
261 # define cpu_vmbits cpu_data[0].vmbits
262 # define __NEED_VMBITS_PROBE
266 #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
267 # define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
268 #elif !defined(cpu_has_vint)
269 # define cpu_has_vint 0
272 #if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
273 # define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
274 #elif !defined(cpu_has_veic)
275 # define cpu_has_veic 0
278 #ifndef cpu_has_inclusive_pcaches
279 #define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
282 #ifndef cpu_dcache_line_size
283 #define cpu_dcache_line_size() cpu_data[0].dcache.linesz
285 #ifndef cpu_icache_line_size
286 #define cpu_icache_line_size() cpu_data[0].icache.linesz
288 #ifndef cpu_scache_line_size
289 #define cpu_scache_line_size() cpu_data[0].scache.linesz
292 #ifndef cpu_hwrena_impl_bits
293 #define cpu_hwrena_impl_bits 0
296 #ifndef cpu_has_perf_cntr_intr_bit
297 #define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI)
301 #define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ)
304 #if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa)
305 # define cpu_has_msa (cpu_data[0].ases & MIPS_ASE_MSA)
306 #elif !defined(cpu_has_msa)
307 # define cpu_has_msa 0
310 #endif /* __ASM_CPU_FEATURES_H */