2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003, 2004 Ralf Baechle
7 * Copyright (C) 2004 Maciej W. Rozycki
9 #ifndef __ASM_CPU_FEATURES_H
10 #define __ASM_CPU_FEATURES_H
13 #include <asm/cpu-info.h>
14 #include <cpu-feature-overrides.h>
17 * SMP assumption: Options of CPU 0 are a superset of all processors.
18 * This is true for all known MIPS systems.
21 #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
23 #ifndef cpu_has_tlbinv
24 #define cpu_has_tlbinv (cpu_data[0].options & MIPS_CPU_TLBINV)
26 #ifndef cpu_has_segments
27 #define cpu_has_segments (cpu_data[0].options & MIPS_CPU_SEGMENTS)
30 #define cpu_has_eva (cpu_data[0].options & MIPS_CPU_EVA)
33 #define cpu_has_htw (cpu_data[0].options & MIPS_CPU_HTW)
35 #ifndef cpu_has_rixiex
36 #define cpu_has_rixiex (cpu_data[0].options & MIPS_CPU_RIXIEX)
39 #define cpu_has_maar (cpu_data[0].options & MIPS_CPU_MAAR)
41 #ifndef cpu_has_rw_llb
42 #define cpu_has_rw_llb (cpu_data[0].options & MIPS_CPU_RW_LLB)
46 * For the moment we don't consider R6000 and R8000 so we can assume that
47 * anything that doesn't support R4000-style exceptions and interrupts is
48 * R3000-like. Users should still treat these two macro definitions as
52 #define cpu_has_3kex (!cpu_has_4kex)
55 #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
57 #ifndef cpu_has_3k_cache
58 #define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
60 #define cpu_has_6k_cache 0
61 #define cpu_has_8k_cache 0
62 #ifndef cpu_has_4k_cache
63 #define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
65 #ifndef cpu_has_tx39_cache
66 #define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
68 #ifndef cpu_has_octeon_cache
69 #define cpu_has_octeon_cache 0
71 /* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work. */
73 #define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
74 #define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
76 #define raw_cpu_has_fpu cpu_has_fpu
79 #define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
81 #ifndef cpu_has_counter
82 #define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
85 #define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
88 #define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
91 #define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
93 #ifndef cpu_has_cache_cdex_p
94 #define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
96 #ifndef cpu_has_cache_cdex_s
97 #define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
99 #ifndef cpu_has_prefetch
100 #define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
102 #ifndef cpu_has_mcheck
103 #define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
105 #ifndef cpu_has_ejtag
106 #define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
109 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
111 #ifndef kernel_uses_llsc
112 #define kernel_uses_llsc cpu_has_llsc
114 #ifndef cpu_has_mips16
115 #define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
118 #define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
120 #ifndef cpu_has_mips3d
121 #define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
123 #ifndef cpu_has_smartmips
124 #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
129 # define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
130 # else /* CONFIG_32BIT */
131 # define cpu_has_rixi ((cpu_data[0].options & MIPS_CPU_RIXI) && !cpu_has_64bits)
135 #ifndef cpu_has_mmips
136 # ifdef CONFIG_SYS_SUPPORTS_MICROMIPS
137 # define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS)
139 # define cpu_has_mmips 0
143 #ifndef cpu_has_vtag_icache
144 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
146 #ifndef cpu_has_dc_aliases
147 #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
149 #ifndef cpu_has_ic_fills_f_dc
150 #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
152 #ifndef cpu_has_pindexed_dcache
153 #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
155 #ifndef cpu_has_local_ebase
156 #define cpu_has_local_ebase 1
160 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
161 * such as the R10000 have I-Caches that snoop local stores; the embedded ones
162 * don't. For maintaining I-cache coherency this means we need to flush the
163 * D-cache all the way back to whever the I-cache does refills from, so the
164 * I-cache has a chance to see the new data at all. Then we have to flush the
166 * Note we may have been rescheduled and may no longer be running on the CPU
167 * that did the store so we can't optimize this into only doing the flush on
170 #ifndef cpu_icache_snoops_remote_store
172 #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
174 #define cpu_icache_snoops_remote_store 1
178 #ifndef cpu_has_mips_1
179 # define cpu_has_mips_1 (!cpu_has_mips_r6)
181 #ifndef cpu_has_mips_2
182 # define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II)
184 #ifndef cpu_has_mips_3
185 # define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III)
187 #ifndef cpu_has_mips_4
188 # define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV)
190 #ifndef cpu_has_mips_5
191 # define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V)
193 #ifndef cpu_has_mips32r1
194 # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
196 #ifndef cpu_has_mips32r2
197 # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
199 #ifndef cpu_has_mips32r6
200 # define cpu_has_mips32r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6)
202 #ifndef cpu_has_mips64r1
203 # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
205 #ifndef cpu_has_mips64r2
206 # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
208 #ifndef cpu_has_mips64r6
209 # define cpu_has_mips64r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R6)
215 #define cpu_has_mips_2_3_4_5 (cpu_has_mips_2 | cpu_has_mips_3_4_5)
216 #define cpu_has_mips_3_4_5 (cpu_has_mips_3 | cpu_has_mips_4_5)
217 #define cpu_has_mips_4_5 (cpu_has_mips_4 | cpu_has_mips_5)
219 #define cpu_has_mips_2_3_4_5_r (cpu_has_mips_2 | cpu_has_mips_3_4_5_r)
220 #define cpu_has_mips_3_4_5_r (cpu_has_mips_3 | cpu_has_mips_4_5_r)
221 #define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r)
222 #define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r)
224 #define cpu_has_mips_3_4_5_64_r2_r6 \
225 (cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6)
226 #define cpu_has_mips_4_5_64_r2_r6 \
227 (cpu_has_mips_4_5 | cpu_has_mips64r1 | \
228 cpu_has_mips_r2 | cpu_has_mips_r6)
230 #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6)
231 #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6)
232 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
233 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
234 #define cpu_has_mips_r6 (cpu_has_mips32r6 | cpu_has_mips64r6)
235 #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
236 cpu_has_mips32r6 | cpu_has_mips64r1 | \
237 cpu_has_mips64r2 | cpu_has_mips64r6)
239 /* MIPSR2 and MIPSR6 have a lot of similarities */
240 #define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r6)
242 #ifndef cpu_has_mips_r2_exec_hazard
243 #define cpu_has_mips_r2_exec_hazard (cpu_has_mips_r2 | cpu_has_mips_r6)
247 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
248 * pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and
249 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels
250 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
252 #ifndef cpu_has_clo_clz
253 #define cpu_has_clo_clz cpu_has_mips_r
257 * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH.
258 * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD.
259 * This indicates the availability of WSBH and in case of 64 bit CPUs also
263 #define cpu_has_wsbh cpu_has_mips_r2
267 #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
271 #define cpu_has_dsp2 (cpu_data[0].ases & MIPS_ASE_DSP2P)
274 #ifndef cpu_has_mipsmt
275 #define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
278 #ifndef cpu_has_userlocal
279 #define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
283 # ifndef cpu_has_nofpuex
284 # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
286 # ifndef cpu_has_64bits
287 # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
289 # ifndef cpu_has_64bit_zero_reg
290 # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
292 # ifndef cpu_has_64bit_gp_regs
293 # define cpu_has_64bit_gp_regs 0
295 # ifndef cpu_has_64bit_addresses
296 # define cpu_has_64bit_addresses 0
299 # define cpu_vmbits 31
304 # ifndef cpu_has_nofpuex
305 # define cpu_has_nofpuex 0
307 # ifndef cpu_has_64bits
308 # define cpu_has_64bits 1
310 # ifndef cpu_has_64bit_zero_reg
311 # define cpu_has_64bit_zero_reg 1
313 # ifndef cpu_has_64bit_gp_regs
314 # define cpu_has_64bit_gp_regs 1
316 # ifndef cpu_has_64bit_addresses
317 # define cpu_has_64bit_addresses 1
320 # define cpu_vmbits cpu_data[0].vmbits
321 # define __NEED_VMBITS_PROBE
325 #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
326 # define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
327 #elif !defined(cpu_has_vint)
328 # define cpu_has_vint 0
331 #if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
332 # define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
333 #elif !defined(cpu_has_veic)
334 # define cpu_has_veic 0
337 #ifndef cpu_has_inclusive_pcaches
338 #define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
341 #ifndef cpu_dcache_line_size
342 #define cpu_dcache_line_size() cpu_data[0].dcache.linesz
344 #ifndef cpu_icache_line_size
345 #define cpu_icache_line_size() cpu_data[0].icache.linesz
347 #ifndef cpu_scache_line_size
348 #define cpu_scache_line_size() cpu_data[0].scache.linesz
351 #ifndef cpu_hwrena_impl_bits
352 #define cpu_hwrena_impl_bits 0
355 #ifndef cpu_has_perf_cntr_intr_bit
356 #define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI)
360 #define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ)
363 #if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa)
364 # define cpu_has_msa (cpu_data[0].ases & MIPS_ASE_MSA)
365 #elif !defined(cpu_has_msa)
366 # define cpu_has_msa 0
370 # define cpu_has_fre (cpu_data[0].options & MIPS_CPU_FRE)
374 # define cpu_has_cdmm (cpu_data[0].options & MIPS_CPU_CDMM)
377 #endif /* __ASM_CPU_FEATURES_H */