2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 Waldorf GMBH
7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
8 * Copyright (C) 1996 Paul M. Antoine
9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 * Copyright (C) 2004 Maciej W. Rozycki
12 #ifndef __ASM_CPU_INFO_H
13 #define __ASM_CPU_INFO_H
15 #include <linux/cache.h>
16 #include <linux/types.h>
19 * Descriptor for a cache
22 unsigned int waysize; /* Bytes per way */
23 unsigned short sets; /* Number of lines per set */
24 unsigned char ways; /* Number of ways */
25 unsigned char linesz; /* Size of line in bytes */
26 unsigned char waybit; /* Bits to select in a cache set */
27 unsigned char flags; /* Flags describing cache properties */
32 unsigned long ases_dyn;
33 unsigned long long options;
34 unsigned long long options_dyn;
42 #define MIPS_CACHE_NOT_PRESENT 0x00000001
43 #define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */
44 #define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */
45 #define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */
46 #define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */
47 #define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */
50 unsigned long asid_cache;
51 #ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
52 unsigned long asid_mask;
56 * Capability and feature descriptor structure for MIPS CPU
59 unsigned long long options;
60 unsigned int udelay_val;
61 unsigned int processor_id;
63 unsigned int fpu_csr31;
64 unsigned int fpu_msk31;
72 struct cache_desc icache; /* Primary I-cache */
73 struct cache_desc dcache; /* Primary D or combined I/D cache */
74 struct cache_desc vcache; /* Victim cache, between pcache and scache */
75 struct cache_desc scache; /* Secondary cache */
76 struct cache_desc tcache; /* Tertiary/split secondary cache */
77 int srsets; /* Shadow register sets */
78 int package;/* physical package number */
79 int core; /* physical core number */
81 int vmbits; /* Virtual memory size in bits */
83 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6)
85 * There is not necessarily a 1:1 mapping of VPE num to CPU number
86 * in particular on multi-core systems.
88 int vpe_id; /* Virtual Processor number */
90 void *data; /* Additional data */
91 unsigned int watch_reg_count; /* Number that exist */
92 unsigned int watch_reg_use_cnt; /* Usable by ptrace */
93 #define NUM_WATCH_REGS 4
94 u16 watch_reg_masks[NUM_WATCH_REGS];
95 unsigned int kscratch_mask; /* Usable KScratch mask. */
97 * Cache Coherency attribute for write-combine memory writes.
98 * (shifted by _CACHE_SHIFT)
100 unsigned int writecombine;
102 * Simple counter to prevent enabling HTW in nested
103 * htw_start/htw_stop calls
105 unsigned int htw_seq;
107 /* VZ & Guest features */
108 struct guest_info guest;
109 unsigned int gtoffset_mask;
110 unsigned int guestid_mask;
111 } __attribute__((aligned(SMP_CACHE_BYTES)));
113 extern struct cpuinfo_mips cpu_data[];
114 #define current_cpu_data cpu_data[smp_processor_id()]
115 #define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
116 #define boot_cpu_data cpu_data[0]
118 extern void cpu_probe(void);
119 extern void cpu_report(void);
121 extern const char *__cpu_name[];
122 #define cpu_name_string() __cpu_name[raw_smp_processor_id()]
125 struct notifier_block;
127 extern int register_proc_cpuinfo_notifier(struct notifier_block *nb);
128 extern int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v);
130 #define proc_cpuinfo_notifier(fn, pri) \
132 static struct notifier_block fn##_nb = { \
133 .notifier_call = fn, \
137 register_proc_cpuinfo_notifier(&fn##_nb); \
140 struct proc_cpuinfo_notifier_args {
145 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6)
146 # define cpu_vpe_id(cpuinfo) ((cpuinfo)->vpe_id)
148 # define cpu_vpe_id(cpuinfo) ({ (void)cpuinfo; 0; })
151 static inline unsigned long cpu_asid_inc(void)
153 return 1 << CONFIG_MIPS_ASID_SHIFT;
156 static inline unsigned long cpu_asid_mask(struct cpuinfo_mips *cpuinfo)
158 #ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
159 return cpuinfo->asid_mask;
161 return ((1 << CONFIG_MIPS_ASID_BITS) - 1) << CONFIG_MIPS_ASID_SHIFT;
164 static inline void set_cpu_asid_mask(struct cpuinfo_mips *cpuinfo,
165 unsigned long asid_mask)
167 #ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
168 cpuinfo->asid_mask = asid_mask;
172 #endif /* __ASM_CPU_INFO_H */