arch/mips/include/asm/kvm_host.h

   1 /*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   7 * Authors: Sanjay Lal <sanjayl@kymasys.com>
   8 */
   9
  10 #ifndef __MIPS_KVM_HOST_H__
  11 #define __MIPS_KVM_HOST_H__
  12
  13 #include <linux/mutex.h>
  14 #include <linux/hrtimer.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/types.h>
  17 #include <linux/kvm.h>
  18 #include <linux/kvm_types.h>
  19 #include <linux/threads.h>
  20 #include <linux/spinlock.h>
  21
  22 #include <asm/inst.h>
  23 #include <asm/mipsregs.h>
  24
  25 /* MIPS KVM register ids */
  26 #define MIPS_CP0_32(_R, _S)                                     \
  27         (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
  28
  29 #define MIPS_CP0_64(_R, _S)                                     \
  30         (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
  31
  32 #define KVM_REG_MIPS_CP0_INDEX          MIPS_CP0_32(0, 0)
  33 #define KVM_REG_MIPS_CP0_ENTRYLO0       MIPS_CP0_64(2, 0)
  34 #define KVM_REG_MIPS_CP0_ENTRYLO1       MIPS_CP0_64(3, 0)
  35 #define KVM_REG_MIPS_CP0_CONTEXT        MIPS_CP0_64(4, 0)
  36 #define KVM_REG_MIPS_CP0_USERLOCAL      MIPS_CP0_64(4, 2)
  37 #define KVM_REG_MIPS_CP0_PAGEMASK       MIPS_CP0_32(5, 0)
  38 #define KVM_REG_MIPS_CP0_PAGEGRAIN      MIPS_CP0_32(5, 1)
  39 #define KVM_REG_MIPS_CP0_WIRED          MIPS_CP0_32(6, 0)
  40 #define KVM_REG_MIPS_CP0_HWRENA         MIPS_CP0_32(7, 0)
  41 #define KVM_REG_MIPS_CP0_BADVADDR       MIPS_CP0_64(8, 0)
  42 #define KVM_REG_MIPS_CP0_COUNT          MIPS_CP0_32(9, 0)
  43 #define KVM_REG_MIPS_CP0_ENTRYHI        MIPS_CP0_64(10, 0)
  44 #define KVM_REG_MIPS_CP0_COMPARE        MIPS_CP0_32(11, 0)
  45 #define KVM_REG_MIPS_CP0_STATUS         MIPS_CP0_32(12, 0)
  46 #define KVM_REG_MIPS_CP0_CAUSE          MIPS_CP0_32(13, 0)
  47 #define KVM_REG_MIPS_CP0_EPC            MIPS_CP0_64(14, 0)
  48 #define KVM_REG_MIPS_CP0_PRID           MIPS_CP0_32(15, 0)
  49 #define KVM_REG_MIPS_CP0_EBASE          MIPS_CP0_64(15, 1)
  50 #define KVM_REG_MIPS_CP0_CONFIG         MIPS_CP0_32(16, 0)
  51 #define KVM_REG_MIPS_CP0_CONFIG1        MIPS_CP0_32(16, 1)
  52 #define KVM_REG_MIPS_CP0_CONFIG2        MIPS_CP0_32(16, 2)
  53 #define KVM_REG_MIPS_CP0_CONFIG3        MIPS_CP0_32(16, 3)
  54 #define KVM_REG_MIPS_CP0_CONFIG4        MIPS_CP0_32(16, 4)
  55 #define KVM_REG_MIPS_CP0_CONFIG5        MIPS_CP0_32(16, 5)
  56 #define KVM_REG_MIPS_CP0_CONFIG7        MIPS_CP0_32(16, 7)
  57 #define KVM_REG_MIPS_CP0_XCONTEXT       MIPS_CP0_64(20, 0)
  58 #define KVM_REG_MIPS_CP0_ERROREPC       MIPS_CP0_64(30, 0)
  59 #define KVM_REG_MIPS_CP0_KSCRATCH1      MIPS_CP0_64(31, 2)
  60 #define KVM_REG_MIPS_CP0_KSCRATCH2      MIPS_CP0_64(31, 3)
  61 #define KVM_REG_MIPS_CP0_KSCRATCH3      MIPS_CP0_64(31, 4)
  62 #define KVM_REG_MIPS_CP0_KSCRATCH4      MIPS_CP0_64(31, 5)
  63 #define KVM_REG_MIPS_CP0_KSCRATCH5      MIPS_CP0_64(31, 6)
  64 #define KVM_REG_MIPS_CP0_KSCRATCH6      MIPS_CP0_64(31, 7)
  65
  66
  67 #define KVM_MAX_VCPUS           1
  68 #define KVM_USER_MEM_SLOTS      8
  69 /* memory slots that does not exposed to userspace */
  70 #define KVM_PRIVATE_MEM_SLOTS   0
  71
  72 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
  73 #define KVM_HALT_POLL_NS_DEFAULT 500000
  74
  75
  76
  77 /*
  78  * Special address that contains the comm page, used for reducing # of traps
  79  * This needs to be within 32Kb of 0x0 (so the zero register can be used), but
  80  * preferably not at 0x0 so that most kernel NULL pointer dereferences can be
  81  * caught.
  82  */
  83 #define KVM_GUEST_COMMPAGE_ADDR         ((PAGE_SIZE > 0x8000) ? 0 : \
  84                                          (0x8000 - PAGE_SIZE))
  85
  86 #define KVM_GUEST_KERNEL_MODE(vcpu)     ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
  87                                         ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
  88
  89 #define KVM_GUEST_KUSEG                 0x00000000UL
  90 #define KVM_GUEST_KSEG0                 0x40000000UL
  91 #define KVM_GUEST_KSEG23                0x60000000UL
  92 #define KVM_GUEST_KSEGX(a)              ((_ACAST32_(a)) & 0xe0000000)
  93 #define KVM_GUEST_CPHYSADDR(a)          ((_ACAST32_(a)) & 0x1fffffff)
  94
  95 #define KVM_GUEST_CKSEG0ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
  96 #define KVM_GUEST_CKSEG1ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
  97 #define KVM_GUEST_CKSEG23ADDR(a)        (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
  98
  99 /*
 100  * Map an address to a certain kernel segment
 101  */
 102 #define KVM_GUEST_KSEG0ADDR(a)          (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
 103 #define KVM_GUEST_KSEG1ADDR(a)          (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
 104 #define KVM_GUEST_KSEG23ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
 105
 106 #define KVM_INVALID_PAGE                0xdeadbeef
 107 #define KVM_INVALID_ADDR                0xdeadbeef
 108
 109 /*
 110  * EVA has overlapping user & kernel address spaces, so user VAs may be >
 111  * PAGE_OFFSET. For this reason we can't use the default KVM_HVA_ERR_BAD of
 112  * PAGE_OFFSET.
 113  */
 114
 115 #define KVM_HVA_ERR_BAD                 (-1UL)
 116 #define KVM_HVA_ERR_RO_BAD              (-2UL)
 117
 118 static inline bool kvm_is_error_hva(unsigned long addr)
 119 {
 120         return IS_ERR_VALUE(addr);
 121 }
 122
 123 struct kvm_vm_stat {
 124         ulong remote_tlb_flush;
 125 };
 126
 127 struct kvm_vcpu_stat {
 128         u64 wait_exits;
 129         u64 cache_exits;
 130         u64 signal_exits;
 131         u64 int_exits;
 132         u64 cop_unusable_exits;
 133         u64 tlbmod_exits;
 134         u64 tlbmiss_ld_exits;
 135         u64 tlbmiss_st_exits;
 136         u64 addrerr_st_exits;
 137         u64 addrerr_ld_exits;
 138         u64 syscall_exits;
 139         u64 resvd_inst_exits;
 140         u64 break_inst_exits;
 141         u64 trap_inst_exits;
 142         u64 msa_fpe_exits;
 143         u64 fpe_exits;
 144         u64 msa_disabled_exits;
 145         u64 flush_dcache_exits;
 146         u64 halt_successful_poll;
 147         u64 halt_attempted_poll;
 148         u64 halt_poll_invalid;
 149         u64 halt_wakeup;
 150 };
 151
 152 struct kvm_arch_memory_slot {
 153 };
 154
 155 struct kvm_arch {
 156         /* Guest physical mm */
 157         struct mm_struct gpa_mm;
 158 };
 159
 160 #define N_MIPS_COPROC_REGS      32
 161 #define N_MIPS_COPROC_SEL       8
 162
 163 struct mips_coproc {
 164         unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
 165 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
 166         unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
 167 #endif
 168 };
 169
 170 /*
 171  * Coprocessor 0 register names
 172  */
 173 #define MIPS_CP0_TLB_INDEX      0
 174 #define MIPS_CP0_TLB_RANDOM     1
 175 #define MIPS_CP0_TLB_LOW        2
 176 #define MIPS_CP0_TLB_LO0        2
 177 #define MIPS_CP0_TLB_LO1        3
 178 #define MIPS_CP0_TLB_CONTEXT    4
 179 #define MIPS_CP0_TLB_PG_MASK    5
 180 #define MIPS_CP0_TLB_WIRED      6
 181 #define MIPS_CP0_HWRENA         7
 182 #define MIPS_CP0_BAD_VADDR      8
 183 #define MIPS_CP0_COUNT          9
 184 #define MIPS_CP0_TLB_HI         10
 185 #define MIPS_CP0_COMPARE        11
 186 #define MIPS_CP0_STATUS         12
 187 #define MIPS_CP0_CAUSE          13
 188 #define MIPS_CP0_EXC_PC         14
 189 #define MIPS_CP0_PRID           15
 190 #define MIPS_CP0_CONFIG         16
 191 #define MIPS_CP0_LLADDR         17
 192 #define MIPS_CP0_WATCH_LO       18
 193 #define MIPS_CP0_WATCH_HI       19
 194 #define MIPS_CP0_TLB_XCONTEXT   20
 195 #define MIPS_CP0_ECC            26
 196 #define MIPS_CP0_CACHE_ERR      27
 197 #define MIPS_CP0_TAG_LO         28
 198 #define MIPS_CP0_TAG_HI         29
 199 #define MIPS_CP0_ERROR_PC       30
 200 #define MIPS_CP0_DEBUG          23
 201 #define MIPS_CP0_DEPC           24
 202 #define MIPS_CP0_PERFCNT        25
 203 #define MIPS_CP0_ERRCTL         26
 204 #define MIPS_CP0_DATA_LO        28
 205 #define MIPS_CP0_DATA_HI        29
 206 #define MIPS_CP0_DESAVE         31
 207
 208 #define MIPS_CP0_CONFIG_SEL     0
 209 #define MIPS_CP0_CONFIG1_SEL    1
 210 #define MIPS_CP0_CONFIG2_SEL    2
 211 #define MIPS_CP0_CONFIG3_SEL    3
 212 #define MIPS_CP0_CONFIG4_SEL    4
 213 #define MIPS_CP0_CONFIG5_SEL    5
 214
 215 /* Resume Flags */
 216 #define RESUME_FLAG_DR          (1<<0)  /* Reload guest nonvolatile state? */
 217 #define RESUME_FLAG_HOST        (1<<1)  /* Resume host? */
 218
 219 #define RESUME_GUEST            0
 220 #define RESUME_GUEST_DR         RESUME_FLAG_DR
 221 #define RESUME_HOST             RESUME_FLAG_HOST
 222
 223 enum emulation_result {
 224         EMULATE_DONE,           /* no further processing */
 225         EMULATE_DO_MMIO,        /* kvm_run filled with MMIO request */
 226         EMULATE_FAIL,           /* can't emulate this instruction */
 227         EMULATE_WAIT,           /* WAIT instruction */
 228         EMULATE_PRIV_FAIL,
 229         EMULATE_EXCEPT,         /* A guest exception has been generated */
 230 };
 231
 232 #define mips3_paddr_to_tlbpfn(x) \
 233         (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
 234 #define mips3_tlbpfn_to_paddr(x) \
 235         ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
 236
 237 #define MIPS3_PG_SHIFT          6
 238 #define MIPS3_PG_FRAME          0x3fffffc0
 239
 240 #define VPN2_MASK               0xffffe000
 241 #define KVM_ENTRYHI_ASID        MIPS_ENTRYHI_ASID
 242 #define TLB_IS_GLOBAL(x)        ((x).tlb_lo[0] & (x).tlb_lo[1] & ENTRYLO_G)
 243 #define TLB_VPN2(x)             ((x).tlb_hi & VPN2_MASK)
 244 #define TLB_ASID(x)             ((x).tlb_hi & KVM_ENTRYHI_ASID)
 245 #define TLB_LO_IDX(x, va)       (((va) >> PAGE_SHIFT) & 1)
 246 #define TLB_IS_VALID(x, va)     ((x).tlb_lo[TLB_LO_IDX(x, va)] & ENTRYLO_V)
 247 #define TLB_IS_DIRTY(x, va)     ((x).tlb_lo[TLB_LO_IDX(x, va)] & ENTRYLO_D)
 248 #define TLB_HI_VPN2_HIT(x, y)   ((TLB_VPN2(x) & ~(x).tlb_mask) ==       \
 249                                  ((y) & VPN2_MASK & ~(x).tlb_mask))
 250 #define TLB_HI_ASID_HIT(x, y)   (TLB_IS_GLOBAL(x) ||                    \
 251                                  TLB_ASID(x) == ((y) & KVM_ENTRYHI_ASID))
 252
 253 struct kvm_mips_tlb {
 254         long tlb_mask;
 255         long tlb_hi;
 256         long tlb_lo[2];
 257 };
 258
 259 #define KVM_NR_MEM_OBJS     4
 260
 261 /*
 262  * We don't want allocation failures within the mmu code, so we preallocate
 263  * enough memory for a single page fault in a cache.
 264  */
 265 struct kvm_mmu_memory_cache {
 266         int nobjs;
 267         void *objects[KVM_NR_MEM_OBJS];
 268 };
 269
 270 #define KVM_MIPS_AUX_FPU        0x1
 271 #define KVM_MIPS_AUX_MSA        0x2
 272
 273 #define KVM_MIPS_GUEST_TLB_SIZE 64
 274 struct kvm_vcpu_arch {
 275         void *guest_ebase;
 276         int (*vcpu_run)(struct kvm_run *run, struct kvm_vcpu *vcpu);
 277         unsigned long host_stack;
 278         unsigned long host_gp;
 279
 280         /* Host CP0 registers used when handling exits from guest */
 281         unsigned long host_cp0_badvaddr;
 282         unsigned long host_cp0_epc;
 283         u32 host_cp0_cause;
 284         u32 host_cp0_badinstr;
 285         u32 host_cp0_badinstrp;
 286
 287         /* GPRS */
 288         unsigned long gprs[32];
 289         unsigned long hi;
 290         unsigned long lo;
 291         unsigned long pc;
 292
 293         /* FPU State */
 294         struct mips_fpu_struct fpu;
 295         /* Which auxiliary state is loaded (KVM_MIPS_AUX_*) */
 296         unsigned int aux_inuse;
 297
 298         /* COP0 State */
 299         struct mips_coproc *cop0;
 300
 301         /* Host KSEG0 address of the EI/DI offset */
 302         void *kseg0_commpage;
 303
 304         /* Resume PC after MMIO completion */
 305         unsigned long io_pc;
 306         /* GPR used as IO source/target */
 307         u32 io_gpr;
 308
 309         struct hrtimer comparecount_timer;
 310         /* Count timer control KVM register */
 311         u32 count_ctl;
 312         /* Count bias from the raw time */
 313         u32 count_bias;
 314         /* Frequency of timer in Hz */
 315         u32 count_hz;
 316         /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */
 317         s64 count_dyn_bias;
 318         /* Resume time */
 319         ktime_t count_resume;
 320         /* Period of timer tick in ns */
 321         u64 count_period;
 322
 323         /* Bitmask of exceptions that are pending */
 324         unsigned long pending_exceptions;
 325
 326         /* Bitmask of pending exceptions to be cleared */
 327         unsigned long pending_exceptions_clr;
 328
 329         /* S/W Based TLB for guest */
 330         struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
 331
 332         /* Guest kernel/user [partial] mm */
 333         struct mm_struct guest_kernel_mm, guest_user_mm;
 334
 335         /* Guest ASID of last user mode execution */
 336         unsigned int last_user_gasid;
 337
 338         /* Cache some mmu pages needed inside spinlock regions */
 339         struct kvm_mmu_memory_cache mmu_page_cache;
 340
 341         int last_sched_cpu;
 342
 343         /* WAIT executed */
 344         int wait;
 345
 346         u8 fpu_enabled;
 347         u8 msa_enabled;
 348         u8 kscratch_enabled;
 349 };
 350
 351
 352 #define kvm_read_c0_guest_index(cop0)           (cop0->reg[MIPS_CP0_TLB_INDEX][0])
 353 #define kvm_write_c0_guest_index(cop0, val)     (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
 354 #define kvm_read_c0_guest_entrylo0(cop0)        (cop0->reg[MIPS_CP0_TLB_LO0][0])
 355 #define kvm_read_c0_guest_entrylo1(cop0)        (cop0->reg[MIPS_CP0_TLB_LO1][0])
 356 #define kvm_read_c0_guest_context(cop0)         (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
 357 #define kvm_write_c0_guest_context(cop0, val)   (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
 358 #define kvm_read_c0_guest_userlocal(cop0)       (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
 359 #define kvm_write_c0_guest_userlocal(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2] = (val))
 360 #define kvm_read_c0_guest_pagemask(cop0)        (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
 361 #define kvm_write_c0_guest_pagemask(cop0, val)  (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
 362 #define kvm_read_c0_guest_wired(cop0)           (cop0->reg[MIPS_CP0_TLB_WIRED][0])
 363 #define kvm_write_c0_guest_wired(cop0, val)     (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
 364 #define kvm_read_c0_guest_hwrena(cop0)          (cop0->reg[MIPS_CP0_HWRENA][0])
 365 #define kvm_write_c0_guest_hwrena(cop0, val)    (cop0->reg[MIPS_CP0_HWRENA][0] = (val))
 366 #define kvm_read_c0_guest_badvaddr(cop0)        (cop0->reg[MIPS_CP0_BAD_VADDR][0])
 367 #define kvm_write_c0_guest_badvaddr(cop0, val)  (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
 368 #define kvm_read_c0_guest_count(cop0)           (cop0->reg[MIPS_CP0_COUNT][0])
 369 #define kvm_write_c0_guest_count(cop0, val)     (cop0->reg[MIPS_CP0_COUNT][0] = (val))
 370 #define kvm_read_c0_guest_entryhi(cop0)         (cop0->reg[MIPS_CP0_TLB_HI][0])
 371 #define kvm_write_c0_guest_entryhi(cop0, val)   (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
 372 #define kvm_read_c0_guest_compare(cop0)         (cop0->reg[MIPS_CP0_COMPARE][0])
 373 #define kvm_write_c0_guest_compare(cop0, val)   (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
 374 #define kvm_read_c0_guest_status(cop0)          (cop0->reg[MIPS_CP0_STATUS][0])
 375 #define kvm_write_c0_guest_status(cop0, val)    (cop0->reg[MIPS_CP0_STATUS][0] = (val))
 376 #define kvm_read_c0_guest_intctl(cop0)          (cop0->reg[MIPS_CP0_STATUS][1])
 377 #define kvm_write_c0_guest_intctl(cop0, val)    (cop0->reg[MIPS_CP0_STATUS][1] = (val))
 378 #define kvm_read_c0_guest_cause(cop0)           (cop0->reg[MIPS_CP0_CAUSE][0])
 379 #define kvm_write_c0_guest_cause(cop0, val)     (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
 380 #define kvm_read_c0_guest_epc(cop0)             (cop0->reg[MIPS_CP0_EXC_PC][0])
 381 #define kvm_write_c0_guest_epc(cop0, val)       (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
 382 #define kvm_read_c0_guest_prid(cop0)            (cop0->reg[MIPS_CP0_PRID][0])
 383 #define kvm_write_c0_guest_prid(cop0, val)      (cop0->reg[MIPS_CP0_PRID][0] = (val))
 384 #define kvm_read_c0_guest_ebase(cop0)           (cop0->reg[MIPS_CP0_PRID][1])
 385 #define kvm_write_c0_guest_ebase(cop0, val)     (cop0->reg[MIPS_CP0_PRID][1] = (val))
 386 #define kvm_read_c0_guest_config(cop0)          (cop0->reg[MIPS_CP0_CONFIG][0])
 387 #define kvm_read_c0_guest_config1(cop0)         (cop0->reg[MIPS_CP0_CONFIG][1])
 388 #define kvm_read_c0_guest_config2(cop0)         (cop0->reg[MIPS_CP0_CONFIG][2])
 389 #define kvm_read_c0_guest_config3(cop0)         (cop0->reg[MIPS_CP0_CONFIG][3])
 390 #define kvm_read_c0_guest_config4(cop0)         (cop0->reg[MIPS_CP0_CONFIG][4])
 391 #define kvm_read_c0_guest_config5(cop0)         (cop0->reg[MIPS_CP0_CONFIG][5])
 392 #define kvm_read_c0_guest_config7(cop0)         (cop0->reg[MIPS_CP0_CONFIG][7])
 393 #define kvm_write_c0_guest_config(cop0, val)    (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
 394 #define kvm_write_c0_guest_config1(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
 395 #define kvm_write_c0_guest_config2(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
 396 #define kvm_write_c0_guest_config3(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
 397 #define kvm_write_c0_guest_config4(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][4] = (val))
 398 #define kvm_write_c0_guest_config5(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][5] = (val))
 399 #define kvm_write_c0_guest_config7(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
 400 #define kvm_read_c0_guest_errorepc(cop0)        (cop0->reg[MIPS_CP0_ERROR_PC][0])
 401 #define kvm_write_c0_guest_errorepc(cop0, val)  (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
 402 #define kvm_read_c0_guest_kscratch1(cop0)       (cop0->reg[MIPS_CP0_DESAVE][2])
 403 #define kvm_read_c0_guest_kscratch2(cop0)       (cop0->reg[MIPS_CP0_DESAVE][3])
 404 #define kvm_read_c0_guest_kscratch3(cop0)       (cop0->reg[MIPS_CP0_DESAVE][4])
 405 #define kvm_read_c0_guest_kscratch4(cop0)       (cop0->reg[MIPS_CP0_DESAVE][5])
 406 #define kvm_read_c0_guest_kscratch5(cop0)       (cop0->reg[MIPS_CP0_DESAVE][6])
 407 #define kvm_read_c0_guest_kscratch6(cop0)       (cop0->reg[MIPS_CP0_DESAVE][7])
 408 #define kvm_write_c0_guest_kscratch1(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][2] = (val))
 409 #define kvm_write_c0_guest_kscratch2(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][3] = (val))
 410 #define kvm_write_c0_guest_kscratch3(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][4] = (val))
 411 #define kvm_write_c0_guest_kscratch4(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][5] = (val))
 412 #define kvm_write_c0_guest_kscratch5(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][6] = (val))
 413 #define kvm_write_c0_guest_kscratch6(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][7] = (val))
 414
 415 /*
 416  * Some of the guest registers may be modified asynchronously (e.g. from a
 417  * hrtimer callback in hard irq context) and therefore need stronger atomicity
 418  * guarantees than other registers.
 419  */
 420
 421 static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg,
 422                                                 unsigned long val)
 423 {
 424         unsigned long temp;
 425         do {
 426                 __asm__ __volatile__(
 427                 "       .set    "MIPS_ISA_ARCH_LEVEL"           \n"
 428                 "       " __LL "%0, %1                          \n"
 429                 "       or      %0, %2                          \n"
 430                 "       " __SC  "%0, %1                         \n"
 431                 "       .set    mips0                           \n"
 432                 : "=&r" (temp), "+m" (*reg)
 433                 : "r" (val));
 434         } while (unlikely(!temp));
 435 }
 436
 437 static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg,
 438                                                   unsigned long val)
 439 {
 440         unsigned long temp;
 441         do {
 442                 __asm__ __volatile__(
 443                 "       .set    "MIPS_ISA_ARCH_LEVEL"           \n"
 444                 "       " __LL "%0, %1                          \n"
 445                 "       and     %0, %2                          \n"
 446                 "       " __SC  "%0, %1                         \n"
 447                 "       .set    mips0                           \n"
 448                 : "=&r" (temp), "+m" (*reg)
 449                 : "r" (~val));
 450         } while (unlikely(!temp));
 451 }
 452
 453 static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg,
 454                                                    unsigned long change,
 455                                                    unsigned long val)
 456 {
 457         unsigned long temp;
 458         do {
 459                 __asm__ __volatile__(
 460                 "       .set    "MIPS_ISA_ARCH_LEVEL"           \n"
 461                 "       " __LL "%0, %1                          \n"
 462                 "       and     %0, %2                          \n"
 463                 "       or      %0, %3                          \n"
 464                 "       " __SC  "%0, %1                         \n"
 465                 "       .set    mips0                           \n"
 466                 : "=&r" (temp), "+m" (*reg)
 467                 : "r" (~change), "r" (val & change));
 468         } while (unlikely(!temp));
 469 }
 470
 471 #define kvm_set_c0_guest_status(cop0, val)      (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
 472 #define kvm_clear_c0_guest_status(cop0, val)    (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
 473
 474 /* Cause can be modified asynchronously from hardirq hrtimer callback */
 475 #define kvm_set_c0_guest_cause(cop0, val)                               \
 476         _kvm_atomic_set_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
 477 #define kvm_clear_c0_guest_cause(cop0, val)                             \
 478         _kvm_atomic_clear_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
 479 #define kvm_change_c0_guest_cause(cop0, change, val)                    \
 480         _kvm_atomic_change_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0],  \
 481                                         change, val)
 482
 483 #define kvm_set_c0_guest_ebase(cop0, val)       (cop0->reg[MIPS_CP0_PRID][1] |= (val))
 484 #define kvm_clear_c0_guest_ebase(cop0, val)     (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
 485 #define kvm_change_c0_guest_ebase(cop0, change, val)                    \
 486 {                                                                       \
 487         kvm_clear_c0_guest_ebase(cop0, change);                         \
 488         kvm_set_c0_guest_ebase(cop0, ((val) & (change)));               \
 489 }
 490
 491 /* Helpers */
 492
 493 static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch *vcpu)
 494 {
 495         return (!__builtin_constant_p(raw_cpu_has_fpu) || raw_cpu_has_fpu) &&
 496                 vcpu->fpu_enabled;
 497 }
 498
 499 static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch *vcpu)
 500 {
 501         return kvm_mips_guest_can_have_fpu(vcpu) &&
 502                 kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP;
 503 }
 504
 505 static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch *vcpu)
 506 {
 507         return (!__builtin_constant_p(cpu_has_msa) || cpu_has_msa) &&
 508                 vcpu->msa_enabled;
 509 }
 510
 511 static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch *vcpu)
 512 {
 513         return kvm_mips_guest_can_have_msa(vcpu) &&
 514                 kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA;
 515 }
 516
 517 struct kvm_mips_callbacks {
 518         int (*handle_cop_unusable)(struct kvm_vcpu *vcpu);
 519         int (*handle_tlb_mod)(struct kvm_vcpu *vcpu);
 520         int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu);
 521         int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu);
 522         int (*handle_addr_err_st)(struct kvm_vcpu *vcpu);
 523         int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu);
 524         int (*handle_syscall)(struct kvm_vcpu *vcpu);
 525         int (*handle_res_inst)(struct kvm_vcpu *vcpu);
 526         int (*handle_break)(struct kvm_vcpu *vcpu);
 527         int (*handle_trap)(struct kvm_vcpu *vcpu);
 528         int (*handle_msa_fpe)(struct kvm_vcpu *vcpu);
 529         int (*handle_fpe)(struct kvm_vcpu *vcpu);
 530         int (*handle_msa_disabled)(struct kvm_vcpu *vcpu);
 531         int (*vcpu_init)(struct kvm_vcpu *vcpu);
 532         void (*vcpu_uninit)(struct kvm_vcpu *vcpu);
 533         int (*vcpu_setup)(struct kvm_vcpu *vcpu);
 534         gpa_t (*gva_to_gpa)(gva_t gva);
 535         void (*queue_timer_int)(struct kvm_vcpu *vcpu);
 536         void (*dequeue_timer_int)(struct kvm_vcpu *vcpu);
 537         void (*queue_io_int)(struct kvm_vcpu *vcpu,
 538                              struct kvm_mips_interrupt *irq);
 539         void (*dequeue_io_int)(struct kvm_vcpu *vcpu,
 540                                struct kvm_mips_interrupt *irq);
 541         int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority,
 542                            u32 cause);
 543         int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority,
 544                          u32 cause);
 545         unsigned long (*num_regs)(struct kvm_vcpu *vcpu);
 546         int (*copy_reg_indices)(struct kvm_vcpu *vcpu, u64 __user *indices);
 547         int (*get_one_reg)(struct kvm_vcpu *vcpu,
 548                            const struct kvm_one_reg *reg, s64 *v);
 549         int (*set_one_reg)(struct kvm_vcpu *vcpu,
 550                            const struct kvm_one_reg *reg, s64 v);
 551         int (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu);
 552         int (*vcpu_put)(struct kvm_vcpu *vcpu, int cpu);
 553         int (*vcpu_run)(struct kvm_run *run, struct kvm_vcpu *vcpu);
 554         void (*vcpu_reenter)(struct kvm_run *run, struct kvm_vcpu *vcpu);
 555 };
 556 extern struct kvm_mips_callbacks *kvm_mips_callbacks;
 557 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
 558
 559 /* Debug: dump vcpu state */
 560 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
 561
 562 extern int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu);
 563
 564 /* Building of entry/exception code */
 565 int kvm_mips_entry_setup(void);
 566 void *kvm_mips_build_vcpu_run(void *addr);
 567 void *kvm_mips_build_tlb_refill_exception(void *addr, void *handler);
 568 void *kvm_mips_build_exception(void *addr, void *handler);
 569 void *kvm_mips_build_exit(void *addr);
 570
 571 /* FPU/MSA context management */
 572 void __kvm_save_fpu(struct kvm_vcpu_arch *vcpu);
 573 void __kvm_restore_fpu(struct kvm_vcpu_arch *vcpu);
 574 void __kvm_restore_fcsr(struct kvm_vcpu_arch *vcpu);
 575 void __kvm_save_msa(struct kvm_vcpu_arch *vcpu);
 576 void __kvm_restore_msa(struct kvm_vcpu_arch *vcpu);
 577 void __kvm_restore_msa_upper(struct kvm_vcpu_arch *vcpu);
 578 void __kvm_restore_msacsr(struct kvm_vcpu_arch *vcpu);
 579 void kvm_own_fpu(struct kvm_vcpu *vcpu);
 580 void kvm_own_msa(struct kvm_vcpu *vcpu);
 581 void kvm_drop_fpu(struct kvm_vcpu *vcpu);
 582 void kvm_lose_fpu(struct kvm_vcpu *vcpu);
 583
 584 /* TLB handling */
 585 u32 kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
 586
 587 u32 kvm_get_user_asid(struct kvm_vcpu *vcpu);
 588
 589 u32 kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
 590
 591 extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
 592                                            struct kvm_vcpu *vcpu);
 593
 594 extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
 595                                               struct kvm_vcpu *vcpu);
 596
 597 extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
 598                                                 struct kvm_mips_tlb *tlb,
 599                                                 unsigned long gva);
 600
 601 extern enum emulation_result kvm_mips_handle_tlbmiss(u32 cause,
 602                                                      u32 *opc,
 603                                                      struct kvm_run *run,
 604                                                      struct kvm_vcpu *vcpu);
 605
 606 extern enum emulation_result kvm_mips_handle_tlbmod(u32 cause,
 607                                                     u32 *opc,
 608                                                     struct kvm_run *run,
 609                                                     struct kvm_vcpu *vcpu);
 610
 611 extern void kvm_mips_dump_host_tlbs(void);
 612 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
 613 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi,
 614                                  bool user, bool kernel);
 615
 616 extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
 617                                      unsigned long entryhi);
 618
 619 void kvm_mips_suspend_mm(int cpu);
 620 void kvm_mips_resume_mm(int cpu);
 621
 622 /* MMU handling */
 623
 624 /**
 625  * enum kvm_mips_flush - Types of MMU flushes.
 626  * @KMF_USER:   Flush guest user virtual memory mappings.
 627  *              Guest USeg only.
 628  * @KMF_KERN:   Flush guest kernel virtual memory mappings.
 629  *              Guest USeg and KSeg2/3.
 630  * @KMF_GPA:    Flush guest physical memory mappings.
 631  *              Also includes KSeg0 if KMF_KERN is set.
 632  */
 633 enum kvm_mips_flush {
 634         KMF_USER        = 0x0,
 635         KMF_KERN        = 0x1,
 636         KMF_GPA         = 0x2,
 637 };
 638 void kvm_mips_flush_gva_pt(pgd_t *pgd, enum kvm_mips_flush flags);
 639 bool kvm_mips_flush_gpa_pt(struct kvm *kvm, gfn_t start_gfn, gfn_t end_gfn);
 640 pgd_t *kvm_pgd_alloc(void);
 641 void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
 642 void kvm_trap_emul_invalidate_gva(struct kvm_vcpu *vcpu, unsigned long addr,
 643                                   bool user);
 644 void kvm_trap_emul_gva_lockless_begin(struct kvm_vcpu *vcpu);
 645 void kvm_trap_emul_gva_lockless_end(struct kvm_vcpu *vcpu);
 646
 647 enum kvm_mips_fault_result {
 648         KVM_MIPS_MAPPED = 0,
 649         KVM_MIPS_GVA,
 650         KVM_MIPS_GPA,
 651         KVM_MIPS_TLB,
 652         KVM_MIPS_TLBINV,
 653         KVM_MIPS_TLBMOD,
 654 };
 655 enum kvm_mips_fault_result kvm_trap_emul_gva_fault(struct kvm_vcpu *vcpu,
 656                                                    unsigned long gva,
 657                                                    bool write);
 658
 659 /* Emulation */
 660 int kvm_get_inst(u32 *opc, struct kvm_vcpu *vcpu, u32 *out);
 661 enum emulation_result update_pc(struct kvm_vcpu *vcpu, u32 cause);
 662 int kvm_get_badinstr(u32 *opc, struct kvm_vcpu *vcpu, u32 *out);
 663 int kvm_get_badinstrp(u32 *opc, struct kvm_vcpu *vcpu, u32 *out);
 664
 665 /**
 666  * kvm_is_ifetch_fault() - Find whether a TLBL exception is due to ifetch fault.
 667  * @vcpu:       Virtual CPU.
 668  *
 669  * Returns:     Whether the TLBL exception was likely due to an instruction
 670  *              fetch fault rather than a data load fault.
 671  */
 672 static inline bool kvm_is_ifetch_fault(struct kvm_vcpu_arch *vcpu)
 673 {
 674         unsigned long badvaddr = vcpu->host_cp0_badvaddr;
 675         unsigned long epc = msk_isa16_mode(vcpu->pc);
 676         u32 cause = vcpu->host_cp0_cause;
 677
 678         if (epc == badvaddr)
 679                 return true;
 680
 681         /*
 682          * Branches may be 32-bit or 16-bit instructions.
 683          * This isn't exact, but we don't really support MIPS16 or microMIPS yet
 684          * in KVM anyway.
 685          */
 686         if ((cause & CAUSEF_BD) && badvaddr - epc <= 4)
 687                 return true;
 688
 689         return false;
 690 }
 691
 692 extern enum emulation_result kvm_mips_emulate_inst(u32 cause,
 693                                                    u32 *opc,
 694                                                    struct kvm_run *run,
 695                                                    struct kvm_vcpu *vcpu);
 696
 697 extern enum emulation_result kvm_mips_emulate_syscall(u32 cause,
 698                                                       u32 *opc,
 699                                                       struct kvm_run *run,
 700                                                       struct kvm_vcpu *vcpu);
 701
 702 extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(u32 cause,
 703                                                          u32 *opc,
 704                                                          struct kvm_run *run,
 705                                                          struct kvm_vcpu *vcpu);
 706
 707 extern enum emulation_result kvm_mips_emulate_tlbinv_ld(u32 cause,
 708                                                         u32 *opc,
 709                                                         struct kvm_run *run,
 710                                                         struct kvm_vcpu *vcpu);
 711
 712 extern enum emulation_result kvm_mips_emulate_tlbmiss_st(u32 cause,
 713                                                          u32 *opc,
 714                                                          struct kvm_run *run,
 715                                                          struct kvm_vcpu *vcpu);
 716
 717 extern enum emulation_result kvm_mips_emulate_tlbinv_st(u32 cause,
 718                                                         u32 *opc,
 719                                                         struct kvm_run *run,
 720                                                         struct kvm_vcpu *vcpu);
 721
 722 extern enum emulation_result kvm_mips_emulate_tlbmod(u32 cause,
 723                                                      u32 *opc,
 724                                                      struct kvm_run *run,
 725                                                      struct kvm_vcpu *vcpu);
 726
 727 extern enum emulation_result kvm_mips_emulate_fpu_exc(u32 cause,
 728                                                       u32 *opc,
 729                                                       struct kvm_run *run,
 730                                                       struct kvm_vcpu *vcpu);
 731
 732 extern enum emulation_result kvm_mips_handle_ri(u32 cause,
 733                                                 u32 *opc,
 734                                                 struct kvm_run *run,
 735                                                 struct kvm_vcpu *vcpu);
 736
 737 extern enum emulation_result kvm_mips_emulate_ri_exc(u32 cause,
 738                                                      u32 *opc,
 739                                                      struct kvm_run *run,
 740                                                      struct kvm_vcpu *vcpu);
 741
 742 extern enum emulation_result kvm_mips_emulate_bp_exc(u32 cause,
 743                                                      u32 *opc,
 744                                                      struct kvm_run *run,
 745                                                      struct kvm_vcpu *vcpu);
 746
 747 extern enum emulation_result kvm_mips_emulate_trap_exc(u32 cause,
 748                                                        u32 *opc,
 749                                                        struct kvm_run *run,
 750                                                        struct kvm_vcpu *vcpu);
 751
 752 extern enum emulation_result kvm_mips_emulate_msafpe_exc(u32 cause,
 753                                                          u32 *opc,
 754                                                          struct kvm_run *run,
 755                                                          struct kvm_vcpu *vcpu);
 756
 757 extern enum emulation_result kvm_mips_emulate_fpe_exc(u32 cause,
 758                                                       u32 *opc,
 759                                                       struct kvm_run *run,
 760                                                       struct kvm_vcpu *vcpu);
 761
 762 extern enum emulation_result kvm_mips_emulate_msadis_exc(u32 cause,
 763                                                          u32 *opc,
 764                                                          struct kvm_run *run,
 765                                                          struct kvm_vcpu *vcpu);
 766
 767 extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
 768                                                          struct kvm_run *run);
 769
 770 u32 kvm_mips_read_count(struct kvm_vcpu *vcpu);
 771 void kvm_mips_write_count(struct kvm_vcpu *vcpu, u32 count);
 772 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, u32 compare, bool ack);
 773 void kvm_mips_init_count(struct kvm_vcpu *vcpu);
 774 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl);
 775 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume);
 776 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz);
 777 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu);
 778 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu);
 779 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu);
 780
 781 enum emulation_result kvm_mips_check_privilege(u32 cause,
 782                                                u32 *opc,
 783                                                struct kvm_run *run,
 784                                                struct kvm_vcpu *vcpu);
 785
 786 enum emulation_result kvm_mips_emulate_cache(union mips_instruction inst,
 787                                              u32 *opc,
 788                                              u32 cause,
 789                                              struct kvm_run *run,
 790                                              struct kvm_vcpu *vcpu);
 791 enum emulation_result kvm_mips_emulate_CP0(union mips_instruction inst,
 792                                            u32 *opc,
 793                                            u32 cause,
 794                                            struct kvm_run *run,
 795                                            struct kvm_vcpu *vcpu);
 796 enum emulation_result kvm_mips_emulate_store(union mips_instruction inst,
 797                                              u32 cause,
 798                                              struct kvm_run *run,
 799                                              struct kvm_vcpu *vcpu);
 800 enum emulation_result kvm_mips_emulate_load(union mips_instruction inst,
 801                                             u32 cause,
 802                                             struct kvm_run *run,
 803                                             struct kvm_vcpu *vcpu);
 804
 805 unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu);
 806 unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu);
 807 unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu);
 808 unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu);
 809
 810 /* Dynamic binary translation */
 811 extern int kvm_mips_trans_cache_index(union mips_instruction inst,
 812                                       u32 *opc, struct kvm_vcpu *vcpu);
 813 extern int kvm_mips_trans_cache_va(union mips_instruction inst, u32 *opc,
 814                                    struct kvm_vcpu *vcpu);
 815 extern int kvm_mips_trans_mfc0(union mips_instruction inst, u32 *opc,
 816                                struct kvm_vcpu *vcpu);
 817 extern int kvm_mips_trans_mtc0(union mips_instruction inst, u32 *opc,
 818                                struct kvm_vcpu *vcpu);
 819
 820 /* Misc */
 821 extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
 822 extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
 823
 824 static inline void kvm_arch_hardware_disable(void) {}
 825 static inline void kvm_arch_hardware_unsetup(void) {}
 826 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
 827 static inline void kvm_arch_free_memslot(struct kvm *kvm,
 828                 struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {}
 829 static inline void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) {}
 830 static inline void kvm_arch_flush_shadow_all(struct kvm *kvm) {}
 831 static inline void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
 832                 struct kvm_memory_slot *slot) {}
 833 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
 834 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {}
 835 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {}
 836 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
 837
 838 #endif /* __MIPS_KVM_HOST_H__ */