arch/mips/include/asm/kvm_host.h

   1 /*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   7 * Authors: Sanjay Lal <sanjayl@kymasys.com>
   8 */
   9
  10 #ifndef __MIPS_KVM_HOST_H__
  11 #define __MIPS_KVM_HOST_H__
  12
  13 #include <linux/cpumask.h>
  14 #include <linux/mutex.h>
  15 #include <linux/hrtimer.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/types.h>
  18 #include <linux/kvm.h>
  19 #include <linux/kvm_types.h>
  20 #include <linux/threads.h>
  21 #include <linux/spinlock.h>
  22
  23 #include <asm/inst.h>
  24 #include <asm/mipsregs.h>
  25
  26 /* MIPS KVM register ids */
  27 #define MIPS_CP0_32(_R, _S)                                     \
  28         (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
  29
  30 #define MIPS_CP0_64(_R, _S)                                     \
  31         (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
  32
  33 #define KVM_REG_MIPS_CP0_INDEX          MIPS_CP0_32(0, 0)
  34 #define KVM_REG_MIPS_CP0_ENTRYLO0       MIPS_CP0_64(2, 0)
  35 #define KVM_REG_MIPS_CP0_ENTRYLO1       MIPS_CP0_64(3, 0)
  36 #define KVM_REG_MIPS_CP0_CONTEXT        MIPS_CP0_64(4, 0)
  37 #define KVM_REG_MIPS_CP0_CONTEXTCONFIG  MIPS_CP0_32(4, 1)
  38 #define KVM_REG_MIPS_CP0_USERLOCAL      MIPS_CP0_64(4, 2)
  39 #define KVM_REG_MIPS_CP0_XCONTEXTCONFIG MIPS_CP0_64(4, 3)
  40 #define KVM_REG_MIPS_CP0_PAGEMASK       MIPS_CP0_32(5, 0)
  41 #define KVM_REG_MIPS_CP0_PAGEGRAIN      MIPS_CP0_32(5, 1)
  42 #define KVM_REG_MIPS_CP0_SEGCTL0        MIPS_CP0_64(5, 2)
  43 #define KVM_REG_MIPS_CP0_SEGCTL1        MIPS_CP0_64(5, 3)
  44 #define KVM_REG_MIPS_CP0_SEGCTL2        MIPS_CP0_64(5, 4)
  45 #define KVM_REG_MIPS_CP0_WIRED          MIPS_CP0_32(6, 0)
  46 #define KVM_REG_MIPS_CP0_HWRENA         MIPS_CP0_32(7, 0)
  47 #define KVM_REG_MIPS_CP0_BADVADDR       MIPS_CP0_64(8, 0)
  48 #define KVM_REG_MIPS_CP0_BADINSTR       MIPS_CP0_32(8, 1)
  49 #define KVM_REG_MIPS_CP0_BADINSTRP      MIPS_CP0_32(8, 2)
  50 #define KVM_REG_MIPS_CP0_COUNT          MIPS_CP0_32(9, 0)
  51 #define KVM_REG_MIPS_CP0_ENTRYHI        MIPS_CP0_64(10, 0)
  52 #define KVM_REG_MIPS_CP0_COMPARE        MIPS_CP0_32(11, 0)
  53 #define KVM_REG_MIPS_CP0_STATUS         MIPS_CP0_32(12, 0)
  54 #define KVM_REG_MIPS_CP0_INTCTL         MIPS_CP0_32(12, 1)
  55 #define KVM_REG_MIPS_CP0_CAUSE          MIPS_CP0_32(13, 0)
  56 #define KVM_REG_MIPS_CP0_EPC            MIPS_CP0_64(14, 0)
  57 #define KVM_REG_MIPS_CP0_PRID           MIPS_CP0_32(15, 0)
  58 #define KVM_REG_MIPS_CP0_EBASE          MIPS_CP0_64(15, 1)
  59 #define KVM_REG_MIPS_CP0_CONFIG         MIPS_CP0_32(16, 0)
  60 #define KVM_REG_MIPS_CP0_CONFIG1        MIPS_CP0_32(16, 1)
  61 #define KVM_REG_MIPS_CP0_CONFIG2        MIPS_CP0_32(16, 2)
  62 #define KVM_REG_MIPS_CP0_CONFIG3        MIPS_CP0_32(16, 3)
  63 #define KVM_REG_MIPS_CP0_CONFIG4        MIPS_CP0_32(16, 4)
  64 #define KVM_REG_MIPS_CP0_CONFIG5        MIPS_CP0_32(16, 5)
  65 #define KVM_REG_MIPS_CP0_CONFIG7        MIPS_CP0_32(16, 7)
  66 #define KVM_REG_MIPS_CP0_XCONTEXT       MIPS_CP0_64(20, 0)
  67 #define KVM_REG_MIPS_CP0_ERROREPC       MIPS_CP0_64(30, 0)
  68 #define KVM_REG_MIPS_CP0_KSCRATCH1      MIPS_CP0_64(31, 2)
  69 #define KVM_REG_MIPS_CP0_KSCRATCH2      MIPS_CP0_64(31, 3)
  70 #define KVM_REG_MIPS_CP0_KSCRATCH3      MIPS_CP0_64(31, 4)
  71 #define KVM_REG_MIPS_CP0_KSCRATCH4      MIPS_CP0_64(31, 5)
  72 #define KVM_REG_MIPS_CP0_KSCRATCH5      MIPS_CP0_64(31, 6)
  73 #define KVM_REG_MIPS_CP0_KSCRATCH6      MIPS_CP0_64(31, 7)
  74
  75
  76 #define KVM_MAX_VCPUS           8
  77 #define KVM_USER_MEM_SLOTS      8
  78 /* memory slots that does not exposed to userspace */
  79 #define KVM_PRIVATE_MEM_SLOTS   0
  80
  81 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
  82 #define KVM_HALT_POLL_NS_DEFAULT 500000
  83
  84 #ifdef CONFIG_KVM_MIPS_VZ
  85 extern unsigned long GUESTID_MASK;
  86 extern unsigned long GUESTID_FIRST_VERSION;
  87 extern unsigned long GUESTID_VERSION_MASK;
  88 #endif
  89
  90
  91 /*
  92  * Special address that contains the comm page, used for reducing # of traps
  93  * This needs to be within 32Kb of 0x0 (so the zero register can be used), but
  94  * preferably not at 0x0 so that most kernel NULL pointer dereferences can be
  95  * caught.
  96  */
  97 #define KVM_GUEST_COMMPAGE_ADDR         ((PAGE_SIZE > 0x8000) ? 0 : \
  98                                          (0x8000 - PAGE_SIZE))
  99
 100 #define KVM_GUEST_KERNEL_MODE(vcpu)     ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
 101                                         ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
 102
 103 #define KVM_GUEST_KUSEG                 0x00000000UL
 104 #define KVM_GUEST_KSEG0                 0x40000000UL
 105 #define KVM_GUEST_KSEG1                 0x40000000UL
 106 #define KVM_GUEST_KSEG23                0x60000000UL
 107 #define KVM_GUEST_KSEGX(a)              ((_ACAST32_(a)) & 0xe0000000)
 108 #define KVM_GUEST_CPHYSADDR(a)          ((_ACAST32_(a)) & 0x1fffffff)
 109
 110 #define KVM_GUEST_CKSEG0ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
 111 #define KVM_GUEST_CKSEG1ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
 112 #define KVM_GUEST_CKSEG23ADDR(a)        (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
 113
 114 /*
 115  * Map an address to a certain kernel segment
 116  */
 117 #define KVM_GUEST_KSEG0ADDR(a)          (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
 118 #define KVM_GUEST_KSEG1ADDR(a)          (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
 119 #define KVM_GUEST_KSEG23ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
 120
 121 #define KVM_INVALID_PAGE                0xdeadbeef
 122 #define KVM_INVALID_ADDR                0xdeadbeef
 123
 124 /*
 125  * EVA has overlapping user & kernel address spaces, so user VAs may be >
 126  * PAGE_OFFSET. For this reason we can't use the default KVM_HVA_ERR_BAD of
 127  * PAGE_OFFSET.
 128  */
 129
 130 #define KVM_HVA_ERR_BAD                 (-1UL)
 131 #define KVM_HVA_ERR_RO_BAD              (-2UL)
 132
 133 static inline bool kvm_is_error_hva(unsigned long addr)
 134 {
 135         return IS_ERR_VALUE(addr);
 136 }
 137
 138 struct kvm_vm_stat {
 139         ulong remote_tlb_flush;
 140 };
 141
 142 struct kvm_vcpu_stat {
 143         u64 wait_exits;
 144         u64 cache_exits;
 145         u64 signal_exits;
 146         u64 int_exits;
 147         u64 cop_unusable_exits;
 148         u64 tlbmod_exits;
 149         u64 tlbmiss_ld_exits;
 150         u64 tlbmiss_st_exits;
 151         u64 addrerr_st_exits;
 152         u64 addrerr_ld_exits;
 153         u64 syscall_exits;
 154         u64 resvd_inst_exits;
 155         u64 break_inst_exits;
 156         u64 trap_inst_exits;
 157         u64 msa_fpe_exits;
 158         u64 fpe_exits;
 159         u64 msa_disabled_exits;
 160         u64 flush_dcache_exits;
 161 #ifdef CONFIG_KVM_MIPS_VZ
 162         u64 vz_gpsi_exits;
 163         u64 vz_gsfc_exits;
 164         u64 vz_hc_exits;
 165         u64 vz_grr_exits;
 166         u64 vz_gva_exits;
 167         u64 vz_ghfc_exits;
 168         u64 vz_gpa_exits;
 169         u64 vz_resvd_exits;
 170 #endif
 171         u64 halt_successful_poll;
 172         u64 halt_attempted_poll;
 173         u64 halt_poll_invalid;
 174         u64 halt_wakeup;
 175 };
 176
 177 struct kvm_arch_memory_slot {
 178 };
 179
 180 struct kvm_arch {
 181         /* Guest physical mm */
 182         struct mm_struct gpa_mm;
 183         /* Mask of CPUs needing GPA ASID flush */
 184         cpumask_t asid_flush_mask;
 185 };
 186
 187 #define N_MIPS_COPROC_REGS      32
 188 #define N_MIPS_COPROC_SEL       8
 189
 190 struct mips_coproc {
 191         unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
 192 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
 193         unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
 194 #endif
 195 };
 196
 197 /*
 198  * Coprocessor 0 register names
 199  */
 200 #define MIPS_CP0_TLB_INDEX      0
 201 #define MIPS_CP0_TLB_RANDOM     1
 202 #define MIPS_CP0_TLB_LOW        2
 203 #define MIPS_CP0_TLB_LO0        2
 204 #define MIPS_CP0_TLB_LO1        3
 205 #define MIPS_CP0_TLB_CONTEXT    4
 206 #define MIPS_CP0_TLB_PG_MASK    5
 207 #define MIPS_CP0_TLB_WIRED      6
 208 #define MIPS_CP0_HWRENA         7
 209 #define MIPS_CP0_BAD_VADDR      8
 210 #define MIPS_CP0_COUNT          9
 211 #define MIPS_CP0_TLB_HI         10
 212 #define MIPS_CP0_COMPARE        11
 213 #define MIPS_CP0_STATUS         12
 214 #define MIPS_CP0_CAUSE          13
 215 #define MIPS_CP0_EXC_PC         14
 216 #define MIPS_CP0_PRID           15
 217 #define MIPS_CP0_CONFIG         16
 218 #define MIPS_CP0_LLADDR         17
 219 #define MIPS_CP0_WATCH_LO       18
 220 #define MIPS_CP0_WATCH_HI       19
 221 #define MIPS_CP0_TLB_XCONTEXT   20
 222 #define MIPS_CP0_ECC            26
 223 #define MIPS_CP0_CACHE_ERR      27
 224 #define MIPS_CP0_TAG_LO         28
 225 #define MIPS_CP0_TAG_HI         29
 226 #define MIPS_CP0_ERROR_PC       30
 227 #define MIPS_CP0_DEBUG          23
 228 #define MIPS_CP0_DEPC           24
 229 #define MIPS_CP0_PERFCNT        25
 230 #define MIPS_CP0_ERRCTL         26
 231 #define MIPS_CP0_DATA_LO        28
 232 #define MIPS_CP0_DATA_HI        29
 233 #define MIPS_CP0_DESAVE         31
 234
 235 #define MIPS_CP0_CONFIG_SEL     0
 236 #define MIPS_CP0_CONFIG1_SEL    1
 237 #define MIPS_CP0_CONFIG2_SEL    2
 238 #define MIPS_CP0_CONFIG3_SEL    3
 239 #define MIPS_CP0_CONFIG4_SEL    4
 240 #define MIPS_CP0_CONFIG5_SEL    5
 241
 242 #define MIPS_CP0_GUESTCTL2      10
 243 #define MIPS_CP0_GUESTCTL2_SEL  5
 244 #define MIPS_CP0_GTOFFSET       12
 245 #define MIPS_CP0_GTOFFSET_SEL   7
 246
 247 /* Resume Flags */
 248 #define RESUME_FLAG_DR          (1<<0)  /* Reload guest nonvolatile state? */
 249 #define RESUME_FLAG_HOST        (1<<1)  /* Resume host? */
 250
 251 #define RESUME_GUEST            0
 252 #define RESUME_GUEST_DR         RESUME_FLAG_DR
 253 #define RESUME_HOST             RESUME_FLAG_HOST
 254
 255 enum emulation_result {
 256         EMULATE_DONE,           /* no further processing */
 257         EMULATE_DO_MMIO,        /* kvm_run filled with MMIO request */
 258         EMULATE_FAIL,           /* can't emulate this instruction */
 259         EMULATE_WAIT,           /* WAIT instruction */
 260         EMULATE_PRIV_FAIL,
 261         EMULATE_EXCEPT,         /* A guest exception has been generated */
 262         EMULATE_HYPERCALL,      /* HYPCALL instruction */
 263 };
 264
 265 #define mips3_paddr_to_tlbpfn(x) \
 266         (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
 267 #define mips3_tlbpfn_to_paddr(x) \
 268         ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
 269
 270 #define MIPS3_PG_SHIFT          6
 271 #define MIPS3_PG_FRAME          0x3fffffc0
 272
 273 #define VPN2_MASK               0xffffe000
 274 #define KVM_ENTRYHI_ASID        MIPS_ENTRYHI_ASID
 275 #define TLB_IS_GLOBAL(x)        ((x).tlb_lo[0] & (x).tlb_lo[1] & ENTRYLO_G)
 276 #define TLB_VPN2(x)             ((x).tlb_hi & VPN2_MASK)
 277 #define TLB_ASID(x)             ((x).tlb_hi & KVM_ENTRYHI_ASID)
 278 #define TLB_LO_IDX(x, va)       (((va) >> PAGE_SHIFT) & 1)
 279 #define TLB_IS_VALID(x, va)     ((x).tlb_lo[TLB_LO_IDX(x, va)] & ENTRYLO_V)
 280 #define TLB_IS_DIRTY(x, va)     ((x).tlb_lo[TLB_LO_IDX(x, va)] & ENTRYLO_D)
 281 #define TLB_HI_VPN2_HIT(x, y)   ((TLB_VPN2(x) & ~(x).tlb_mask) ==       \
 282                                  ((y) & VPN2_MASK & ~(x).tlb_mask))
 283 #define TLB_HI_ASID_HIT(x, y)   (TLB_IS_GLOBAL(x) ||                    \
 284                                  TLB_ASID(x) == ((y) & KVM_ENTRYHI_ASID))
 285
 286 struct kvm_mips_tlb {
 287         long tlb_mask;
 288         long tlb_hi;
 289         long tlb_lo[2];
 290 };
 291
 292 #define KVM_NR_MEM_OBJS     4
 293
 294 /*
 295  * We don't want allocation failures within the mmu code, so we preallocate
 296  * enough memory for a single page fault in a cache.
 297  */
 298 struct kvm_mmu_memory_cache {
 299         int nobjs;
 300         void *objects[KVM_NR_MEM_OBJS];
 301 };
 302
 303 #define KVM_MIPS_AUX_FPU        0x1
 304 #define KVM_MIPS_AUX_MSA        0x2
 305
 306 #define KVM_MIPS_GUEST_TLB_SIZE 64
 307 struct kvm_vcpu_arch {
 308         void *guest_ebase;
 309         int (*vcpu_run)(struct kvm_run *run, struct kvm_vcpu *vcpu);
 310
 311         /* Host registers preserved across guest mode execution */
 312         unsigned long host_stack;
 313         unsigned long host_gp;
 314         unsigned long host_pgd;
 315         unsigned long host_entryhi;
 316
 317         /* Host CP0 registers used when handling exits from guest */
 318         unsigned long host_cp0_badvaddr;
 319         unsigned long host_cp0_epc;
 320         u32 host_cp0_cause;
 321         u32 host_cp0_guestctl0;
 322         u32 host_cp0_badinstr;
 323         u32 host_cp0_badinstrp;
 324
 325         /* GPRS */
 326         unsigned long gprs[32];
 327         unsigned long hi;
 328         unsigned long lo;
 329         unsigned long pc;
 330
 331         /* FPU State */
 332         struct mips_fpu_struct fpu;
 333         /* Which auxiliary state is loaded (KVM_MIPS_AUX_*) */
 334         unsigned int aux_inuse;
 335
 336         /* COP0 State */
 337         struct mips_coproc *cop0;
 338
 339         /* Host KSEG0 address of the EI/DI offset */
 340         void *kseg0_commpage;
 341
 342         /* Resume PC after MMIO completion */
 343         unsigned long io_pc;
 344         /* GPR used as IO source/target */
 345         u32 io_gpr;
 346
 347         struct hrtimer comparecount_timer;
 348         /* Count timer control KVM register */
 349         u32 count_ctl;
 350         /* Count bias from the raw time */
 351         u32 count_bias;
 352         /* Frequency of timer in Hz */
 353         u32 count_hz;
 354         /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */
 355         s64 count_dyn_bias;
 356         /* Resume time */
 357         ktime_t count_resume;
 358         /* Period of timer tick in ns */
 359         u64 count_period;
 360
 361         /* Bitmask of exceptions that are pending */
 362         unsigned long pending_exceptions;
 363
 364         /* Bitmask of pending exceptions to be cleared */
 365         unsigned long pending_exceptions_clr;
 366
 367         /* S/W Based TLB for guest */
 368         struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
 369
 370         /* Guest kernel/user [partial] mm */
 371         struct mm_struct guest_kernel_mm, guest_user_mm;
 372
 373         /* Guest ASID of last user mode execution */
 374         unsigned int last_user_gasid;
 375
 376         /* Cache some mmu pages needed inside spinlock regions */
 377         struct kvm_mmu_memory_cache mmu_page_cache;
 378
 379 #ifdef CONFIG_KVM_MIPS_VZ
 380         /* vcpu's vzguestid is different on each host cpu in an smp system */
 381         u32 vzguestid[NR_CPUS];
 382
 383         /* wired guest TLB entries */
 384         struct kvm_mips_tlb *wired_tlb;
 385         unsigned int wired_tlb_limit;
 386         unsigned int wired_tlb_used;
 387 #endif
 388
 389         /* Last CPU the VCPU state was loaded on */
 390         int last_sched_cpu;
 391         /* Last CPU the VCPU actually executed guest code on */
 392         int last_exec_cpu;
 393
 394         /* WAIT executed */
 395         int wait;
 396
 397         u8 fpu_enabled;
 398         u8 msa_enabled;
 399 };
 400
 401 static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg,
 402                                                 unsigned long val)
 403 {
 404         unsigned long temp;
 405         do {
 406                 __asm__ __volatile__(
 407                 "       .set    "MIPS_ISA_ARCH_LEVEL"           \n"
 408                 "       " __LL "%0, %1                          \n"
 409                 "       or      %0, %2                          \n"
 410                 "       " __SC  "%0, %1                         \n"
 411                 "       .set    mips0                           \n"
 412                 : "=&r" (temp), "+m" (*reg)
 413                 : "r" (val));
 414         } while (unlikely(!temp));
 415 }
 416
 417 static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg,
 418                                                   unsigned long val)
 419 {
 420         unsigned long temp;
 421         do {
 422                 __asm__ __volatile__(
 423                 "       .set    "MIPS_ISA_ARCH_LEVEL"           \n"
 424                 "       " __LL "%0, %1                          \n"
 425                 "       and     %0, %2                          \n"
 426                 "       " __SC  "%0, %1                         \n"
 427                 "       .set    mips0                           \n"
 428                 : "=&r" (temp), "+m" (*reg)
 429                 : "r" (~val));
 430         } while (unlikely(!temp));
 431 }
 432
 433 static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg,
 434                                                    unsigned long change,
 435                                                    unsigned long val)
 436 {
 437         unsigned long temp;
 438         do {
 439                 __asm__ __volatile__(
 440                 "       .set    "MIPS_ISA_ARCH_LEVEL"           \n"
 441                 "       " __LL "%0, %1                          \n"
 442                 "       and     %0, %2                          \n"
 443                 "       or      %0, %3                          \n"
 444                 "       " __SC  "%0, %1                         \n"
 445                 "       .set    mips0                           \n"
 446                 : "=&r" (temp), "+m" (*reg)
 447                 : "r" (~change), "r" (val & change));
 448         } while (unlikely(!temp));
 449 }
 450
 451 /* Guest register types, used in accessor build below */
 452 #define __KVMT32        u32
 453 #define __KVMTl unsigned long
 454
 455 /*
 456  * __BUILD_KVM_$ops_SAVED(): kvm_$op_sw_gc0_$reg()
 457  * These operate on the saved guest C0 state in RAM.
 458  */
 459
 460 /* Generate saved context simple accessors */
 461 #define __BUILD_KVM_RW_SAVED(name, type, _reg, sel)                     \
 462 static inline __KVMT##type kvm_read_sw_gc0_##name(struct mips_coproc *cop0) \
 463 {                                                                       \
 464         return cop0->reg[(_reg)][(sel)];                                \
 465 }                                                                       \
 466 static inline void kvm_write_sw_gc0_##name(struct mips_coproc *cop0,    \
 467                                            __KVMT##type val)            \
 468 {                                                                       \
 469         cop0->reg[(_reg)][(sel)] = val;                                 \
 470 }
 471
 472 /* Generate saved context bitwise modifiers */
 473 #define __BUILD_KVM_SET_SAVED(name, type, _reg, sel)                    \
 474 static inline void kvm_set_sw_gc0_##name(struct mips_coproc *cop0,      \
 475                                          __KVMT##type val)              \
 476 {                                                                       \
 477         cop0->reg[(_reg)][(sel)] |= val;                                \
 478 }                                                                       \
 479 static inline void kvm_clear_sw_gc0_##name(struct mips_coproc *cop0,    \
 480                                            __KVMT##type val)            \
 481 {                                                                       \
 482         cop0->reg[(_reg)][(sel)] &= ~val;                               \
 483 }                                                                       \
 484 static inline void kvm_change_sw_gc0_##name(struct mips_coproc *cop0,   \
 485                                             __KVMT##type mask,          \
 486                                             __KVMT##type val)           \
 487 {                                                                       \
 488         unsigned long _mask = mask;                                     \
 489         cop0->reg[(_reg)][(sel)] &= ~_mask;                             \
 490         cop0->reg[(_reg)][(sel)] |= val & _mask;                        \
 491 }
 492
 493 /* Generate saved context atomic bitwise modifiers */
 494 #define __BUILD_KVM_ATOMIC_SAVED(name, type, _reg, sel)                 \
 495 static inline void kvm_set_sw_gc0_##name(struct mips_coproc *cop0,      \
 496                                          __KVMT##type val)              \
 497 {                                                                       \
 498         _kvm_atomic_set_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val);   \
 499 }                                                                       \
 500 static inline void kvm_clear_sw_gc0_##name(struct mips_coproc *cop0,    \
 501                                            __KVMT##type val)            \
 502 {                                                                       \
 503         _kvm_atomic_clear_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val); \
 504 }                                                                       \
 505 static inline void kvm_change_sw_gc0_##name(struct mips_coproc *cop0,   \
 506                                             __KVMT##type mask,          \
 507                                             __KVMT##type val)           \
 508 {                                                                       \
 509         _kvm_atomic_change_c0_guest_reg(&cop0->reg[(_reg)][(sel)], mask, \
 510                                         val);                           \
 511 }
 512
 513 /*
 514  * __BUILD_KVM_$ops_VZ(): kvm_$op_vz_gc0_$reg()
 515  * These operate on the VZ guest C0 context in hardware.
 516  */
 517
 518 /* Generate VZ guest context simple accessors */
 519 #define __BUILD_KVM_RW_VZ(name, type, _reg, sel)                        \
 520 static inline __KVMT##type kvm_read_vz_gc0_##name(struct mips_coproc *cop0) \
 521 {                                                                       \
 522         return read_gc0_##name();                                       \
 523 }                                                                       \
 524 static inline void kvm_write_vz_gc0_##name(struct mips_coproc *cop0,    \
 525                                            __KVMT##type val)            \
 526 {                                                                       \
 527         write_gc0_##name(val);                                          \
 528 }
 529
 530 /* Generate VZ guest context bitwise modifiers */
 531 #define __BUILD_KVM_SET_VZ(name, type, _reg, sel)                       \
 532 static inline void kvm_set_vz_gc0_##name(struct mips_coproc *cop0,      \
 533                                          __KVMT##type val)              \
 534 {                                                                       \
 535         set_gc0_##name(val);                                            \
 536 }                                                                       \
 537 static inline void kvm_clear_vz_gc0_##name(struct mips_coproc *cop0,    \
 538                                            __KVMT##type val)            \
 539 {                                                                       \
 540         clear_gc0_##name(val);                                          \
 541 }                                                                       \
 542 static inline void kvm_change_vz_gc0_##name(struct mips_coproc *cop0,   \
 543                                             __KVMT##type mask,          \
 544                                             __KVMT##type val)           \
 545 {                                                                       \
 546         change_gc0_##name(mask, val);                                   \
 547 }
 548
 549 /* Generate VZ guest context save/restore to/from saved context */
 550 #define __BUILD_KVM_SAVE_VZ(name, _reg, sel)                    \
 551 static inline void kvm_restore_gc0_##name(struct mips_coproc *cop0)     \
 552 {                                                                       \
 553         write_gc0_##name(cop0->reg[(_reg)][(sel)]);                     \
 554 }                                                                       \
 555 static inline void kvm_save_gc0_##name(struct mips_coproc *cop0)        \
 556 {                                                                       \
 557         cop0->reg[(_reg)][(sel)] = read_gc0_##name();                   \
 558 }
 559
 560 /*
 561  * __BUILD_KVM_$ops_WRAP(): kvm_$op_$name1() -> kvm_$op_$name2()
 562  * These wrap a set of operations to provide them with a different name.
 563  */
 564
 565 /* Generate simple accessor wrapper */
 566 #define __BUILD_KVM_RW_WRAP(name1, name2, type)                         \
 567 static inline __KVMT##type kvm_read_##name1(struct mips_coproc *cop0)   \
 568 {                                                                       \
 569         return kvm_read_##name2(cop0);                                  \
 570 }                                                                       \
 571 static inline void kvm_write_##name1(struct mips_coproc *cop0,          \
 572                                      __KVMT##type val)                  \
 573 {                                                                       \
 574         kvm_write_##name2(cop0, val);                                   \
 575 }
 576
 577 /* Generate bitwise modifier wrapper */
 578 #define __BUILD_KVM_SET_WRAP(name1, name2, type)                        \
 579 static inline void kvm_set_##name1(struct mips_coproc *cop0,            \
 580                                    __KVMT##type val)                    \
 581 {                                                                       \
 582         kvm_set_##name2(cop0, val);                                     \
 583 }                                                                       \
 584 static inline void kvm_clear_##name1(struct mips_coproc *cop0,          \
 585                                      __KVMT##type val)                  \
 586 {                                                                       \
 587         kvm_clear_##name2(cop0, val);                                   \
 588 }                                                                       \
 589 static inline void kvm_change_##name1(struct mips_coproc *cop0,         \
 590                                       __KVMT##type mask,                \
 591                                       __KVMT##type val)                 \
 592 {                                                                       \
 593         kvm_change_##name2(cop0, mask, val);                            \
 594 }
 595
 596 /*
 597  * __BUILD_KVM_$ops_SW(): kvm_$op_c0_guest_$reg() -> kvm_$op_sw_gc0_$reg()
 598  * These generate accessors operating on the saved context in RAM, and wrap them
 599  * with the common guest C0 accessors (for use by common emulation code).
 600  */
 601
 602 #define __BUILD_KVM_RW_SW(name, type, _reg, sel)                        \
 603         __BUILD_KVM_RW_SAVED(name, type, _reg, sel)                     \
 604         __BUILD_KVM_RW_WRAP(c0_guest_##name, sw_gc0_##name, type)
 605
 606 #define __BUILD_KVM_SET_SW(name, type, _reg, sel)                       \
 607         __BUILD_KVM_SET_SAVED(name, type, _reg, sel)                    \
 608         __BUILD_KVM_SET_WRAP(c0_guest_##name, sw_gc0_##name, type)
 609
 610 #define __BUILD_KVM_ATOMIC_SW(name, type, _reg, sel)                    \
 611         __BUILD_KVM_ATOMIC_SAVED(name, type, _reg, sel)                 \
 612         __BUILD_KVM_SET_WRAP(c0_guest_##name, sw_gc0_##name, type)
 613
 614 #ifndef CONFIG_KVM_MIPS_VZ
 615
 616 /*
 617  * T&E (trap & emulate software based virtualisation)
 618  * We generate the common accessors operating exclusively on the saved context
 619  * in RAM.
 620  */
 621
 622 #define __BUILD_KVM_RW_HW       __BUILD_KVM_RW_SW
 623 #define __BUILD_KVM_SET_HW      __BUILD_KVM_SET_SW
 624 #define __BUILD_KVM_ATOMIC_HW   __BUILD_KVM_ATOMIC_SW
 625
 626 #else
 627
 628 /*
 629  * VZ (hardware assisted virtualisation)
 630  * These macros use the active guest state in VZ mode (hardware registers),
 631  */
 632
 633 /*
 634  * __BUILD_KVM_$ops_HW(): kvm_$op_c0_guest_$reg() -> kvm_$op_vz_gc0_$reg()
 635  * These generate accessors operating on the VZ guest context in hardware, and
 636  * wrap them with the common guest C0 accessors (for use by common emulation
 637  * code).
 638  *
 639  * Accessors operating on the saved context in RAM are also generated to allow
 640  * convenient explicit saving and restoring of the state.
 641  */
 642
 643 #define __BUILD_KVM_RW_HW(name, type, _reg, sel)                        \
 644         __BUILD_KVM_RW_SAVED(name, type, _reg, sel)                     \
 645         __BUILD_KVM_RW_VZ(name, type, _reg, sel)                        \
 646         __BUILD_KVM_RW_WRAP(c0_guest_##name, vz_gc0_##name, type)       \
 647         __BUILD_KVM_SAVE_VZ(name, _reg, sel)
 648
 649 #define __BUILD_KVM_SET_HW(name, type, _reg, sel)                       \
 650         __BUILD_KVM_SET_SAVED(name, type, _reg, sel)                    \
 651         __BUILD_KVM_SET_VZ(name, type, _reg, sel)                       \
 652         __BUILD_KVM_SET_WRAP(c0_guest_##name, vz_gc0_##name, type)
 653
 654 /*
 655  * We can't do atomic modifications of COP0 state if hardware can modify it.
 656  * Races must be handled explicitly.
 657  */
 658 #define __BUILD_KVM_ATOMIC_HW   __BUILD_KVM_SET_HW
 659
 660 #endif
 661
 662 /*
 663  * Define accessors for CP0 registers that are accessible to the guest. These
 664  * are primarily used by common emulation code, which may need to access the
 665  * registers differently depending on the implementation.
 666  *
 667  *    fns_hw/sw    name     type    reg num         select
 668  */
 669 __BUILD_KVM_RW_HW(index,          32, MIPS_CP0_TLB_INDEX,    0)
 670 __BUILD_KVM_RW_HW(entrylo0,       l,  MIPS_CP0_TLB_LO0,      0)
 671 __BUILD_KVM_RW_HW(entrylo1,       l,  MIPS_CP0_TLB_LO1,      0)
 672 __BUILD_KVM_RW_HW(context,        l,  MIPS_CP0_TLB_CONTEXT,  0)
 673 __BUILD_KVM_RW_HW(contextconfig,  32, MIPS_CP0_TLB_CONTEXT,  1)
 674 __BUILD_KVM_RW_HW(userlocal,      l,  MIPS_CP0_TLB_CONTEXT,  2)
 675 __BUILD_KVM_RW_HW(xcontextconfig, l,  MIPS_CP0_TLB_CONTEXT,  3)
 676 __BUILD_KVM_RW_HW(pagemask,       l,  MIPS_CP0_TLB_PG_MASK,  0)
 677 __BUILD_KVM_RW_HW(pagegrain,      32, MIPS_CP0_TLB_PG_MASK,  1)
 678 __BUILD_KVM_RW_HW(segctl0,        l,  MIPS_CP0_TLB_PG_MASK,  2)
 679 __BUILD_KVM_RW_HW(segctl1,        l,  MIPS_CP0_TLB_PG_MASK,  3)
 680 __BUILD_KVM_RW_HW(segctl2,        l,  MIPS_CP0_TLB_PG_MASK,  4)
 681 __BUILD_KVM_RW_HW(wired,          32, MIPS_CP0_TLB_WIRED,    0)
 682 __BUILD_KVM_RW_HW(hwrena,         32, MIPS_CP0_HWRENA,       0)
 683 __BUILD_KVM_RW_HW(badvaddr,       l,  MIPS_CP0_BAD_VADDR,    0)
 684 __BUILD_KVM_RW_HW(badinstr,       32, MIPS_CP0_BAD_VADDR,    1)
 685 __BUILD_KVM_RW_HW(badinstrp,      32, MIPS_CP0_BAD_VADDR,    2)
 686 __BUILD_KVM_RW_SW(count,          32, MIPS_CP0_COUNT,        0)
 687 __BUILD_KVM_RW_HW(entryhi,        l,  MIPS_CP0_TLB_HI,       0)
 688 __BUILD_KVM_RW_HW(compare,        32, MIPS_CP0_COMPARE,      0)
 689 __BUILD_KVM_RW_HW(status,         32, MIPS_CP0_STATUS,       0)
 690 __BUILD_KVM_RW_HW(intctl,         32, MIPS_CP0_STATUS,       1)
 691 __BUILD_KVM_RW_HW(cause,          32, MIPS_CP0_CAUSE,        0)
 692 __BUILD_KVM_RW_HW(epc,            l,  MIPS_CP0_EXC_PC,       0)
 693 __BUILD_KVM_RW_SW(prid,           32, MIPS_CP0_PRID,         0)
 694 __BUILD_KVM_RW_HW(ebase,          l,  MIPS_CP0_PRID,         1)
 695 __BUILD_KVM_RW_HW(config,         32, MIPS_CP0_CONFIG,       0)
 696 __BUILD_KVM_RW_HW(config1,        32, MIPS_CP0_CONFIG,       1)
 697 __BUILD_KVM_RW_HW(config2,        32, MIPS_CP0_CONFIG,       2)
 698 __BUILD_KVM_RW_HW(config3,        32, MIPS_CP0_CONFIG,       3)
 699 __BUILD_KVM_RW_HW(config4,        32, MIPS_CP0_CONFIG,       4)
 700 __BUILD_KVM_RW_HW(config5,        32, MIPS_CP0_CONFIG,       5)
 701 __BUILD_KVM_RW_HW(config6,        32, MIPS_CP0_CONFIG,       6)
 702 __BUILD_KVM_RW_HW(config7,        32, MIPS_CP0_CONFIG,       7)
 703 __BUILD_KVM_RW_HW(xcontext,       l,  MIPS_CP0_TLB_XCONTEXT, 0)
 704 __BUILD_KVM_RW_HW(errorepc,       l,  MIPS_CP0_ERROR_PC,     0)
 705 __BUILD_KVM_RW_HW(kscratch1,      l,  MIPS_CP0_DESAVE,       2)
 706 __BUILD_KVM_RW_HW(kscratch2,      l,  MIPS_CP0_DESAVE,       3)
 707 __BUILD_KVM_RW_HW(kscratch3,      l,  MIPS_CP0_DESAVE,       4)
 708 __BUILD_KVM_RW_HW(kscratch4,      l,  MIPS_CP0_DESAVE,       5)
 709 __BUILD_KVM_RW_HW(kscratch5,      l,  MIPS_CP0_DESAVE,       6)
 710 __BUILD_KVM_RW_HW(kscratch6,      l,  MIPS_CP0_DESAVE,       7)
 711
 712 /* Bitwise operations (on HW state) */
 713 __BUILD_KVM_SET_HW(status,        32, MIPS_CP0_STATUS,       0)
 714 /* Cause can be modified asynchronously from hardirq hrtimer callback */
 715 __BUILD_KVM_ATOMIC_HW(cause,      32, MIPS_CP0_CAUSE,        0)
 716 __BUILD_KVM_SET_HW(ebase,         l,  MIPS_CP0_PRID,         1)
 717
 718 /* Bitwise operations (on saved state) */
 719 __BUILD_KVM_SET_SAVED(config,     32, MIPS_CP0_CONFIG,       0)
 720 __BUILD_KVM_SET_SAVED(config1,    32, MIPS_CP0_CONFIG,       1)
 721 __BUILD_KVM_SET_SAVED(config2,    32, MIPS_CP0_CONFIG,       2)
 722 __BUILD_KVM_SET_SAVED(config3,    32, MIPS_CP0_CONFIG,       3)
 723 __BUILD_KVM_SET_SAVED(config4,    32, MIPS_CP0_CONFIG,       4)
 724 __BUILD_KVM_SET_SAVED(config5,    32, MIPS_CP0_CONFIG,       5)
 725
 726 /* Helpers */
 727
 728 static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch *vcpu)
 729 {
 730         return (!__builtin_constant_p(raw_cpu_has_fpu) || raw_cpu_has_fpu) &&
 731                 vcpu->fpu_enabled;
 732 }
 733
 734 static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch *vcpu)
 735 {
 736         return kvm_mips_guest_can_have_fpu(vcpu) &&
 737                 kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP;
 738 }
 739
 740 static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch *vcpu)
 741 {
 742         return (!__builtin_constant_p(cpu_has_msa) || cpu_has_msa) &&
 743                 vcpu->msa_enabled;
 744 }
 745
 746 static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch *vcpu)
 747 {
 748         return kvm_mips_guest_can_have_msa(vcpu) &&
 749                 kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA;
 750 }
 751
 752 struct kvm_mips_callbacks {
 753         int (*handle_cop_unusable)(struct kvm_vcpu *vcpu);
 754         int (*handle_tlb_mod)(struct kvm_vcpu *vcpu);
 755         int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu);
 756         int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu);
 757         int (*handle_addr_err_st)(struct kvm_vcpu *vcpu);
 758         int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu);
 759         int (*handle_syscall)(struct kvm_vcpu *vcpu);
 760         int (*handle_res_inst)(struct kvm_vcpu *vcpu);
 761         int (*handle_break)(struct kvm_vcpu *vcpu);
 762         int (*handle_trap)(struct kvm_vcpu *vcpu);
 763         int (*handle_msa_fpe)(struct kvm_vcpu *vcpu);
 764         int (*handle_fpe)(struct kvm_vcpu *vcpu);
 765         int (*handle_msa_disabled)(struct kvm_vcpu *vcpu);
 766         int (*handle_guest_exit)(struct kvm_vcpu *vcpu);
 767         int (*hardware_enable)(void);
 768         void (*hardware_disable)(void);
 769         int (*check_extension)(struct kvm *kvm, long ext);
 770         int (*vcpu_init)(struct kvm_vcpu *vcpu);
 771         void (*vcpu_uninit)(struct kvm_vcpu *vcpu);
 772         int (*vcpu_setup)(struct kvm_vcpu *vcpu);
 773         void (*flush_shadow_all)(struct kvm *kvm);
 774         /*
 775          * Must take care of flushing any cached GPA PTEs (e.g. guest entries in
 776          * VZ root TLB, or T&E GVA page tables and corresponding root TLB
 777          * mappings).
 778          */
 779         void (*flush_shadow_memslot)(struct kvm *kvm,
 780                                      const struct kvm_memory_slot *slot);
 781         gpa_t (*gva_to_gpa)(gva_t gva);
 782         void (*queue_timer_int)(struct kvm_vcpu *vcpu);
 783         void (*dequeue_timer_int)(struct kvm_vcpu *vcpu);
 784         void (*queue_io_int)(struct kvm_vcpu *vcpu,
 785                              struct kvm_mips_interrupt *irq);
 786         void (*dequeue_io_int)(struct kvm_vcpu *vcpu,
 787                                struct kvm_mips_interrupt *irq);
 788         int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority,
 789                            u32 cause);
 790         int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority,
 791                          u32 cause);
 792         unsigned long (*num_regs)(struct kvm_vcpu *vcpu);
 793         int (*copy_reg_indices)(struct kvm_vcpu *vcpu, u64 __user *indices);
 794         int (*get_one_reg)(struct kvm_vcpu *vcpu,
 795                            const struct kvm_one_reg *reg, s64 *v);
 796         int (*set_one_reg)(struct kvm_vcpu *vcpu,
 797                            const struct kvm_one_reg *reg, s64 v);
 798         int (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu);
 799         int (*vcpu_put)(struct kvm_vcpu *vcpu, int cpu);
 800         int (*vcpu_run)(struct kvm_run *run, struct kvm_vcpu *vcpu);
 801         void (*vcpu_reenter)(struct kvm_run *run, struct kvm_vcpu *vcpu);
 802 };
 803 extern struct kvm_mips_callbacks *kvm_mips_callbacks;
 804 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
 805
 806 /* Debug: dump vcpu state */
 807 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
 808
 809 extern int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu);
 810
 811 /* Building of entry/exception code */
 812 int kvm_mips_entry_setup(void);
 813 void *kvm_mips_build_vcpu_run(void *addr);
 814 void *kvm_mips_build_tlb_refill_exception(void *addr, void *handler);
 815 void *kvm_mips_build_exception(void *addr, void *handler);
 816 void *kvm_mips_build_exit(void *addr);
 817
 818 /* FPU/MSA context management */
 819 void __kvm_save_fpu(struct kvm_vcpu_arch *vcpu);
 820 void __kvm_restore_fpu(struct kvm_vcpu_arch *vcpu);
 821 void __kvm_restore_fcsr(struct kvm_vcpu_arch *vcpu);
 822 void __kvm_save_msa(struct kvm_vcpu_arch *vcpu);
 823 void __kvm_restore_msa(struct kvm_vcpu_arch *vcpu);
 824 void __kvm_restore_msa_upper(struct kvm_vcpu_arch *vcpu);
 825 void __kvm_restore_msacsr(struct kvm_vcpu_arch *vcpu);
 826 void kvm_own_fpu(struct kvm_vcpu *vcpu);
 827 void kvm_own_msa(struct kvm_vcpu *vcpu);
 828 void kvm_drop_fpu(struct kvm_vcpu *vcpu);
 829 void kvm_lose_fpu(struct kvm_vcpu *vcpu);
 830
 831 /* TLB handling */
 832 u32 kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
 833
 834 u32 kvm_get_user_asid(struct kvm_vcpu *vcpu);
 835
 836 u32 kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
 837
 838 #ifdef CONFIG_KVM_MIPS_VZ
 839 int kvm_mips_handle_vz_root_tlb_fault(unsigned long badvaddr,
 840                                       struct kvm_vcpu *vcpu, bool write_fault);
 841 #endif
 842 extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
 843                                            struct kvm_vcpu *vcpu,
 844                                            bool write_fault);
 845
 846 extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
 847                                               struct kvm_vcpu *vcpu);
 848
 849 extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
 850                                                 struct kvm_mips_tlb *tlb,
 851                                                 unsigned long gva,
 852                                                 bool write_fault);
 853
 854 extern enum emulation_result kvm_mips_handle_tlbmiss(u32 cause,
 855                                                      u32 *opc,
 856                                                      struct kvm_run *run,
 857                                                      struct kvm_vcpu *vcpu,
 858                                                      bool write_fault);
 859
 860 extern void kvm_mips_dump_host_tlbs(void);
 861 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
 862 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi,
 863                                  bool user, bool kernel);
 864
 865 extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
 866                                      unsigned long entryhi);
 867
 868 #ifdef CONFIG_KVM_MIPS_VZ
 869 int kvm_vz_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
 870 int kvm_vz_guest_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long gva,
 871                             unsigned long *gpa);
 872 void kvm_vz_local_flush_roottlb_all_guests(void);
 873 void kvm_vz_local_flush_guesttlb_all(void);
 874 void kvm_vz_save_guesttlb(struct kvm_mips_tlb *buf, unsigned int index,
 875                           unsigned int count);
 876 void kvm_vz_load_guesttlb(const struct kvm_mips_tlb *buf, unsigned int index,
 877                           unsigned int count);
 878 #endif
 879
 880 void kvm_mips_suspend_mm(int cpu);
 881 void kvm_mips_resume_mm(int cpu);
 882
 883 /* MMU handling */
 884
 885 /**
 886  * enum kvm_mips_flush - Types of MMU flushes.
 887  * @KMF_USER:   Flush guest user virtual memory mappings.
 888  *              Guest USeg only.
 889  * @KMF_KERN:   Flush guest kernel virtual memory mappings.
 890  *              Guest USeg and KSeg2/3.
 891  * @KMF_GPA:    Flush guest physical memory mappings.
 892  *              Also includes KSeg0 if KMF_KERN is set.
 893  */
 894 enum kvm_mips_flush {
 895         KMF_USER        = 0x0,
 896         KMF_KERN        = 0x1,
 897         KMF_GPA         = 0x2,
 898 };
 899 void kvm_mips_flush_gva_pt(pgd_t *pgd, enum kvm_mips_flush flags);
 900 bool kvm_mips_flush_gpa_pt(struct kvm *kvm, gfn_t start_gfn, gfn_t end_gfn);
 901 int kvm_mips_mkclean_gpa_pt(struct kvm *kvm, gfn_t start_gfn, gfn_t end_gfn);
 902 pgd_t *kvm_pgd_alloc(void);
 903 void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
 904 void kvm_trap_emul_invalidate_gva(struct kvm_vcpu *vcpu, unsigned long addr,
 905                                   bool user);
 906 void kvm_trap_emul_gva_lockless_begin(struct kvm_vcpu *vcpu);
 907 void kvm_trap_emul_gva_lockless_end(struct kvm_vcpu *vcpu);
 908
 909 enum kvm_mips_fault_result {
 910         KVM_MIPS_MAPPED = 0,
 911         KVM_MIPS_GVA,
 912         KVM_MIPS_GPA,
 913         KVM_MIPS_TLB,
 914         KVM_MIPS_TLBINV,
 915         KVM_MIPS_TLBMOD,
 916 };
 917 enum kvm_mips_fault_result kvm_trap_emul_gva_fault(struct kvm_vcpu *vcpu,
 918                                                    unsigned long gva,
 919                                                    bool write);
 920
 921 #define KVM_ARCH_WANT_MMU_NOTIFIER
 922 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
 923 int kvm_unmap_hva_range(struct kvm *kvm,
 924                         unsigned long start, unsigned long end);
 925 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
 926 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
 927 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
 928
 929 static inline void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
 930                                                          unsigned long address)
 931 {
 932 }
 933
 934 /* Emulation */
 935 int kvm_get_inst(u32 *opc, struct kvm_vcpu *vcpu, u32 *out);
 936 enum emulation_result update_pc(struct kvm_vcpu *vcpu, u32 cause);
 937 int kvm_get_badinstr(u32 *opc, struct kvm_vcpu *vcpu, u32 *out);
 938 int kvm_get_badinstrp(u32 *opc, struct kvm_vcpu *vcpu, u32 *out);
 939
 940 /**
 941  * kvm_is_ifetch_fault() - Find whether a TLBL exception is due to ifetch fault.
 942  * @vcpu:       Virtual CPU.
 943  *
 944  * Returns:     Whether the TLBL exception was likely due to an instruction
 945  *              fetch fault rather than a data load fault.
 946  */
 947 static inline bool kvm_is_ifetch_fault(struct kvm_vcpu_arch *vcpu)
 948 {
 949         unsigned long badvaddr = vcpu->host_cp0_badvaddr;
 950         unsigned long epc = msk_isa16_mode(vcpu->pc);
 951         u32 cause = vcpu->host_cp0_cause;
 952
 953         if (epc == badvaddr)
 954                 return true;
 955
 956         /*
 957          * Branches may be 32-bit or 16-bit instructions.
 958          * This isn't exact, but we don't really support MIPS16 or microMIPS yet
 959          * in KVM anyway.
 960          */
 961         if ((cause & CAUSEF_BD) && badvaddr - epc <= 4)
 962                 return true;
 963
 964         return false;
 965 }
 966
 967 extern enum emulation_result kvm_mips_emulate_inst(u32 cause,
 968                                                    u32 *opc,
 969                                                    struct kvm_run *run,
 970                                                    struct kvm_vcpu *vcpu);
 971
 972 long kvm_mips_guest_exception_base(struct kvm_vcpu *vcpu);
 973
 974 extern enum emulation_result kvm_mips_emulate_syscall(u32 cause,
 975                                                       u32 *opc,
 976                                                       struct kvm_run *run,
 977                                                       struct kvm_vcpu *vcpu);
 978
 979 extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(u32 cause,
 980                                                          u32 *opc,
 981                                                          struct kvm_run *run,
 982                                                          struct kvm_vcpu *vcpu);
 983
 984 extern enum emulation_result kvm_mips_emulate_tlbinv_ld(u32 cause,
 985                                                         u32 *opc,
 986                                                         struct kvm_run *run,
 987                                                         struct kvm_vcpu *vcpu);
 988
 989 extern enum emulation_result kvm_mips_emulate_tlbmiss_st(u32 cause,
 990                                                          u32 *opc,
 991                                                          struct kvm_run *run,
 992                                                          struct kvm_vcpu *vcpu);
 993
 994 extern enum emulation_result kvm_mips_emulate_tlbinv_st(u32 cause,
 995                                                         u32 *opc,
 996                                                         struct kvm_run *run,
 997                                                         struct kvm_vcpu *vcpu);
 998
 999 extern enum emulation_result kvm_mips_emulate_tlbmod(u32 cause,
1000                                                      u32 *opc,
1001                                                      struct kvm_run *run,
1002                                                      struct kvm_vcpu *vcpu);
1003
1004 extern enum emulation_result kvm_mips_emulate_fpu_exc(u32 cause,
1005                                                       u32 *opc,
1006                                                       struct kvm_run *run,
1007                                                       struct kvm_vcpu *vcpu);
1008
1009 extern enum emulation_result kvm_mips_handle_ri(u32 cause,
1010                                                 u32 *opc,
1011                                                 struct kvm_run *run,
1012                                                 struct kvm_vcpu *vcpu);
1013
1014 extern enum emulation_result kvm_mips_emulate_ri_exc(u32 cause,
1015                                                      u32 *opc,
1016                                                      struct kvm_run *run,
1017                                                      struct kvm_vcpu *vcpu);
1018
1019 extern enum emulation_result kvm_mips_emulate_bp_exc(u32 cause,
1020                                                      u32 *opc,
1021                                                      struct kvm_run *run,
1022                                                      struct kvm_vcpu *vcpu);
1023
1024 extern enum emulation_result kvm_mips_emulate_trap_exc(u32 cause,
1025                                                        u32 *opc,
1026                                                        struct kvm_run *run,
1027                                                        struct kvm_vcpu *vcpu);
1028
1029 extern enum emulation_result kvm_mips_emulate_msafpe_exc(u32 cause,
1030                                                          u32 *opc,
1031                                                          struct kvm_run *run,
1032                                                          struct kvm_vcpu *vcpu);
1033
1034 extern enum emulation_result kvm_mips_emulate_fpe_exc(u32 cause,
1035                                                       u32 *opc,
1036                                                       struct kvm_run *run,
1037                                                       struct kvm_vcpu *vcpu);
1038
1039 extern enum emulation_result kvm_mips_emulate_msadis_exc(u32 cause,
1040                                                          u32 *opc,
1041                                                          struct kvm_run *run,
1042                                                          struct kvm_vcpu *vcpu);
1043
1044 extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
1045                                                          struct kvm_run *run);
1046
1047 u32 kvm_mips_read_count(struct kvm_vcpu *vcpu);
1048 void kvm_mips_write_count(struct kvm_vcpu *vcpu, u32 count);
1049 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, u32 compare, bool ack);
1050 void kvm_mips_init_count(struct kvm_vcpu *vcpu, unsigned long count_hz);
1051 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl);
1052 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume);
1053 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz);
1054 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu);
1055 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu);
1056 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu);
1057
1058 enum emulation_result kvm_mips_check_privilege(u32 cause,
1059                                                u32 *opc,
1060                                                struct kvm_run *run,
1061                                                struct kvm_vcpu *vcpu);
1062
1063 enum emulation_result kvm_mips_emulate_cache(union mips_instruction inst,
1064                                              u32 *opc,
1065                                              u32 cause,
1066                                              struct kvm_run *run,
1067                                              struct kvm_vcpu *vcpu);
1068 enum emulation_result kvm_mips_emulate_CP0(union mips_instruction inst,
1069                                            u32 *opc,
1070                                            u32 cause,
1071                                            struct kvm_run *run,
1072                                            struct kvm_vcpu *vcpu);
1073 enum emulation_result kvm_mips_emulate_store(union mips_instruction inst,
1074                                              u32 cause,
1075                                              struct kvm_run *run,
1076                                              struct kvm_vcpu *vcpu);
1077 enum emulation_result kvm_mips_emulate_load(union mips_instruction inst,
1078                                             u32 cause,
1079                                             struct kvm_run *run,
1080                                             struct kvm_vcpu *vcpu);
1081
1082 /* COP0 */
1083 enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu *vcpu);
1084
1085 unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu);
1086 unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu);
1087 unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu);
1088 unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu);
1089
1090 /* Hypercalls (hypcall.c) */
1091
1092 enum emulation_result kvm_mips_emul_hypcall(struct kvm_vcpu *vcpu,
1093                                             union mips_instruction inst);
1094 int kvm_mips_handle_hypcall(struct kvm_vcpu *vcpu);
1095
1096 /* Dynamic binary translation */
1097 extern int kvm_mips_trans_cache_index(union mips_instruction inst,
1098                                       u32 *opc, struct kvm_vcpu *vcpu);
1099 extern int kvm_mips_trans_cache_va(union mips_instruction inst, u32 *opc,
1100                                    struct kvm_vcpu *vcpu);
1101 extern int kvm_mips_trans_mfc0(union mips_instruction inst, u32 *opc,
1102                                struct kvm_vcpu *vcpu);
1103 extern int kvm_mips_trans_mtc0(union mips_instruction inst, u32 *opc,
1104                                struct kvm_vcpu *vcpu);
1105
1106 /* Misc */
1107 extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
1108 extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
1109
1110 static inline void kvm_arch_hardware_unsetup(void) {}
1111 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
1112 static inline void kvm_arch_free_memslot(struct kvm *kvm,
1113                 struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {}
1114 static inline void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) {}
1115 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
1116 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {}
1117 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {}
1118 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
1119
1120 #endif /* __MIPS_KVM_HOST_H__ */