2 * GPIO functions for Au1000, Au1500, Au1100, Au1550, Au1200
4 * Copyright (c) 2009 Manuel Lauss.
6 * Licensed under the terms outlined in the file COPYING.
9 #ifndef _ALCHEMY_GPIO_AU1000_H_
10 #define _ALCHEMY_GPIO_AU1000_H_
12 #include <asm/mach-au1x00/au1000.h>
14 /* The default GPIO numberspace as documented in the Alchemy manuals.
15 * GPIO0-31 from GPIO1 block, GPIO200-215 from GPIO2 block.
17 #define ALCHEMY_GPIO1_BASE 0
18 #define ALCHEMY_GPIO2_BASE 200
20 #define ALCHEMY_GPIO1_NUM 32
21 #define ALCHEMY_GPIO2_NUM 16
22 #define ALCHEMY_GPIO1_MAX (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1)
23 #define ALCHEMY_GPIO2_MAX (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1)
25 #define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off))
29 static inline int au1000_gpio1_to_irq(int gpio)
31 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
34 static inline int au1000_gpio2_to_irq(int gpio)
39 static inline int au1000_irq_to_gpio(int irq)
41 if ((irq >= AU1000_GPIO0_INT) && (irq <= AU1000_GPIO31_INT))
42 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO0_INT) + 0;
47 static inline int au1500_gpio1_to_irq(int gpio)
49 gpio -= ALCHEMY_GPIO1_BASE;
54 case 23 ... 28: return MAKE_IRQ(1, gpio);
60 static inline int au1500_gpio2_to_irq(int gpio)
62 gpio -= ALCHEMY_GPIO2_BASE;
65 case 0 ... 3: return MAKE_IRQ(1, 16 + gpio - 0);
66 case 4 ... 5: return MAKE_IRQ(1, 21 + gpio - 4);
67 case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6);
73 static inline int au1500_irq_to_gpio(int irq)
76 case AU1500_GPIO0_INT ... AU1500_GPIO15_INT:
77 case AU1500_GPIO20_INT:
78 case AU1500_GPIO23_INT ... AU1500_GPIO28_INT:
79 return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO0_INT) + 0;
80 case AU1500_GPIO200_INT ... AU1500_GPIO203_INT:
81 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO200_INT) + 0;
82 case AU1500_GPIO204_INT ... AU1500_GPIO205_INT:
83 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO204_INT) + 4;
84 case AU1500_GPIO206_INT ... AU1500_GPIO207_INT:
85 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO206_INT) + 6;
86 case AU1500_GPIO208_215_INT:
87 return ALCHEMY_GPIO2_BASE + 8;
93 static inline int au1100_gpio1_to_irq(int gpio)
95 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
98 static inline int au1100_gpio2_to_irq(int gpio)
100 gpio -= ALCHEMY_GPIO2_BASE;
102 if ((gpio >= 8) && (gpio <= 15))
103 return MAKE_IRQ(0, 29); /* shared GPIO208_215 */
108 static inline int au1100_irq_to_gpio(int irq)
111 case AU1100_GPIO0_INT ... AU1100_GPIO31_INT:
112 return ALCHEMY_GPIO1_BASE + (irq - AU1100_GPIO0_INT) + 0;
113 case AU1100_GPIO208_215_INT:
114 return ALCHEMY_GPIO2_BASE + 8;
120 static inline int au1550_gpio1_to_irq(int gpio)
122 gpio -= ALCHEMY_GPIO1_BASE;
126 case 20 ... 28: return MAKE_IRQ(1, gpio);
127 case 16 ... 17: return MAKE_IRQ(1, 18 + gpio - 16);
133 static inline int au1550_gpio2_to_irq(int gpio)
135 gpio -= ALCHEMY_GPIO2_BASE;
138 case 0: return MAKE_IRQ(1, 16);
139 case 1 ... 5: return MAKE_IRQ(1, 17); /* shared GPIO201_205 */
140 case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6);
141 case 8 ... 15: return MAKE_IRQ(1, 31); /* shared GPIO208_215 */
147 static inline int au1550_irq_to_gpio(int irq)
150 case AU1550_GPIO0_INT ... AU1550_GPIO15_INT:
151 return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO0_INT) + 0;
152 case AU1550_GPIO200_INT:
153 case AU1550_GPIO201_205_INT:
154 return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO200_INT) + 0;
155 case AU1550_GPIO16_INT ... AU1550_GPIO28_INT:
156 return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO16_INT) + 16;
157 case AU1550_GPIO206_INT ... AU1550_GPIO208_215_INT:
158 return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO206_INT) + 6;
164 static inline int au1200_gpio1_to_irq(int gpio)
166 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
169 static inline int au1200_gpio2_to_irq(int gpio)
171 gpio -= ALCHEMY_GPIO2_BASE;
174 case 0 ... 2: return MAKE_IRQ(0, 5 + gpio - 0);
175 case 3: return MAKE_IRQ(0, 22);
176 case 4 ... 7: return MAKE_IRQ(0, 24 + gpio - 4);
177 case 8 ... 15: return MAKE_IRQ(0, 28); /* shared GPIO208_215 */
183 static inline int au1200_irq_to_gpio(int irq)
186 case AU1200_GPIO0_INT ... AU1200_GPIO31_INT:
187 return ALCHEMY_GPIO1_BASE + (irq - AU1200_GPIO0_INT) + 0;
188 case AU1200_GPIO200_INT ... AU1200_GPIO202_INT:
189 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO200_INT) + 0;
190 case AU1200_GPIO203_INT:
191 return ALCHEMY_GPIO2_BASE + 3;
192 case AU1200_GPIO204_INT ... AU1200_GPIO208_215_INT:
193 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO204_INT) + 4;
200 * GPIO1 block macros for common linux gpio functions.
202 static inline void alchemy_gpio1_set_value(int gpio, int v)
204 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
205 unsigned long r = v ? SYS_OUTPUTSET : SYS_OUTPUTCLR;
210 static inline int alchemy_gpio1_get_value(int gpio)
212 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
213 return au_readl(SYS_PINSTATERD) & mask;
216 static inline int alchemy_gpio1_direction_input(int gpio)
218 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
219 au_writel(mask, SYS_TRIOUTCLR);
224 static inline int alchemy_gpio1_direction_output(int gpio, int v)
226 /* hardware switches to "output" mode when one of the two
227 * "set_value" registers is accessed.
229 alchemy_gpio1_set_value(gpio, v);
233 static inline int alchemy_gpio1_is_valid(int gpio)
235 return ((gpio >= ALCHEMY_GPIO1_BASE) && (gpio <= ALCHEMY_GPIO1_MAX));
238 static inline int alchemy_gpio1_to_irq(int gpio)
240 switch (alchemy_get_cputype()) {
241 case ALCHEMY_CPU_AU1000:
242 return au1000_gpio1_to_irq(gpio);
243 case ALCHEMY_CPU_AU1100:
244 return au1100_gpio1_to_irq(gpio);
245 case ALCHEMY_CPU_AU1500:
246 return au1500_gpio1_to_irq(gpio);
247 case ALCHEMY_CPU_AU1550:
248 return au1550_gpio1_to_irq(gpio);
249 case ALCHEMY_CPU_AU1200:
250 return au1200_gpio1_to_irq(gpio);
256 * GPIO2 block macros for common linux GPIO functions. The 'gpio'
257 * parameter must be in range of ALCHEMY_GPIO2_BASE..ALCHEMY_GPIO2_MAX.
259 static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out)
261 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE);
262 unsigned long d = au_readl(GPIO2_DIR);
267 au_writel(d, GPIO2_DIR);
271 static inline void alchemy_gpio2_set_value(int gpio, int v)
274 mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE);
275 au_writel(mask, GPIO2_OUTPUT);
279 static inline int alchemy_gpio2_get_value(int gpio)
281 return au_readl(GPIO2_PINSTATE) & (1 << (gpio - ALCHEMY_GPIO2_BASE));
284 static inline int alchemy_gpio2_direction_input(int gpio)
287 local_irq_save(flags);
288 __alchemy_gpio2_mod_dir(gpio, 0);
289 local_irq_restore(flags);
293 static inline int alchemy_gpio2_direction_output(int gpio, int v)
296 alchemy_gpio2_set_value(gpio, v);
297 local_irq_save(flags);
298 __alchemy_gpio2_mod_dir(gpio, 1);
299 local_irq_restore(flags);
303 static inline int alchemy_gpio2_is_valid(int gpio)
305 return ((gpio >= ALCHEMY_GPIO2_BASE) && (gpio <= ALCHEMY_GPIO2_MAX));
308 static inline int alchemy_gpio2_to_irq(int gpio)
310 switch (alchemy_get_cputype()) {
311 case ALCHEMY_CPU_AU1000:
312 return au1000_gpio2_to_irq(gpio);
313 case ALCHEMY_CPU_AU1100:
314 return au1100_gpio2_to_irq(gpio);
315 case ALCHEMY_CPU_AU1500:
316 return au1500_gpio2_to_irq(gpio);
317 case ALCHEMY_CPU_AU1550:
318 return au1550_gpio2_to_irq(gpio);
319 case ALCHEMY_CPU_AU1200:
320 return au1200_gpio2_to_irq(gpio);
325 /**********************************************************************/
327 /* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
328 * SYS_PININPUTEN is written to at least once. On Au1550/Au1200 this
329 * register enables use of GPIOs as wake source.
331 static inline void alchemy_gpio1_input_enable(void)
333 au_writel(0, SYS_PININPUTEN); /* the write op is key */
337 /* GPIO2 shared interrupts and control */
339 static inline void __alchemy_gpio2_mod_int(int gpio2, int en)
341 unsigned long r = au_readl(GPIO2_INTENABLE);
346 au_writel(r, GPIO2_INTENABLE);
351 * alchemy_gpio2_enable_int - Enable a GPIO2 pins' shared irq contribution.
352 * @gpio2: The GPIO2 pin to activate (200...215).
354 * GPIO208-215 have one shared interrupt line to the INTC. They are
355 * and'ed with a per-pin enable bit and finally or'ed together to form
356 * a single irq request (useful for active-high sources).
357 * With this function, a pins' individual contribution to the int request
358 * can be enabled. As with all other GPIO-based interrupts, the INTC
359 * must be programmed to accept the GPIO208_215 interrupt as well.
361 * NOTE: Calling this macro is only necessary for GPIO208-215; all other
362 * GPIO2-based interrupts have their own request to the INTC. Please
363 * consult your Alchemy databook for more information!
365 * NOTE: On the Au1550, GPIOs 201-205 also have a shared interrupt request
366 * line to the INTC, GPIO201_205. This function can be used for those
369 * NOTE: 'gpio2' parameter must be in range of the GPIO2 numberspace
370 * (200-215 by default). No sanity checks are made,
372 static inline void alchemy_gpio2_enable_int(int gpio2)
376 gpio2 -= ALCHEMY_GPIO2_BASE;
378 /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
379 switch (alchemy_get_cputype()) {
380 case ALCHEMY_CPU_AU1100:
381 case ALCHEMY_CPU_AU1500:
385 local_irq_save(flags);
386 __alchemy_gpio2_mod_int(gpio2, 1);
387 local_irq_restore(flags);
391 * alchemy_gpio2_disable_int - Disable a GPIO2 pins' shared irq contribution.
392 * @gpio2: The GPIO2 pin to activate (200...215).
394 * see function alchemy_gpio2_enable_int() for more information.
396 static inline void alchemy_gpio2_disable_int(int gpio2)
400 gpio2 -= ALCHEMY_GPIO2_BASE;
402 /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
403 switch (alchemy_get_cputype()) {
404 case ALCHEMY_CPU_AU1100:
405 case ALCHEMY_CPU_AU1500:
409 local_irq_save(flags);
410 __alchemy_gpio2_mod_int(gpio2, 0);
411 local_irq_restore(flags);
415 * alchemy_gpio2_enable - Activate GPIO2 block.
417 * The GPIO2 block must be enabled excplicitly to work. On systems
418 * where this isn't done by the bootloader, this macro can be used.
420 static inline void alchemy_gpio2_enable(void)
422 au_writel(3, GPIO2_ENABLE); /* reset, clock enabled */
424 au_writel(1, GPIO2_ENABLE); /* clock enabled */
429 * alchemy_gpio2_disable - disable GPIO2 block.
431 * Disable and put GPIO2 block in low-power mode.
433 static inline void alchemy_gpio2_disable(void)
435 au_writel(2, GPIO2_ENABLE); /* reset, clock disabled */
439 /**********************************************************************/
441 /* wrappers for on-chip gpios; can be used before gpio chips have been
442 * registered with gpiolib.
444 static inline int alchemy_gpio_direction_input(int gpio)
446 return (gpio >= ALCHEMY_GPIO2_BASE) ?
447 alchemy_gpio2_direction_input(gpio) :
448 alchemy_gpio1_direction_input(gpio);
451 static inline int alchemy_gpio_direction_output(int gpio, int v)
453 return (gpio >= ALCHEMY_GPIO2_BASE) ?
454 alchemy_gpio2_direction_output(gpio, v) :
455 alchemy_gpio1_direction_output(gpio, v);
458 static inline int alchemy_gpio_get_value(int gpio)
460 return (gpio >= ALCHEMY_GPIO2_BASE) ?
461 alchemy_gpio2_get_value(gpio) :
462 alchemy_gpio1_get_value(gpio);
465 static inline void alchemy_gpio_set_value(int gpio, int v)
467 if (gpio >= ALCHEMY_GPIO2_BASE)
468 alchemy_gpio2_set_value(gpio, v);
470 alchemy_gpio1_set_value(gpio, v);
473 static inline int alchemy_gpio_is_valid(int gpio)
475 return (gpio >= ALCHEMY_GPIO2_BASE) ?
476 alchemy_gpio2_is_valid(gpio) :
477 alchemy_gpio1_is_valid(gpio);
480 static inline int alchemy_gpio_cansleep(int gpio)
482 return 0; /* Alchemy never gets tired */
485 static inline int alchemy_gpio_to_irq(int gpio)
487 return (gpio >= ALCHEMY_GPIO2_BASE) ?
488 alchemy_gpio2_to_irq(gpio) :
489 alchemy_gpio1_to_irq(gpio);
492 static inline int alchemy_irq_to_gpio(int irq)
494 switch (alchemy_get_cputype()) {
495 case ALCHEMY_CPU_AU1000:
496 return au1000_irq_to_gpio(irq);
497 case ALCHEMY_CPU_AU1100:
498 return au1100_irq_to_gpio(irq);
499 case ALCHEMY_CPU_AU1500:
500 return au1500_irq_to_gpio(irq);
501 case ALCHEMY_CPU_AU1550:
502 return au1550_irq_to_gpio(irq);
503 case ALCHEMY_CPU_AU1200:
504 return au1200_irq_to_gpio(irq);
509 /**********************************************************************/
511 /* Linux gpio framework integration.
513 * 4 use cases of Au1000-Au1200 GPIOS:
514 *(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
515 * Board must register gpiochips.
516 *(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
517 * 2 (1 for Au1000) gpio_chips are registered.
519 *(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
520 * the boards' gpio.h must provide the linux gpio wrapper functions,
522 *(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
523 * inlinable gpio functions are provided which enable access to the
524 * Au1000 gpios only by using the numbers straight out of the data-
527 * Cases 1 and 3 are intended for boards which want to provide their own
528 * GPIO namespace and -operations (i.e. for example you have 8 GPIOs
529 * which are in part provided by spare Au1000 GPIO pins and in part by
530 * an external FPGA but you still want them to be accssible in linux
531 * as gpio0-7. The board can of course use the alchemy_gpioX_* functions
535 #ifndef CONFIG_GPIOLIB
538 #ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */
540 static inline int gpio_direction_input(int gpio)
542 return alchemy_gpio_direction_input(gpio);
545 static inline int gpio_direction_output(int gpio, int v)
547 return alchemy_gpio_direction_output(gpio, v);
550 static inline int gpio_get_value(int gpio)
552 return alchemy_gpio_get_value(gpio);
555 static inline void gpio_set_value(int gpio, int v)
557 alchemy_gpio_set_value(gpio, v);
560 static inline int gpio_get_value_cansleep(unsigned gpio)
562 return gpio_get_value(gpio);
565 static inline void gpio_set_value_cansleep(unsigned gpio, int value)
567 gpio_set_value(gpio, value);
570 static inline int gpio_is_valid(int gpio)
572 return alchemy_gpio_is_valid(gpio);
575 static inline int gpio_cansleep(int gpio)
577 return alchemy_gpio_cansleep(gpio);
580 static inline int gpio_to_irq(int gpio)
582 return alchemy_gpio_to_irq(gpio);
585 static inline int irq_to_gpio(int irq)
587 return alchemy_irq_to_gpio(irq);
590 static inline int gpio_request(unsigned gpio, const char *label)
595 static inline int gpio_request_one(unsigned gpio,
596 unsigned long flags, const char *label)
601 static inline int gpio_request_array(struct gpio *array, size_t num)
606 static inline void gpio_free(unsigned gpio)
610 static inline void gpio_free_array(struct gpio *array, size_t num)
614 static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
619 static inline int gpio_export(unsigned gpio, bool direction_may_change)
624 static inline int gpio_export_link(struct device *dev, const char *name,
630 static inline int gpio_sysfs_set_active_low(unsigned gpio, int value)
635 static inline void gpio_unexport(unsigned gpio)
639 #endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
642 #else /* CONFIG GPIOLIB */
645 /* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */
646 #ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (2) */
648 /* get everything through gpiolib */
649 #define gpio_to_irq __gpio_to_irq
650 #define gpio_get_value __gpio_get_value
651 #define gpio_set_value __gpio_set_value
652 #define gpio_cansleep __gpio_cansleep
653 #define irq_to_gpio alchemy_irq_to_gpio
655 #include <asm-generic/gpio.h>
657 #endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
660 #endif /* !CONFIG_GPIOLIB */
662 #endif /* _ALCHEMY_GPIO_AU1000_H_ */