2 * AMD Alchemy Semi PB1550 Referrence Board
3 * Board Registers defines.
5 * Copyright 2004 Embedded Edge LLC.
6 * Copyright 2005 Ralf Baechle (ralf@linux-mips.org)
8 * ########################################################################
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
23 * ########################################################################
27 #ifndef __ASM_PB1550_H
28 #define __ASM_PB1550_H
30 #include <linux/types.h>
31 #include <asm/mach-au1x00/au1xxx_psc.h>
33 #define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
34 #define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
35 #define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
36 #define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
38 #define SPI_PSC_BASE PSC0_BASE_ADDR
39 #define AC97_PSC_BASE PSC1_BASE_ADDR
40 #define SMBUS_PSC_BASE PSC2_BASE_ADDR
41 #define I2S_PSC_BASE PSC3_BASE_ADDR
43 #define PCMCIA_MAX_SOCK 1
44 #define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
47 #define SET_VCC_VPP(VCC, VPP, SLOT) \
48 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
50 #if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
51 #define PB1550_BOTH_BANKS
52 #elif defined(CONFIG_MTD_PB1550_BOOT) && !defined(CONFIG_MTD_PB1550_USER)
53 #define PB1550_BOOT_ONLY
54 #elif !defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
55 #define PB1550_USER_ONLY
59 * Timing values as described in databook, * ns value stripped of
61 * These defines are here rather than an SOC1550 generic file because
62 * the parts chosen on another board may be different and may require
65 #define NAND_T_H (18 >> 2)
66 #define NAND_T_PUL (30 >> 2)
67 #define NAND_T_SU (30 >> 2)
68 #define NAND_T_WH (30 >> 2)
70 /* Bitfield shift amounts */
71 #define NAND_T_H_SHIFT 0
72 #define NAND_T_PUL_SHIFT 4
73 #define NAND_T_SU_SHIFT 8
74 #define NAND_T_WH_SHIFT 12
76 #define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
77 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
78 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
79 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
83 /* Should be done by YAMON */
84 #define NAND_STCFG 0x00400005 /* 8-bit NAND */
85 #define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
86 #define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
88 #endif /* __ASM_PB1550_H */