2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved.
7 * Douglas Leung <douglas@mips.com>
8 * Steven J. Hill <sjhill@mips.com>
10 #ifndef _MIPS_SEAD3INT_H
11 #define _MIPS_SEAD3INT_H
13 #include <linux/irqchip/mips-gic.h>
15 /* CPU interrupt offsets */
16 #define CPU_INT_EHCI 2
19 /* GIC interrupt offsets */
20 #define GIC_INT_NET GIC_SHARED_TO_HWIRQ(0)
21 #define GIC_INT_EHCI GIC_SHARED_TO_HWIRQ(5)
23 #endif /* !(_MIPS_SEAD3INT_H) */