arch/mips/include/asm/mipsregs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   7  * Copyright (C) 2000 Silicon Graphics, Inc.
   8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
  11  * Copyright (C) 2003, 2004  Maciej W. Rozycki
  12  */
  13 #ifndef _ASM_MIPSREGS_H
  14 #define _ASM_MIPSREGS_H
  15
  16 #include <linux/linkage.h>
  17 #include <asm/hazards.h>
  18 #include <asm/war.h>
  19
  20 /*
  21  * The following macros are especially useful for __asm__
  22  * inline assembler.
  23  */
  24 #ifndef __STR
  25 #define __STR(x) #x
  26 #endif
  27 #ifndef STR
  28 #define STR(x) __STR(x)
  29 #endif
  30
  31 /*
  32  *  Configure language
  33  */
  34 #ifdef __ASSEMBLY__
  35 #define _ULCAST_
  36 #else
  37 #define _ULCAST_ (unsigned long)
  38 #endif
  39
  40 /*
  41  * Coprocessor 0 register names
  42  */
  43 #define CP0_INDEX $0
  44 #define CP0_RANDOM $1
  45 #define CP0_ENTRYLO0 $2
  46 #define CP0_ENTRYLO1 $3
  47 #define CP0_CONF $3
  48 #define CP0_CONTEXT $4
  49 #define CP0_PAGEMASK $5
  50 #define CP0_WIRED $6
  51 #define CP0_INFO $7
  52 #define CP0_BADVADDR $8
  53 #define CP0_COUNT $9
  54 #define CP0_ENTRYHI $10
  55 #define CP0_COMPARE $11
  56 #define CP0_STATUS $12
  57 #define CP0_CAUSE $13
  58 #define CP0_EPC $14
  59 #define CP0_PRID $15
  60 #define CP0_CONFIG $16
  61 #define CP0_LLADDR $17
  62 #define CP0_WATCHLO $18
  63 #define CP0_WATCHHI $19
  64 #define CP0_XCONTEXT $20
  65 #define CP0_FRAMEMASK $21
  66 #define CP0_DIAGNOSTIC $22
  67 #define CP0_DEBUG $23
  68 #define CP0_DEPC $24
  69 #define CP0_PERFORMANCE $25
  70 #define CP0_ECC $26
  71 #define CP0_CACHEERR $27
  72 #define CP0_TAGLO $28
  73 #define CP0_TAGHI $29
  74 #define CP0_ERROREPC $30
  75 #define CP0_DESAVE $31
  76
  77 /*
  78  * R4640/R4650 cp0 register names.  These registers are listed
  79  * here only for completeness; without MMU these CPUs are not useable
  80  * by Linux.  A future ELKS port might take make Linux run on them
  81  * though ...
  82  */
  83 #define CP0_IBASE $0
  84 #define CP0_IBOUND $1
  85 #define CP0_DBASE $2
  86 #define CP0_DBOUND $3
  87 #define CP0_CALG $17
  88 #define CP0_IWATCH $18
  89 #define CP0_DWATCH $19
  90
  91 /*
  92  * Coprocessor 0 Set 1 register names
  93  */
  94 #define CP0_S1_DERRADDR0  $26
  95 #define CP0_S1_DERRADDR1  $27
  96 #define CP0_S1_INTCONTROL $20
  97
  98 /*
  99  * Coprocessor 0 Set 2 register names
 100  */
 101 #define CP0_S2_SRSCTL     $12   /* MIPSR2 */
 102
 103 /*
 104  * Coprocessor 0 Set 3 register names
 105  */
 106 #define CP0_S3_SRSMAP     $12   /* MIPSR2 */
 107
 108 /*
 109  *  TX39 Series
 110  */
 111 #define CP0_TX39_CACHE  $7
 112
 113 /*
 114  * Coprocessor 1 (FPU) register names
 115  */
 116 #define CP1_REVISION   $0
 117 #define CP1_STATUS     $31
 118
 119 /*
 120  * FPU Status Register Values
 121  */
 122 /*
 123  * Status Register Values
 124  */
 125
 126 #define FPU_CSR_FLUSH   0x01000000      /* flush denormalised results to 0 */
 127 #define FPU_CSR_COND    0x00800000      /* $fcc0 */
 128 #define FPU_CSR_COND0   0x00800000      /* $fcc0 */
 129 #define FPU_CSR_COND1   0x02000000      /* $fcc1 */
 130 #define FPU_CSR_COND2   0x04000000      /* $fcc2 */
 131 #define FPU_CSR_COND3   0x08000000      /* $fcc3 */
 132 #define FPU_CSR_COND4   0x10000000      /* $fcc4 */
 133 #define FPU_CSR_COND5   0x20000000      /* $fcc5 */
 134 #define FPU_CSR_COND6   0x40000000      /* $fcc6 */
 135 #define FPU_CSR_COND7   0x80000000      /* $fcc7 */
 136
 137 /*
 138  * Bits 18 - 20 of the FPU Status Register will be read as 0,
 139  * and should be written as zero.
 140  */
 141 #define FPU_CSR_RSVD    0x001c0000
 142
 143 /*
 144  * X the exception cause indicator
 145  * E the exception enable
 146  * S the sticky/flag bit
 147 */
 148 #define FPU_CSR_ALL_X   0x0003f000
 149 #define FPU_CSR_UNI_X   0x00020000
 150 #define FPU_CSR_INV_X   0x00010000
 151 #define FPU_CSR_DIV_X   0x00008000
 152 #define FPU_CSR_OVF_X   0x00004000
 153 #define FPU_CSR_UDF_X   0x00002000
 154 #define FPU_CSR_INE_X   0x00001000
 155
 156 #define FPU_CSR_ALL_E   0x00000f80
 157 #define FPU_CSR_INV_E   0x00000800
 158 #define FPU_CSR_DIV_E   0x00000400
 159 #define FPU_CSR_OVF_E   0x00000200
 160 #define FPU_CSR_UDF_E   0x00000100
 161 #define FPU_CSR_INE_E   0x00000080
 162
 163 #define FPU_CSR_ALL_S   0x0000007c
 164 #define FPU_CSR_INV_S   0x00000040
 165 #define FPU_CSR_DIV_S   0x00000020
 166 #define FPU_CSR_OVF_S   0x00000010
 167 #define FPU_CSR_UDF_S   0x00000008
 168 #define FPU_CSR_INE_S   0x00000004
 169
 170 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
 171 #define FPU_CSR_RM      0x00000003
 172 #define FPU_CSR_RN      0x0     /* nearest */
 173 #define FPU_CSR_RZ      0x1     /* towards zero */
 174 #define FPU_CSR_RU      0x2     /* towards +Infinity */
 175 #define FPU_CSR_RD      0x3     /* towards -Infinity */
 176
 177
 178 /*
 179  * Values for PageMask register
 180  */
 181 #ifdef CONFIG_CPU_VR41XX
 182
 183 /* Why doesn't stupidity hurt ... */
 184
 185 #define PM_1K           0x00000000
 186 #define PM_4K           0x00001800
 187 #define PM_16K          0x00007800
 188 #define PM_64K          0x0001f800
 189 #define PM_256K         0x0007f800
 190
 191 #else
 192
 193 #define PM_4K           0x00000000
 194 #define PM_8K           0x00002000
 195 #define PM_16K          0x00006000
 196 #define PM_32K          0x0000e000
 197 #define PM_64K          0x0001e000
 198 #define PM_128K         0x0003e000
 199 #define PM_256K         0x0007e000
 200 #define PM_512K         0x000fe000
 201 #define PM_1M           0x001fe000
 202 #define PM_2M           0x003fe000
 203 #define PM_4M           0x007fe000
 204 #define PM_8M           0x00ffe000
 205 #define PM_16M          0x01ffe000
 206 #define PM_32M          0x03ffe000
 207 #define PM_64M          0x07ffe000
 208 #define PM_256M         0x1fffe000
 209 #define PM_1G           0x7fffe000
 210
 211 #endif
 212
 213 /*
 214  * Default page size for a given kernel configuration
 215  */
 216 #ifdef CONFIG_PAGE_SIZE_4KB
 217 #define PM_DEFAULT_MASK PM_4K
 218 #elif defined(CONFIG_PAGE_SIZE_8KB)
 219 #define PM_DEFAULT_MASK PM_8K
 220 #elif defined(CONFIG_PAGE_SIZE_16KB)
 221 #define PM_DEFAULT_MASK PM_16K
 222 #elif defined(CONFIG_PAGE_SIZE_32KB)
 223 #define PM_DEFAULT_MASK PM_32K
 224 #elif defined(CONFIG_PAGE_SIZE_64KB)
 225 #define PM_DEFAULT_MASK PM_64K
 226 #else
 227 #error Bad page size configuration!
 228 #endif
 229
 230 /*
 231  * Default huge tlb size for a given kernel configuration
 232  */
 233 #ifdef CONFIG_PAGE_SIZE_4KB
 234 #define PM_HUGE_MASK    PM_1M
 235 #elif defined(CONFIG_PAGE_SIZE_8KB)
 236 #define PM_HUGE_MASK    PM_4M
 237 #elif defined(CONFIG_PAGE_SIZE_16KB)
 238 #define PM_HUGE_MASK    PM_16M
 239 #elif defined(CONFIG_PAGE_SIZE_32KB)
 240 #define PM_HUGE_MASK    PM_64M
 241 #elif defined(CONFIG_PAGE_SIZE_64KB)
 242 #define PM_HUGE_MASK    PM_256M
 243 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
 244 #error Bad page size configuration for hugetlbfs!
 245 #endif
 246
 247 /*
 248  * Values used for computation of new tlb entries
 249  */
 250 #define PL_4K           12
 251 #define PL_16K          14
 252 #define PL_64K          16
 253 #define PL_256K         18
 254 #define PL_1M           20
 255 #define PL_4M           22
 256 #define PL_16M          24
 257 #define PL_64M          26
 258 #define PL_256M         28
 259
 260 /*
 261  * PageGrain bits
 262  */
 263 #define PG_RIE          (_ULCAST_(1) <<  31)
 264 #define PG_XIE          (_ULCAST_(1) <<  30)
 265 #define PG_ELPA         (_ULCAST_(1) <<  29)
 266 #define PG_ESP          (_ULCAST_(1) <<  28)
 267
 268 /*
 269  * R4x00 interrupt enable / cause bits
 270  */
 271 #define IE_SW0          (_ULCAST_(1) <<  8)
 272 #define IE_SW1          (_ULCAST_(1) <<  9)
 273 #define IE_IRQ0         (_ULCAST_(1) << 10)
 274 #define IE_IRQ1         (_ULCAST_(1) << 11)
 275 #define IE_IRQ2         (_ULCAST_(1) << 12)
 276 #define IE_IRQ3         (_ULCAST_(1) << 13)
 277 #define IE_IRQ4         (_ULCAST_(1) << 14)
 278 #define IE_IRQ5         (_ULCAST_(1) << 15)
 279
 280 /*
 281  * R4x00 interrupt cause bits
 282  */
 283 #define C_SW0           (_ULCAST_(1) <<  8)
 284 #define C_SW1           (_ULCAST_(1) <<  9)
 285 #define C_IRQ0          (_ULCAST_(1) << 10)
 286 #define C_IRQ1          (_ULCAST_(1) << 11)
 287 #define C_IRQ2          (_ULCAST_(1) << 12)
 288 #define C_IRQ3          (_ULCAST_(1) << 13)
 289 #define C_IRQ4          (_ULCAST_(1) << 14)
 290 #define C_IRQ5          (_ULCAST_(1) << 15)
 291
 292 /*
 293  * Bitfields in the R4xx0 cp0 status register
 294  */
 295 #define ST0_IE                  0x00000001
 296 #define ST0_EXL                 0x00000002
 297 #define ST0_ERL                 0x00000004
 298 #define ST0_KSU                 0x00000018
 299 #  define KSU_USER              0x00000010
 300 #  define KSU_SUPERVISOR        0x00000008
 301 #  define KSU_KERNEL            0x00000000
 302 #define ST0_UX                  0x00000020
 303 #define ST0_SX                  0x00000040
 304 #define ST0_KX                  0x00000080
 305 #define ST0_DE                  0x00010000
 306 #define ST0_CE                  0x00020000
 307
 308 /*
 309  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
 310  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
 311  * processors.
 312  */
 313 #define ST0_CO                  0x08000000
 314
 315 /*
 316  * Bitfields in the R[23]000 cp0 status register.
 317  */
 318 #define ST0_IEC                 0x00000001
 319 #define ST0_KUC                 0x00000002
 320 #define ST0_IEP                 0x00000004
 321 #define ST0_KUP                 0x00000008
 322 #define ST0_IEO                 0x00000010
 323 #define ST0_KUO                 0x00000020
 324 /* bits 6 & 7 are reserved on R[23]000 */
 325 #define ST0_ISC                 0x00010000
 326 #define ST0_SWC                 0x00020000
 327 #define ST0_CM                  0x00080000
 328
 329 /*
 330  * Bits specific to the R4640/R4650
 331  */
 332 #define ST0_UM                  (_ULCAST_(1) <<  4)
 333 #define ST0_IL                  (_ULCAST_(1) << 23)
 334 #define ST0_DL                  (_ULCAST_(1) << 24)
 335
 336 /*
 337  * Enable the MIPS MDMX and DSP ASEs
 338  */
 339 #define ST0_MX                  0x01000000
 340
 341 /*
 342  * Bitfields in the TX39 family CP0 Configuration Register 3
 343  */
 344 #define TX39_CONF_ICS_SHIFT     19
 345 #define TX39_CONF_ICS_MASK      0x00380000
 346 #define TX39_CONF_ICS_1KB       0x00000000
 347 #define TX39_CONF_ICS_2KB       0x00080000
 348 #define TX39_CONF_ICS_4KB       0x00100000
 349 #define TX39_CONF_ICS_8KB       0x00180000
 350 #define TX39_CONF_ICS_16KB      0x00200000
 351
 352 #define TX39_CONF_DCS_SHIFT     16
 353 #define TX39_CONF_DCS_MASK      0x00070000
 354 #define TX39_CONF_DCS_1KB       0x00000000
 355 #define TX39_CONF_DCS_2KB       0x00010000
 356 #define TX39_CONF_DCS_4KB       0x00020000
 357 #define TX39_CONF_DCS_8KB       0x00030000
 358 #define TX39_CONF_DCS_16KB      0x00040000
 359
 360 #define TX39_CONF_CWFON         0x00004000
 361 #define TX39_CONF_WBON          0x00002000
 362 #define TX39_CONF_RF_SHIFT      10
 363 #define TX39_CONF_RF_MASK       0x00000c00
 364 #define TX39_CONF_DOZE          0x00000200
 365 #define TX39_CONF_HALT          0x00000100
 366 #define TX39_CONF_LOCK          0x00000080
 367 #define TX39_CONF_ICE           0x00000020
 368 #define TX39_CONF_DCE           0x00000010
 369 #define TX39_CONF_IRSIZE_SHIFT  2
 370 #define TX39_CONF_IRSIZE_MASK   0x0000000c
 371 #define TX39_CONF_DRSIZE_SHIFT  0
 372 #define TX39_CONF_DRSIZE_MASK   0x00000003
 373
 374 /*
 375  * Status register bits available in all MIPS CPUs.
 376  */
 377 #define ST0_IM                  0x0000ff00
 378 #define  STATUSB_IP0            8
 379 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
 380 #define  STATUSB_IP1            9
 381 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
 382 #define  STATUSB_IP2            10
 383 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
 384 #define  STATUSB_IP3            11
 385 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
 386 #define  STATUSB_IP4            12
 387 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
 388 #define  STATUSB_IP5            13
 389 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
 390 #define  STATUSB_IP6            14
 391 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
 392 #define  STATUSB_IP7            15
 393 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
 394 #define  STATUSB_IP8            0
 395 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
 396 #define  STATUSB_IP9            1
 397 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
 398 #define  STATUSB_IP10           2
 399 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
 400 #define  STATUSB_IP11           3
 401 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
 402 #define  STATUSB_IP12           4
 403 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
 404 #define  STATUSB_IP13           5
 405 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
 406 #define  STATUSB_IP14           6
 407 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
 408 #define  STATUSB_IP15           7
 409 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
 410 #define ST0_CH                  0x00040000
 411 #define ST0_NMI                 0x00080000
 412 #define ST0_SR                  0x00100000
 413 #define ST0_TS                  0x00200000
 414 #define ST0_BEV                 0x00400000
 415 #define ST0_RE                  0x02000000
 416 #define ST0_FR                  0x04000000
 417 #define ST0_CU                  0xf0000000
 418 #define ST0_CU0                 0x10000000
 419 #define ST0_CU1                 0x20000000
 420 #define ST0_CU2                 0x40000000
 421 #define ST0_CU3                 0x80000000
 422 #define ST0_XX                  0x80000000      /* MIPS IV naming */
 423
 424 /*
 425  * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
 426  *
 427  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 428  */
 429 #define INTCTLB_IPPCI           26
 430 #define INTCTLF_IPPCI           (_ULCAST_(7) << INTCTLB_IPPCI)
 431 #define INTCTLB_IPTI            29
 432 #define INTCTLF_IPTI            (_ULCAST_(7) << INTCTLB_IPTI)
 433
 434 /*
 435  * Bitfields and bit numbers in the coprocessor 0 cause register.
 436  *
 437  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 438  */
 439 #define  CAUSEB_EXCCODE         2
 440 #define  CAUSEF_EXCCODE         (_ULCAST_(31)  <<  2)
 441 #define  CAUSEB_IP              8
 442 #define  CAUSEF_IP              (_ULCAST_(255) <<  8)
 443 #define  CAUSEB_IP0             8
 444 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
 445 #define  CAUSEB_IP1             9
 446 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
 447 #define  CAUSEB_IP2             10
 448 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
 449 #define  CAUSEB_IP3             11
 450 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
 451 #define  CAUSEB_IP4             12
 452 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
 453 #define  CAUSEB_IP5             13
 454 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
 455 #define  CAUSEB_IP6             14
 456 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
 457 #define  CAUSEB_IP7             15
 458 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
 459 #define  CAUSEB_IV              23
 460 #define  CAUSEF_IV              (_ULCAST_(1)   << 23)
 461 #define  CAUSEB_PCI             26
 462 #define  CAUSEF_PCI             (_ULCAST_(1)   << 26)
 463 #define  CAUSEB_CE              28
 464 #define  CAUSEF_CE              (_ULCAST_(3)   << 28)
 465 #define  CAUSEB_TI              30
 466 #define  CAUSEF_TI              (_ULCAST_(1)   << 30)
 467 #define  CAUSEB_BD              31
 468 #define  CAUSEF_BD              (_ULCAST_(1)   << 31)
 469
 470 /*
 471  * Bits in the coprocessor 0 config register.
 472  */
 473 /* Generic bits.  */
 474 #define CONF_CM_CACHABLE_NO_WA          0
 475 #define CONF_CM_CACHABLE_WA             1
 476 #define CONF_CM_UNCACHED                2
 477 #define CONF_CM_CACHABLE_NONCOHERENT    3
 478 #define CONF_CM_CACHABLE_CE             4
 479 #define CONF_CM_CACHABLE_COW            5
 480 #define CONF_CM_CACHABLE_CUW            6
 481 #define CONF_CM_CACHABLE_ACCELERATED    7
 482 #define CONF_CM_CMASK                   7
 483 #define CONF_BE                 (_ULCAST_(1) << 15)
 484
 485 /* Bits common to various processors.  */
 486 #define CONF_CU                 (_ULCAST_(1) <<  3)
 487 #define CONF_DB                 (_ULCAST_(1) <<  4)
 488 #define CONF_IB                 (_ULCAST_(1) <<  5)
 489 #define CONF_DC                 (_ULCAST_(7) <<  6)
 490 #define CONF_IC                 (_ULCAST_(7) <<  9)
 491 #define CONF_EB                 (_ULCAST_(1) << 13)
 492 #define CONF_EM                 (_ULCAST_(1) << 14)
 493 #define CONF_SM                 (_ULCAST_(1) << 16)
 494 #define CONF_SC                 (_ULCAST_(1) << 17)
 495 #define CONF_EW                 (_ULCAST_(3) << 18)
 496 #define CONF_EP                 (_ULCAST_(15)<< 24)
 497 #define CONF_EC                 (_ULCAST_(7) << 28)
 498 #define CONF_CM                 (_ULCAST_(1) << 31)
 499
 500 /* Bits specific to the R4xx0.  */
 501 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
 502 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
 503 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
 504
 505 /* Bits specific to the R5000.  */
 506 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
 507 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
 508
 509 /* Bits specific to the RM7000.  */
 510 #define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
 511 #define RM7K_CONF_TE            (_ULCAST_(1) << 12)
 512 #define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
 513 #define RM7K_CONF_TC            (_ULCAST_(1) << 17)
 514 #define RM7K_CONF_SI            (_ULCAST_(3) << 20)
 515 #define RM7K_CONF_SC            (_ULCAST_(1) << 31)
 516
 517 /* Bits specific to the R10000.  */
 518 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
 519 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
 520 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
 521 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
 522 #define R10K_CONF_EC            (_ULCAST_(15)<<  9)
 523 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
 524 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
 525 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
 526 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
 527 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
 528 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
 529
 530 /* Bits specific to the VR41xx.  */
 531 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
 532 #define VR41_CONF_P4K           (_ULCAST_(1) << 13)
 533 #define VR41_CONF_BP            (_ULCAST_(1) << 16)
 534 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
 535 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
 536
 537 /* Bits specific to the R30xx.  */
 538 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
 539 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
 540 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
 541 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
 542 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
 543 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
 544 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
 545 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
 546 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
 547
 548 /* Bits specific to the TX49.  */
 549 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
 550 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
 551 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
 552 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
 553
 554 /* Bits specific to the MIPS32/64 PRA.  */
 555 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
 556 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
 557 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
 558 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
 559
 560 /*
 561  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
 562  */
 563 #define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
 564 #define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
 565 #define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
 566 #define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
 567 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
 568 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
 569 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
 570 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
 571 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
 572 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
 573 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
 574 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
 575 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
 576 #define MIPS_CONF1_TLBS         (_ULCAST_(63)<< 25)
 577
 578 #define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
 579 #define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
 580 #define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
 581 #define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
 582 #define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
 583 #define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
 584 #define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
 585 #define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
 586
 587 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
 588 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
 589 #define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
 590 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
 591 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
 592 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 593 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
 594 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
 595 #define MIPS_CONF3_DSP2P        (_ULCAST_(1) << 11)
 596 #define MIPS_CONF3_RXI          (_ULCAST_(1) << 12)
 597 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 598 #define MIPS_CONF3_ISA          (_ULCAST_(3) << 14)
 599 #define MIPS_CONF3_ISA_OE       (_ULCAST_(1) << 16)
 600 #define MIPS_CONF3_VZ           (_ULCAST_(1) << 23)
 601
 602 #define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
 603 #define MIPS_CONF4_MMUEXTDEF    (_ULCAST_(3) << 14)
 604 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 605
 606 #define MIPS_CONF6_SYND         (_ULCAST_(1) << 13)
 607
 608 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
 609
 610 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
 611
 612
 613 /*
 614  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
 615  */
 616 #define MIPS_FPIR_S             (_ULCAST_(1) << 16)
 617 #define MIPS_FPIR_D             (_ULCAST_(1) << 17)
 618 #define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
 619 #define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
 620 #define MIPS_FPIR_W             (_ULCAST_(1) << 20)
 621 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
 622 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
 623
 624 #ifndef __ASSEMBLY__
 625
 626 /*
 627  * Macros for handling the ISA mode bit for microMIPS.
 628  */
 629 #define get_isa16_mode(x)               ((x) & 0x1)
 630 #define msk_isa16_mode(x)               ((x) & ~0x1)
 631 #define set_isa16_mode(x)               do { (x) |= 0x1; } while(0)
 632
 633 /*
 634  * microMIPS instructions can be 16-bit or 32-bit in length. This
 635  * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
 636  */
 637 static inline int mm_insn_16bit(u16 insn)
 638 {
 639         u16 opcode = (insn >> 10) & 0x7;
 640
 641         return (opcode >= 1 && opcode <= 3) ? 1 : 0;
 642 }
 643
 644 /*
 645  * Functions to access the R10000 performance counters.  These are basically
 646  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
 647  * performance counter number encoded into bits 1 ... 5 of the instruction.
 648  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
 649  * disassembler these will look like an access to sel 0 or 1.
 650  */
 651 #define read_r10k_perf_cntr(counter)                            \
 652 ({                                                              \
 653         unsigned int __res;                                     \
 654         __asm__ __volatile__(                                   \
 655         "mfpc\t%0, %1"                                          \
 656         : "=r" (__res)                                          \
 657         : "i" (counter));                                       \
 658                                                                 \
 659         __res;                                                  \
 660 })
 661
 662 #define write_r10k_perf_cntr(counter,val)                       \
 663 do {                                                            \
 664         __asm__ __volatile__(                                   \
 665         "mtpc\t%0, %1"                                          \
 666         :                                                       \
 667         : "r" (val), "i" (counter));                            \
 668 } while (0)
 669
 670 #define read_r10k_perf_event(counter)                           \
 671 ({                                                              \
 672         unsigned int __res;                                     \
 673         __asm__ __volatile__(                                   \
 674         "mfps\t%0, %1"                                          \
 675         : "=r" (__res)                                          \
 676         : "i" (counter));                                       \
 677                                                                 \
 678         __res;                                                  \
 679 })
 680
 681 #define write_r10k_perf_cntl(counter,val)                       \
 682 do {                                                            \
 683         __asm__ __volatile__(                                   \
 684         "mtps\t%0, %1"                                          \
 685         :                                                       \
 686         : "r" (val), "i" (counter));                            \
 687 } while (0)
 688
 689
 690 /*
 691  * Macros to access the system control coprocessor
 692  */
 693
 694 #define __read_32bit_c0_register(source, sel)                           \
 695 ({ int __res;                                                           \
 696         if (sel == 0)                                                   \
 697                 __asm__ __volatile__(                                   \
 698                         "mfc0\t%0, " #source "\n\t"                     \
 699                         : "=r" (__res));                                \
 700         else                                                            \
 701                 __asm__ __volatile__(                                   \
 702                         ".set\tmips32\n\t"                              \
 703                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
 704                         ".set\tmips0\n\t"                               \
 705                         : "=r" (__res));                                \
 706         __res;                                                          \
 707 })
 708
 709 #define __read_64bit_c0_register(source, sel)                           \
 710 ({ unsigned long long __res;                                            \
 711         if (sizeof(unsigned long) == 4)                                 \
 712                 __res = __read_64bit_c0_split(source, sel);             \
 713         else if (sel == 0)                                              \
 714                 __asm__ __volatile__(                                   \
 715                         ".set\tmips3\n\t"                               \
 716                         "dmfc0\t%0, " #source "\n\t"                    \
 717                         ".set\tmips0"                                   \
 718                         : "=r" (__res));                                \
 719         else                                                            \
 720                 __asm__ __volatile__(                                   \
 721                         ".set\tmips64\n\t"                              \
 722                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
 723                         ".set\tmips0"                                   \
 724                         : "=r" (__res));                                \
 725         __res;                                                          \
 726 })
 727
 728 #define __write_32bit_c0_register(register, sel, value)                 \
 729 do {                                                                    \
 730         if (sel == 0)                                                   \
 731                 __asm__ __volatile__(                                   \
 732                         "mtc0\t%z0, " #register "\n\t"                  \
 733                         : : "Jr" ((unsigned int)(value)));              \
 734         else                                                            \
 735                 __asm__ __volatile__(                                   \
 736                         ".set\tmips32\n\t"                              \
 737                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
 738                         ".set\tmips0"                                   \
 739                         : : "Jr" ((unsigned int)(value)));              \
 740 } while (0)
 741
 742 #define __write_64bit_c0_register(register, sel, value)                 \
 743 do {                                                                    \
 744         if (sizeof(unsigned long) == 4)                                 \
 745                 __write_64bit_c0_split(register, sel, value);           \
 746         else if (sel == 0)                                              \
 747                 __asm__ __volatile__(                                   \
 748                         ".set\tmips3\n\t"                               \
 749                         "dmtc0\t%z0, " #register "\n\t"                 \
 750                         ".set\tmips0"                                   \
 751                         : : "Jr" (value));                              \
 752         else                                                            \
 753                 __asm__ __volatile__(                                   \
 754                         ".set\tmips64\n\t"                              \
 755                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
 756                         ".set\tmips0"                                   \
 757                         : : "Jr" (value));                              \
 758 } while (0)
 759
 760 #define __read_ulong_c0_register(reg, sel)                              \
 761         ((sizeof(unsigned long) == 4) ?                                 \
 762         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
 763         (unsigned long) __read_64bit_c0_register(reg, sel))
 764
 765 #define __write_ulong_c0_register(reg, sel, val)                        \
 766 do {                                                                    \
 767         if (sizeof(unsigned long) == 4)                                 \
 768                 __write_32bit_c0_register(reg, sel, val);               \
 769         else                                                            \
 770                 __write_64bit_c0_register(reg, sel, val);               \
 771 } while (0)
 772
 773 /*
 774  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
 775  */
 776 #define __read_32bit_c0_ctrl_register(source)                           \
 777 ({ int __res;                                                           \
 778         __asm__ __volatile__(                                           \
 779                 "cfc0\t%0, " #source "\n\t"                             \
 780                 : "=r" (__res));                                        \
 781         __res;                                                          \
 782 })
 783
 784 #define __write_32bit_c0_ctrl_register(register, value)                 \
 785 do {                                                                    \
 786         __asm__ __volatile__(                                           \
 787                 "ctc0\t%z0, " #register "\n\t"                          \
 788                 : : "Jr" ((unsigned int)(value)));                      \
 789 } while (0)
 790
 791 /*
 792  * These versions are only needed for systems with more than 38 bits of
 793  * physical address space running the 32-bit kernel.  That's none atm :-)
 794  */
 795 #define __read_64bit_c0_split(source, sel)                              \
 796 ({                                                                      \
 797         unsigned long long __val;                                       \
 798         unsigned long __flags;                                          \
 799                                                                         \
 800         local_irq_save(__flags);                                        \
 801         if (sel == 0)                                                   \
 802                 __asm__ __volatile__(                                   \
 803                         ".set\tmips64\n\t"                              \
 804                         "dmfc0\t%M0, " #source "\n\t"                   \
 805                         "dsll\t%L0, %M0, 32\n\t"                        \
 806                         "dsra\t%M0, %M0, 32\n\t"                        \
 807                         "dsra\t%L0, %L0, 32\n\t"                        \
 808                         ".set\tmips0"                                   \
 809                         : "=r" (__val));                                \
 810         else                                                            \
 811                 __asm__ __volatile__(                                   \
 812                         ".set\tmips64\n\t"                              \
 813                         "dmfc0\t%M0, " #source ", " #sel "\n\t"         \
 814                         "dsll\t%L0, %M0, 32\n\t"                        \
 815                         "dsra\t%M0, %M0, 32\n\t"                        \
 816                         "dsra\t%L0, %L0, 32\n\t"                        \
 817                         ".set\tmips0"                                   \
 818                         : "=r" (__val));                                \
 819         local_irq_restore(__flags);                                     \
 820                                                                         \
 821         __val;                                                          \
 822 })
 823
 824 #define __write_64bit_c0_split(source, sel, val)                        \
 825 do {                                                                    \
 826         unsigned long __flags;                                          \
 827                                                                         \
 828         local_irq_save(__flags);                                        \
 829         if (sel == 0)                                                   \
 830                 __asm__ __volatile__(                                   \
 831                         ".set\tmips64\n\t"                              \
 832                         "dsll\t%L0, %L0, 32\n\t"                        \
 833                         "dsrl\t%L0, %L0, 32\n\t"                        \
 834                         "dsll\t%M0, %M0, 32\n\t"                        \
 835                         "or\t%L0, %L0, %M0\n\t"                         \
 836                         "dmtc0\t%L0, " #source "\n\t"                   \
 837                         ".set\tmips0"                                   \
 838                         : : "r" (val));                                 \
 839         else                                                            \
 840                 __asm__ __volatile__(                                   \
 841                         ".set\tmips64\n\t"                              \
 842                         "dsll\t%L0, %L0, 32\n\t"                        \
 843                         "dsrl\t%L0, %L0, 32\n\t"                        \
 844                         "dsll\t%M0, %M0, 32\n\t"                        \
 845                         "or\t%L0, %L0, %M0\n\t"                         \
 846                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
 847                         ".set\tmips0"                                   \
 848                         : : "r" (val));                                 \
 849         local_irq_restore(__flags);                                     \
 850 } while (0)
 851
 852 #define read_c0_index()         __read_32bit_c0_register($0, 0)
 853 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
 854
 855 #define read_c0_random()        __read_32bit_c0_register($1, 0)
 856 #define write_c0_random(val)    __write_32bit_c0_register($1, 0, val)
 857
 858 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
 859 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
 860
 861 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
 862 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
 863
 864 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
 865 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
 866
 867 #define read_c0_context()       __read_ulong_c0_register($4, 0)
 868 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
 869
 870 #define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
 871 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
 872
 873 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
 874 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
 875
 876 #define read_c0_pagegrain()     __read_32bit_c0_register($5, 1)
 877 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
 878
 879 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
 880 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
 881
 882 #define read_c0_info()          __read_32bit_c0_register($7, 0)
 883
 884 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
 885 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
 886
 887 #define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
 888 #define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
 889
 890 #define read_c0_count()         __read_32bit_c0_register($9, 0)
 891 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
 892
 893 #define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
 894 #define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
 895
 896 #define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
 897 #define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
 898
 899 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
 900 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
 901
 902 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
 903 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
 904
 905 #define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
 906 #define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
 907
 908 #define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
 909 #define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
 910
 911 #define read_c0_status()        __read_32bit_c0_register($12, 0)
 912 #ifdef CONFIG_MIPS_MT_SMTC
 913 #define write_c0_status(val)                                            \
 914 do {                                                                    \
 915         __write_32bit_c0_register($12, 0, val);                         \
 916         __ehb();                                                        \
 917 } while (0)
 918 #else
 919 /*
 920  * Legacy non-SMTC code, which may be hazardous
 921  * but which might not support EHB
 922  */
 923 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
 924 #endif /* CONFIG_MIPS_MT_SMTC */
 925
 926 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
 927 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
 928
 929 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
 930 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
 931
 932 #define read_c0_prid()          __read_32bit_c0_register($15, 0)
 933
 934 #define read_c0_config()        __read_32bit_c0_register($16, 0)
 935 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
 936 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
 937 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
 938 #define read_c0_config4()       __read_32bit_c0_register($16, 4)
 939 #define read_c0_config5()       __read_32bit_c0_register($16, 5)
 940 #define read_c0_config6()       __read_32bit_c0_register($16, 6)
 941 #define read_c0_config7()       __read_32bit_c0_register($16, 7)
 942 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
 943 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
 944 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
 945 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
 946 #define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
 947 #define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
 948 #define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
 949 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
 950
 951 /*
 952  * The WatchLo register.  There may be up to 8 of them.
 953  */
 954 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
 955 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
 956 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
 957 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
 958 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
 959 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
 960 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
 961 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
 962 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
 963 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
 964 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
 965 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
 966 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
 967 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
 968 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
 969 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
 970
 971 /*
 972  * The WatchHi register.  There may be up to 8 of them.
 973  */
 974 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
 975 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
 976 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
 977 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
 978 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
 979 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
 980 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
 981 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
 982
 983 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
 984 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
 985 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
 986 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
 987 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
 988 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
 989 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
 990 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
 991
 992 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
 993 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
 994
 995 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
 996 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
 997
 998 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
 999 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1000
1001 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
1002 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
1003
1004 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
1005 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
1006
1007 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
1008 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
1009
1010 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
1011 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
1012
1013 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
1014 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
1015
1016 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
1017 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
1018
1019 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
1020 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
1021
1022 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
1023 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
1024
1025 /*
1026  * MIPS32 / MIPS64 performance counters
1027  */
1028 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
1029 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1030 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
1031 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1032 #define read_c0_perfcntr0_64()  __read_64bit_c0_register($25, 1)
1033 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1034 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
1035 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1036 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
1037 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1038 #define read_c0_perfcntr1_64()  __read_64bit_c0_register($25, 3)
1039 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1040 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
1041 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1042 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
1043 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1044 #define read_c0_perfcntr2_64()  __read_64bit_c0_register($25, 5)
1045 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1046 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
1047 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1048 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
1049 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1050 #define read_c0_perfcntr3_64()  __read_64bit_c0_register($25, 7)
1051 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1052
1053 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
1054 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
1055
1056 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
1057 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1058
1059 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
1060
1061 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
1062 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1063
1064 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
1065 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
1066
1067 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
1068 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
1069
1070 #define read_c0_ddatalo()       __read_32bit_c0_register($28, 3)
1071 #define write_c0_ddatalo(val)   __write_32bit_c0_register($28, 3, val)
1072
1073 #define read_c0_staglo()        __read_32bit_c0_register($28, 4)
1074 #define write_c0_staglo(val)    __write_32bit_c0_register($28, 4, val)
1075
1076 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
1077 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
1078
1079 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
1080 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
1081
1082 /* MIPSR2 */
1083 #define read_c0_hwrena()        __read_32bit_c0_register($7, 0)
1084 #define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
1085
1086 #define read_c0_intctl()        __read_32bit_c0_register($12, 1)
1087 #define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
1088
1089 #define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
1090 #define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
1091
1092 #define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
1093 #define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
1094
1095 #define read_c0_ebase()         __read_32bit_c0_register($15, 1)
1096 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
1097
1098
1099 /* Cavium OCTEON (cnMIPS) */
1100 #define read_c0_cvmcount()      __read_ulong_c0_register($9, 6)
1101 #define write_c0_cvmcount(val)  __write_ulong_c0_register($9, 6, val)
1102
1103 #define read_c0_cvmctl()        __read_64bit_c0_register($9, 7)
1104 #define write_c0_cvmctl(val)    __write_64bit_c0_register($9, 7, val)
1105
1106 #define read_c0_cvmmemctl()     __read_64bit_c0_register($11, 7)
1107 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1108 /*
1109  * The cacheerr registers are not standardized.  On OCTEON, they are
1110  * 64 bits wide.
1111  */
1112 #define read_octeon_c0_icacheerr()      __read_64bit_c0_register($27, 0)
1113 #define write_octeon_c0_icacheerr(val)  __write_64bit_c0_register($27, 0, val)
1114
1115 #define read_octeon_c0_dcacheerr()      __read_64bit_c0_register($27, 1)
1116 #define write_octeon_c0_dcacheerr(val)  __write_64bit_c0_register($27, 1, val)
1117
1118 /* BMIPS3300 */
1119 #define read_c0_brcm_config_0()         __read_32bit_c0_register($22, 0)
1120 #define write_c0_brcm_config_0(val)     __write_32bit_c0_register($22, 0, val)
1121
1122 #define read_c0_brcm_bus_pll()          __read_32bit_c0_register($22, 4)
1123 #define write_c0_brcm_bus_pll(val)      __write_32bit_c0_register($22, 4, val)
1124
1125 #define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
1126 #define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
1127
1128 /* BMIPS43xx */
1129 #define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
1130 #define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
1131
1132 #define read_c0_brcm_cmt_ctrl()         __read_32bit_c0_register($22, 2)
1133 #define write_c0_brcm_cmt_ctrl(val)     __write_32bit_c0_register($22, 2, val)
1134
1135 #define read_c0_brcm_cmt_local()        __read_32bit_c0_register($22, 3)
1136 #define write_c0_brcm_cmt_local(val)    __write_32bit_c0_register($22, 3, val)
1137
1138 #define read_c0_brcm_config_1()         __read_32bit_c0_register($22, 5)
1139 #define write_c0_brcm_config_1(val)     __write_32bit_c0_register($22, 5, val)
1140
1141 #define read_c0_brcm_cbr()              __read_32bit_c0_register($22, 6)
1142 #define write_c0_brcm_cbr(val)          __write_32bit_c0_register($22, 6, val)
1143
1144 /* BMIPS5000 */
1145 #define read_c0_brcm_config()           __read_32bit_c0_register($22, 0)
1146 #define write_c0_brcm_config(val)       __write_32bit_c0_register($22, 0, val)
1147
1148 #define read_c0_brcm_mode()             __read_32bit_c0_register($22, 1)
1149 #define write_c0_brcm_mode(val)         __write_32bit_c0_register($22, 1, val)
1150
1151 #define read_c0_brcm_action()           __read_32bit_c0_register($22, 2)
1152 #define write_c0_brcm_action(val)       __write_32bit_c0_register($22, 2, val)
1153
1154 #define read_c0_brcm_edsp()             __read_32bit_c0_register($22, 3)
1155 #define write_c0_brcm_edsp(val)         __write_32bit_c0_register($22, 3, val)
1156
1157 #define read_c0_brcm_bootvec()          __read_32bit_c0_register($22, 4)
1158 #define write_c0_brcm_bootvec(val)      __write_32bit_c0_register($22, 4, val)
1159
1160 #define read_c0_brcm_sleepcount()       __read_32bit_c0_register($22, 7)
1161 #define write_c0_brcm_sleepcount(val)   __write_32bit_c0_register($22, 7, val)
1162
1163 /*
1164  * Macros to access the floating point coprocessor control registers
1165  */
1166 #define read_32bit_cp1_register(source)                                 \
1167 ({                                                                      \
1168         int __res;                                                      \
1169                                                                         \
1170         __asm__ __volatile__(                                           \
1171         "       .set    push                                    \n"     \
1172         "       .set    reorder                                 \n"     \
1173         "       # gas fails to assemble cfc1 for some archs,    \n"     \
1174         "       # like Octeon.                                  \n"     \
1175         "       .set    mips1                                   \n"     \
1176         "       cfc1    %0,"STR(source)"                        \n"     \
1177         "       .set    pop                                     \n"     \
1178         : "=r" (__res));                                                \
1179         __res;                                                          \
1180 })
1181
1182 #ifdef HAVE_AS_DSP
1183 #define rddsp(mask)                                                     \
1184 ({                                                                      \
1185         unsigned int __dspctl;                                          \
1186                                                                         \
1187         __asm__ __volatile__(                                           \
1188         "       .set push                                       \n"     \
1189         "       .set dsp                                        \n"     \
1190         "       rddsp   %0, %x1                                 \n"     \
1191         "       .set pop                                        \n"     \
1192         : "=r" (__dspctl)                                               \
1193         : "i" (mask));                                                  \
1194         __dspctl;                                                       \
1195 })
1196
1197 #define wrdsp(val, mask)                                                \
1198 do {                                                                    \
1199         __asm__ __volatile__(                                           \
1200         "       .set push                                       \n"     \
1201         "       .set dsp                                        \n"     \
1202         "       wrdsp   %0, %x1                                 \n"     \
1203         "       .set pop                                        \n"     \
1204         :                                                               \
1205         : "r" (val), "i" (mask));                                       \
1206 } while (0)
1207
1208 #define mflo0()                                                         \
1209 ({                                                                      \
1210         long mflo0;                                                     \
1211         __asm__(                                                        \
1212         "       .set push                                       \n"     \
1213         "       .set dsp                                        \n"     \
1214         "       mflo %0, $ac0                                   \n"     \
1215         "       .set pop                                        \n"     \
1216         : "=r" (mflo0));                                                \
1217         mflo0;                                                          \
1218 })
1219
1220 #define mflo1()                                                         \
1221 ({                                                                      \
1222         long mflo1;                                                     \
1223         __asm__(                                                        \
1224         "       .set push                                       \n"     \
1225         "       .set dsp                                        \n"     \
1226         "       mflo %0, $ac1                                   \n"     \
1227         "       .set pop                                        \n"     \
1228         : "=r" (mflo1));                                                \
1229         mflo1;                                                          \
1230 })
1231
1232 #define mflo2()                                                         \
1233 ({                                                                      \
1234         long mflo2;                                                     \
1235         __asm__(                                                        \
1236         "       .set push                                       \n"     \
1237         "       .set dsp                                        \n"     \
1238         "       mflo %0, $ac2                                   \n"     \
1239         "       .set pop                                        \n"     \
1240         : "=r" (mflo2));                                                \
1241         mflo2;                                                          \
1242 })
1243
1244 #define mflo3()                                                         \
1245 ({                                                                      \
1246         long mflo3;                                                     \
1247         __asm__(                                                        \
1248         "       .set push                                       \n"     \
1249         "       .set dsp                                        \n"     \
1250         "       mflo %0, $ac3                                   \n"     \
1251         "       .set pop                                        \n"     \
1252         : "=r" (mflo3));                                                \
1253         mflo3;                                                          \
1254 })
1255
1256 #define mfhi0()                                                         \
1257 ({                                                                      \
1258         long mfhi0;                                                     \
1259         __asm__(                                                        \
1260         "       .set push                                       \n"     \
1261         "       .set dsp                                        \n"     \
1262         "       mfhi %0, $ac0                                   \n"     \
1263         "       .set pop                                        \n"     \
1264         : "=r" (mfhi0));                                                \
1265         mfhi0;                                                          \
1266 })
1267
1268 #define mfhi1()                                                         \
1269 ({                                                                      \
1270         long mfhi1;                                                     \
1271         __asm__(                                                        \
1272         "       .set push                                       \n"     \
1273         "       .set dsp                                        \n"     \
1274         "       mfhi %0, $ac1                                   \n"     \
1275         "       .set pop                                        \n"     \
1276         : "=r" (mfhi1));                                                \
1277         mfhi1;                                                          \
1278 })
1279
1280 #define mfhi2()                                                         \
1281 ({                                                                      \
1282         long mfhi2;                                                     \
1283         __asm__(                                                        \
1284         "       .set push                                       \n"     \
1285         "       .set dsp                                        \n"     \
1286         "       mfhi %0, $ac2                                   \n"     \
1287         "       .set pop                                        \n"     \
1288         : "=r" (mfhi2));                                                \
1289         mfhi2;                                                          \
1290 })
1291
1292 #define mfhi3()                                                         \
1293 ({                                                                      \
1294         long mfhi3;                                                     \
1295         __asm__(                                                        \
1296         "       .set push                                       \n"     \
1297         "       .set dsp                                        \n"     \
1298         "       mfhi %0, $ac3                                   \n"     \
1299         "       .set pop                                        \n"     \
1300         : "=r" (mfhi3));                                                \
1301         mfhi3;                                                          \
1302 })
1303
1304
1305 #define mtlo0(x)                                                        \
1306 ({                                                                      \
1307         __asm__(                                                        \
1308         "       .set push                                       \n"     \
1309         "       .set dsp                                        \n"     \
1310         "       mtlo %0, $ac0                                   \n"     \
1311         "       .set pop                                        \n"     \
1312         :                                                               \
1313         : "r" (x));                                                     \
1314 })
1315
1316 #define mtlo1(x)                                                        \
1317 ({                                                                      \
1318         __asm__(                                                        \
1319         "       .set push                                       \n"     \
1320         "       .set dsp                                        \n"     \
1321         "       mtlo %0, $ac1                                   \n"     \
1322         "       .set pop                                        \n"     \
1323         :                                                               \
1324         : "r" (x));                                                     \
1325 })
1326
1327 #define mtlo2(x)                                                        \
1328 ({                                                                      \
1329         __asm__(                                                        \
1330         "       .set push                                       \n"     \
1331         "       .set dsp                                        \n"     \
1332         "       mtlo %0, $ac2                                   \n"     \
1333         "       .set pop                                        \n"     \
1334         :                                                               \
1335         : "r" (x));                                                     \
1336 })
1337
1338 #define mtlo3(x)                                                        \
1339 ({                                                                      \
1340         __asm__(                                                        \
1341         "       .set push                                       \n"     \
1342         "       .set dsp                                        \n"     \
1343         "       mtlo %0, $ac3                                   \n"     \
1344         "       .set pop                                        \n"     \
1345         :                                                               \
1346         : "r" (x));                                                     \
1347 })
1348
1349 #define mthi0(x)                                                        \
1350 ({                                                                      \
1351         __asm__(                                                        \
1352         "       .set push                                       \n"     \
1353         "       .set dsp                                        \n"     \
1354         "       mthi %0, $ac0                                   \n"     \
1355         "       .set pop                                        \n"     \
1356         :                                                               \
1357         : "r" (x));                                                     \
1358 })
1359
1360 #define mthi1(x)                                                        \
1361 ({                                                                      \
1362         __asm__(                                                        \
1363         "       .set push                                       \n"     \
1364         "       .set dsp                                        \n"     \
1365         "       mthi %0, $ac1                                   \n"     \
1366         "       .set pop                                        \n"     \
1367         :                                                               \
1368         : "r" (x));                                                     \
1369 })
1370
1371 #define mthi2(x)                                                        \
1372 ({                                                                      \
1373         __asm__(                                                        \
1374         "       .set push                                       \n"     \
1375         "       .set dsp                                        \n"     \
1376         "       mthi %0, $ac2                                   \n"     \
1377         "       .set pop                                        \n"     \
1378         :                                                               \
1379         : "r" (x));                                                     \
1380 })
1381
1382 #define mthi3(x)                                                        \
1383 ({                                                                      \
1384         __asm__(                                                        \
1385         "       .set push                                       \n"     \
1386         "       .set dsp                                        \n"     \
1387         "       mthi %0, $ac3                                   \n"     \
1388         "       .set pop                                        \n"     \
1389         :                                                               \
1390         : "r" (x));                                                     \
1391 })
1392
1393 #else
1394
1395 #ifdef CONFIG_CPU_MICROMIPS
1396 #define rddsp(mask)                                                     \
1397 ({                                                                      \
1398         unsigned int __res;                                             \
1399                                                                         \
1400         __asm__ __volatile__(                                           \
1401         "       .set    push                                    \n"     \
1402         "       .set    noat                                    \n"     \
1403         "       # rddsp $1, %x1                                 \n"     \
1404         "       .hword  ((0x0020067c | (%x1 << 14)) >> 16)      \n"     \
1405         "       .hword  ((0x0020067c | (%x1 << 14)) & 0xffff)   \n"     \
1406         "       move    %0, $1                                  \n"     \
1407         "       .set    pop                                     \n"     \
1408         : "=r" (__res)                                                  \
1409         : "i" (mask));                                                  \
1410         __res;                                                          \
1411 })
1412
1413 #define wrdsp(val, mask)                                                \
1414 do {                                                                    \
1415         __asm__ __volatile__(                                           \
1416         "       .set    push                                    \n"     \
1417         "       .set    noat                                    \n"     \
1418         "       move    $1, %0                                  \n"     \
1419         "       # wrdsp $1, %x1                                 \n"     \
1420         "       .hword  ((0x0020167c | (%x1 << 14)) >> 16)      \n"     \
1421         "       .hword  ((0x0020167c | (%x1 << 14)) & 0xffff)   \n"     \
1422         "       .set    pop                                     \n"     \
1423         :                                                               \
1424         : "r" (val), "i" (mask));                                       \
1425 } while (0)
1426
1427 #define _umips_dsp_mfxxx(ins)                                           \
1428 ({                                                                      \
1429         unsigned long __treg;                                           \
1430                                                                         \
1431         __asm__ __volatile__(                                           \
1432         "       .set    push                                    \n"     \
1433         "       .set    noat                                    \n"     \
1434         "       .hword  0x0001                                  \n"     \
1435         "       .hword  %x1                                     \n"     \
1436         "       move    %0, $1                                  \n"     \
1437         "       .set    pop                                     \n"     \
1438         : "=r" (__treg)                                                 \
1439         : "i" (ins));                                                   \
1440         __treg;                                                         \
1441 })
1442
1443 #define _umips_dsp_mtxxx(val, ins)                                      \
1444 do {                                                                    \
1445         __asm__ __volatile__(                                           \
1446         "       .set    push                                    \n"     \
1447         "       .set    noat                                    \n"     \
1448         "       move    $1, %0                                  \n"     \
1449         "       .hword  0x0001                                  \n"     \
1450         "       .hword  %x1                                     \n"     \
1451         "       .set    pop                                     \n"     \
1452         :                                                               \
1453         : "r" (val), "i" (ins));                                        \
1454 } while (0)
1455
1456 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
1457 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
1458
1459 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
1460 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
1461
1462 #define mflo0() _umips_dsp_mflo(0)
1463 #define mflo1() _umips_dsp_mflo(1)
1464 #define mflo2() _umips_dsp_mflo(2)
1465 #define mflo3() _umips_dsp_mflo(3)
1466
1467 #define mfhi0() _umips_dsp_mfhi(0)
1468 #define mfhi1() _umips_dsp_mfhi(1)
1469 #define mfhi2() _umips_dsp_mfhi(2)
1470 #define mfhi3() _umips_dsp_mfhi(3)
1471
1472 #define mtlo0(x) _umips_dsp_mtlo(x, 0)
1473 #define mtlo1(x) _umips_dsp_mtlo(x, 1)
1474 #define mtlo2(x) _umips_dsp_mtlo(x, 2)
1475 #define mtlo3(x) _umips_dsp_mtlo(x, 3)
1476
1477 #define mthi0(x) _umips_dsp_mthi(x, 0)
1478 #define mthi1(x) _umips_dsp_mthi(x, 1)
1479 #define mthi2(x) _umips_dsp_mthi(x, 2)
1480 #define mthi3(x) _umips_dsp_mthi(x, 3)
1481
1482 #else  /* !CONFIG_CPU_MICROMIPS */
1483 #define rddsp(mask)                                                     \
1484 ({                                                                      \
1485         unsigned int __res;                                             \
1486                                                                         \
1487         __asm__ __volatile__(                                           \
1488         "       .set    push                            \n"             \
1489         "       .set    noat                            \n"             \
1490         "       # rddsp $1, %x1                         \n"             \
1491         "       .word   0x7c000cb8 | (%x1 << 16)        \n"             \
1492         "       move    %0, $1                          \n"             \
1493         "       .set    pop                             \n"             \
1494         : "=r" (__res)                                                  \
1495         : "i" (mask));                                                  \
1496         __res;                                                          \
1497 })
1498
1499 #define wrdsp(val, mask)                                                \
1500 do {                                                                    \
1501         __asm__ __volatile__(                                           \
1502         "       .set    push                                    \n"     \
1503         "       .set    noat                                    \n"     \
1504         "       move    $1, %0                                  \n"     \
1505         "       # wrdsp $1, %x1                                 \n"     \
1506         "       .word   0x7c2004f8 | (%x1 << 11)                \n"     \
1507         "       .set    pop                                     \n"     \
1508         :                                                               \
1509         : "r" (val), "i" (mask));                                       \
1510 } while (0)
1511
1512 #define _dsp_mfxxx(ins)                                                 \
1513 ({                                                                      \
1514         unsigned long __treg;                                           \
1515                                                                         \
1516         __asm__ __volatile__(                                           \
1517         "       .set    push                                    \n"     \
1518         "       .set    noat                                    \n"     \
1519         "       .word   (0x00000810 | %1)                       \n"     \
1520         "       move    %0, $1                                  \n"     \
1521         "       .set    pop                                     \n"     \
1522         : "=r" (__treg)                                                 \
1523         : "i" (ins));                                                   \
1524         __treg;                                                         \
1525 })
1526
1527 #define _dsp_mtxxx(val, ins)                                            \
1528 do {                                                                    \
1529         __asm__ __volatile__(                                           \
1530         "       .set    push                                    \n"     \
1531         "       .set    noat                                    \n"     \
1532         "       move    $1, %0                                  \n"     \
1533         "       .word   (0x00200011 | %1)                       \n"     \
1534         "       .set    pop                                     \n"     \
1535         :                                                               \
1536         : "r" (val), "i" (ins));                                        \
1537 } while (0)
1538
1539 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
1540 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
1541
1542 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
1543 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1544
1545 #define mflo0() _dsp_mflo(0)
1546 #define mflo1() _dsp_mflo(1)
1547 #define mflo2() _dsp_mflo(2)
1548 #define mflo3() _dsp_mflo(3)
1549
1550 #define mfhi0() _dsp_mfhi(0)
1551 #define mfhi1() _dsp_mfhi(1)
1552 #define mfhi2() _dsp_mfhi(2)
1553 #define mfhi3() _dsp_mfhi(3)
1554
1555 #define mtlo0(x) _dsp_mtlo(x, 0)
1556 #define mtlo1(x) _dsp_mtlo(x, 1)
1557 #define mtlo2(x) _dsp_mtlo(x, 2)
1558 #define mtlo3(x) _dsp_mtlo(x, 3)
1559
1560 #define mthi0(x) _dsp_mthi(x, 0)
1561 #define mthi1(x) _dsp_mthi(x, 1)
1562 #define mthi2(x) _dsp_mthi(x, 2)
1563 #define mthi3(x) _dsp_mthi(x, 3)
1564
1565 #endif /* CONFIG_CPU_MICROMIPS */
1566 #endif
1567
1568 /*
1569  * TLB operations.
1570  *
1571  * It is responsibility of the caller to take care of any TLB hazards.
1572  */
1573 static inline void tlb_probe(void)
1574 {
1575         __asm__ __volatile__(
1576                 ".set noreorder\n\t"
1577                 "tlbp\n\t"
1578                 ".set reorder");
1579 }
1580
1581 static inline void tlb_read(void)
1582 {
1583 #if MIPS34K_MISSED_ITLB_WAR
1584         int res = 0;
1585
1586         __asm__ __volatile__(
1587         "       .set    push                                    \n"
1588         "       .set    noreorder                               \n"
1589         "       .set    noat                                    \n"
1590         "       .set    mips32r2                                \n"
1591         "       .word   0x41610001              # dvpe $1       \n"
1592         "       move    %0, $1                                  \n"
1593         "       ehb                                             \n"
1594         "       .set    pop                                     \n"
1595         : "=r" (res));
1596
1597         instruction_hazard();
1598 #endif
1599
1600         __asm__ __volatile__(
1601                 ".set noreorder\n\t"
1602                 "tlbr\n\t"
1603                 ".set reorder");
1604
1605 #if MIPS34K_MISSED_ITLB_WAR
1606         if ((res & _ULCAST_(1)))
1607                 __asm__ __volatile__(
1608                 "       .set    push                            \n"
1609                 "       .set    noreorder                       \n"
1610                 "       .set    noat                            \n"
1611                 "       .set    mips32r2                        \n"
1612                 "       .word   0x41600021      # evpe          \n"
1613                 "       ehb                                     \n"
1614                 "       .set    pop                             \n");
1615 #endif
1616 }
1617
1618 static inline void tlb_write_indexed(void)
1619 {
1620         __asm__ __volatile__(
1621                 ".set noreorder\n\t"
1622                 "tlbwi\n\t"
1623                 ".set reorder");
1624 }
1625
1626 static inline void tlb_write_random(void)
1627 {
1628         __asm__ __volatile__(
1629                 ".set noreorder\n\t"
1630                 "tlbwr\n\t"
1631                 ".set reorder");
1632 }
1633
1634 /*
1635  * Manipulate bits in a c0 register.
1636  */
1637 #ifndef CONFIG_MIPS_MT_SMTC
1638 /*
1639  * SMTC Linux requires shutting-down microthread scheduling
1640  * during CP0 register read-modify-write sequences.
1641  */
1642 #define __BUILD_SET_C0(name)                                    \
1643 static inline unsigned int                                      \
1644 set_c0_##name(unsigned int set)                                 \
1645 {                                                               \
1646         unsigned int res, new;                                  \
1647                                                                 \
1648         res = read_c0_##name();                                 \
1649         new = res | set;                                        \
1650         write_c0_##name(new);                                   \
1651                                                                 \
1652         return res;                                             \
1653 }                                                               \
1654                                                                 \
1655 static inline unsigned int                                      \
1656 clear_c0_##name(unsigned int clear)                             \
1657 {                                                               \
1658         unsigned int res, new;                                  \
1659                                                                 \
1660         res = read_c0_##name();                                 \
1661         new = res & ~clear;                                     \
1662         write_c0_##name(new);                                   \
1663                                                                 \
1664         return res;                                             \
1665 }                                                               \
1666                                                                 \
1667 static inline unsigned int                                      \
1668 change_c0_##name(unsigned int change, unsigned int val)         \
1669 {                                                               \
1670         unsigned int res, new;                                  \
1671                                                                 \
1672         res = read_c0_##name();                                 \
1673         new = res & ~change;                                    \
1674         new |= (val & change);                                  \
1675         write_c0_##name(new);                                   \
1676                                                                 \
1677         return res;                                             \
1678 }
1679
1680 #else /* SMTC versions that manage MT scheduling */
1681
1682 #include <linux/irqflags.h>
1683
1684 /*
1685  * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with
1686  * header file recursion.
1687  */
1688 static inline unsigned int __dmt(void)
1689 {
1690         int res;
1691
1692         __asm__ __volatile__(
1693         "       .set    push                                            \n"
1694         "       .set    mips32r2                                        \n"
1695         "       .set    noat                                            \n"
1696         "       .word   0x41610BC1                      # dmt $1        \n"
1697         "       ehb                                                     \n"
1698         "       move    %0, $1                                          \n"
1699         "       .set    pop                                             \n"
1700         : "=r" (res));
1701
1702         instruction_hazard();
1703
1704         return res;
1705 }
1706
1707 #define __VPECONTROL_TE_SHIFT   15
1708 #define __VPECONTROL_TE         (1UL << __VPECONTROL_TE_SHIFT)
1709
1710 #define __EMT_ENABLE            __VPECONTROL_TE
1711
1712 static inline void __emt(unsigned int previous)
1713 {
1714         if ((previous & __EMT_ENABLE))
1715                 __asm__ __volatile__(
1716                 "       .set    mips32r2                                \n"
1717                 "       .word   0x41600be1              # emt           \n"
1718                 "       ehb                                             \n"
1719                 "       .set    mips0                                   \n");
1720 }
1721
1722 static inline void __ehb(void)
1723 {
1724         __asm__ __volatile__(
1725         "       .set    mips32r2                                        \n"
1726         "       ehb                                                     \n"             "       .set    mips0                                           \n");
1727 }
1728
1729 /*
1730  * Note that local_irq_save/restore affect TC-specific IXMT state,
1731  * not Status.IE as in non-SMTC kernel.
1732  */
1733
1734 #define __BUILD_SET_C0(name)                                    \
1735 static inline unsigned int                                      \
1736 set_c0_##name(unsigned int set)                                 \
1737 {                                                               \
1738         unsigned int res;                                       \
1739         unsigned int new;                                       \
1740         unsigned int omt;                                       \
1741         unsigned long flags;                                    \
1742                                                                 \
1743         local_irq_save(flags);                                  \
1744         omt = __dmt();                                          \
1745         res = read_c0_##name();                                 \
1746         new = res | set;                                        \
1747         write_c0_##name(new);                                   \
1748         __emt(omt);                                             \
1749         local_irq_restore(flags);                               \
1750                                                                 \
1751         return res;                                             \
1752 }                                                               \
1753                                                                 \
1754 static inline unsigned int                                      \
1755 clear_c0_##name(unsigned int clear)                             \
1756 {                                                               \
1757         unsigned int res;                                       \
1758         unsigned int new;                                       \
1759         unsigned int omt;                                       \
1760         unsigned long flags;                                    \
1761                                                                 \
1762         local_irq_save(flags);                                  \
1763         omt = __dmt();                                          \
1764         res = read_c0_##name();                                 \
1765         new = res & ~clear;                                     \
1766         write_c0_##name(new);                                   \
1767         __emt(omt);                                             \
1768         local_irq_restore(flags);                               \
1769                                                                 \
1770         return res;                                             \
1771 }                                                               \
1772                                                                 \
1773 static inline unsigned int                                      \
1774 change_c0_##name(unsigned int change, unsigned int newbits)     \
1775 {                                                               \
1776         unsigned int res;                                       \
1777         unsigned int new;                                       \
1778         unsigned int omt;                                       \
1779         unsigned long flags;                                    \
1780                                                                 \
1781         local_irq_save(flags);                                  \
1782                                                                 \
1783         omt = __dmt();                                          \
1784         res = read_c0_##name();                                 \
1785         new = res & ~change;                                    \
1786         new |= (newbits & change);                              \
1787         write_c0_##name(new);                                   \
1788         __emt(omt);                                             \
1789         local_irq_restore(flags);                               \
1790                                                                 \
1791         return res;                                             \
1792 }
1793 #endif
1794
1795 __BUILD_SET_C0(status)
1796 __BUILD_SET_C0(cause)
1797 __BUILD_SET_C0(config)
1798 __BUILD_SET_C0(intcontrol)
1799 __BUILD_SET_C0(intctl)
1800 __BUILD_SET_C0(srsmap)
1801 __BUILD_SET_C0(brcm_config_0)
1802 __BUILD_SET_C0(brcm_bus_pll)
1803 __BUILD_SET_C0(brcm_reset)
1804 __BUILD_SET_C0(brcm_cmt_intr)
1805 __BUILD_SET_C0(brcm_cmt_ctrl)
1806 __BUILD_SET_C0(brcm_config)
1807 __BUILD_SET_C0(brcm_mode)
1808
1809 #endif /* !__ASSEMBLY__ */
1810
1811 #endif /* _ASM_MIPSREGS_H */