arch/mips/include/asm/mipsregs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   7  * Copyright (C) 2000 Silicon Graphics, Inc.
   8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
  11  * Copyright (C) 2003, 2004  Maciej W. Rozycki
  12  */
  13 #ifndef _ASM_MIPSREGS_H
  14 #define _ASM_MIPSREGS_H
  15
  16 #include <linux/linkage.h>
  17 #include <linux/types.h>
  18 #include <asm/hazards.h>
  19 #include <asm/war.h>
  20
  21 /*
  22  * The following macros are especially useful for __asm__
  23  * inline assembler.
  24  */
  25 #ifndef __STR
  26 #define __STR(x) #x
  27 #endif
  28 #ifndef STR
  29 #define STR(x) __STR(x)
  30 #endif
  31
  32 /*
  33  *  Configure language
  34  */
  35 #ifdef __ASSEMBLY__
  36 #define _ULCAST_
  37 #else
  38 #define _ULCAST_ (unsigned long)
  39 #endif
  40
  41 /*
  42  * Coprocessor 0 register names
  43  */
  44 #define CP0_INDEX $0
  45 #define CP0_RANDOM $1
  46 #define CP0_ENTRYLO0 $2
  47 #define CP0_ENTRYLO1 $3
  48 #define CP0_CONF $3
  49 #define CP0_CONTEXT $4
  50 #define CP0_PAGEMASK $5
  51 #define CP0_WIRED $6
  52 #define CP0_INFO $7
  53 #define CP0_HWRENA $7, 0
  54 #define CP0_BADVADDR $8
  55 #define CP0_BADINSTR $8, 1
  56 #define CP0_COUNT $9
  57 #define CP0_ENTRYHI $10
  58 #define CP0_COMPARE $11
  59 #define CP0_STATUS $12
  60 #define CP0_CAUSE $13
  61 #define CP0_EPC $14
  62 #define CP0_PRID $15
  63 #define CP0_EBASE $15, 1
  64 #define CP0_CMGCRBASE $15, 3
  65 #define CP0_CONFIG $16
  66 #define CP0_CONFIG3 $16, 3
  67 #define CP0_CONFIG5 $16, 5
  68 #define CP0_LLADDR $17
  69 #define CP0_WATCHLO $18
  70 #define CP0_WATCHHI $19
  71 #define CP0_XCONTEXT $20
  72 #define CP0_FRAMEMASK $21
  73 #define CP0_DIAGNOSTIC $22
  74 #define CP0_DEBUG $23
  75 #define CP0_DEPC $24
  76 #define CP0_PERFORMANCE $25
  77 #define CP0_ECC $26
  78 #define CP0_CACHEERR $27
  79 #define CP0_TAGLO $28
  80 #define CP0_TAGHI $29
  81 #define CP0_ERROREPC $30
  82 #define CP0_DESAVE $31
  83
  84 /*
  85  * R4640/R4650 cp0 register names.  These registers are listed
  86  * here only for completeness; without MMU these CPUs are not useable
  87  * by Linux.  A future ELKS port might take make Linux run on them
  88  * though ...
  89  */
  90 #define CP0_IBASE $0
  91 #define CP0_IBOUND $1
  92 #define CP0_DBASE $2
  93 #define CP0_DBOUND $3
  94 #define CP0_CALG $17
  95 #define CP0_IWATCH $18
  96 #define CP0_DWATCH $19
  97
  98 /*
  99  * Coprocessor 0 Set 1 register names
 100  */
 101 #define CP0_S1_DERRADDR0  $26
 102 #define CP0_S1_DERRADDR1  $27
 103 #define CP0_S1_INTCONTROL $20
 104
 105 /*
 106  * Coprocessor 0 Set 2 register names
 107  */
 108 #define CP0_S2_SRSCTL     $12   /* MIPSR2 */
 109
 110 /*
 111  * Coprocessor 0 Set 3 register names
 112  */
 113 #define CP0_S3_SRSMAP     $12   /* MIPSR2 */
 114
 115 /*
 116  *  TX39 Series
 117  */
 118 #define CP0_TX39_CACHE  $7
 119
 120
 121 /* Generic EntryLo bit definitions */
 122 #define ENTRYLO_G               (_ULCAST_(1) << 0)
 123 #define ENTRYLO_V               (_ULCAST_(1) << 1)
 124 #define ENTRYLO_D               (_ULCAST_(1) << 2)
 125 #define ENTRYLO_C_SHIFT         3
 126 #define ENTRYLO_C               (_ULCAST_(7) << ENTRYLO_C_SHIFT)
 127
 128 /* R3000 EntryLo bit definitions */
 129 #define R3K_ENTRYLO_G           (_ULCAST_(1) << 8)
 130 #define R3K_ENTRYLO_V           (_ULCAST_(1) << 9)
 131 #define R3K_ENTRYLO_D           (_ULCAST_(1) << 10)
 132 #define R3K_ENTRYLO_N           (_ULCAST_(1) << 11)
 133
 134 /* MIPS32/64 EntryLo bit definitions */
 135 #define MIPS_ENTRYLO_PFN_SHIFT  6
 136 #define MIPS_ENTRYLO_XI         (_ULCAST_(1) << (BITS_PER_LONG - 2))
 137 #define MIPS_ENTRYLO_RI         (_ULCAST_(1) << (BITS_PER_LONG - 1))
 138
 139 /*
 140  * Values for PageMask register
 141  */
 142 #ifdef CONFIG_CPU_VR41XX
 143
 144 /* Why doesn't stupidity hurt ... */
 145
 146 #define PM_1K           0x00000000
 147 #define PM_4K           0x00001800
 148 #define PM_16K          0x00007800
 149 #define PM_64K          0x0001f800
 150 #define PM_256K         0x0007f800
 151
 152 #else
 153
 154 #define PM_4K           0x00000000
 155 #define PM_8K           0x00002000
 156 #define PM_16K          0x00006000
 157 #define PM_32K          0x0000e000
 158 #define PM_64K          0x0001e000
 159 #define PM_128K         0x0003e000
 160 #define PM_256K         0x0007e000
 161 #define PM_512K         0x000fe000
 162 #define PM_1M           0x001fe000
 163 #define PM_2M           0x003fe000
 164 #define PM_4M           0x007fe000
 165 #define PM_8M           0x00ffe000
 166 #define PM_16M          0x01ffe000
 167 #define PM_32M          0x03ffe000
 168 #define PM_64M          0x07ffe000
 169 #define PM_256M         0x1fffe000
 170 #define PM_1G           0x7fffe000
 171
 172 #endif
 173
 174 /*
 175  * Default page size for a given kernel configuration
 176  */
 177 #ifdef CONFIG_PAGE_SIZE_4KB
 178 #define PM_DEFAULT_MASK PM_4K
 179 #elif defined(CONFIG_PAGE_SIZE_8KB)
 180 #define PM_DEFAULT_MASK PM_8K
 181 #elif defined(CONFIG_PAGE_SIZE_16KB)
 182 #define PM_DEFAULT_MASK PM_16K
 183 #elif defined(CONFIG_PAGE_SIZE_32KB)
 184 #define PM_DEFAULT_MASK PM_32K
 185 #elif defined(CONFIG_PAGE_SIZE_64KB)
 186 #define PM_DEFAULT_MASK PM_64K
 187 #else
 188 #error Bad page size configuration!
 189 #endif
 190
 191 /*
 192  * Default huge tlb size for a given kernel configuration
 193  */
 194 #ifdef CONFIG_PAGE_SIZE_4KB
 195 #define PM_HUGE_MASK    PM_1M
 196 #elif defined(CONFIG_PAGE_SIZE_8KB)
 197 #define PM_HUGE_MASK    PM_4M
 198 #elif defined(CONFIG_PAGE_SIZE_16KB)
 199 #define PM_HUGE_MASK    PM_16M
 200 #elif defined(CONFIG_PAGE_SIZE_32KB)
 201 #define PM_HUGE_MASK    PM_64M
 202 #elif defined(CONFIG_PAGE_SIZE_64KB)
 203 #define PM_HUGE_MASK    PM_256M
 204 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
 205 #error Bad page size configuration for hugetlbfs!
 206 #endif
 207
 208 /*
 209  * Values used for computation of new tlb entries
 210  */
 211 #define PL_4K           12
 212 #define PL_16K          14
 213 #define PL_64K          16
 214 #define PL_256K         18
 215 #define PL_1M           20
 216 #define PL_4M           22
 217 #define PL_16M          24
 218 #define PL_64M          26
 219 #define PL_256M         28
 220
 221 /*
 222  * PageGrain bits
 223  */
 224 #define PG_RIE          (_ULCAST_(1) <<  31)
 225 #define PG_XIE          (_ULCAST_(1) <<  30)
 226 #define PG_ELPA         (_ULCAST_(1) <<  29)
 227 #define PG_ESP          (_ULCAST_(1) <<  28)
 228 #define PG_IEC          (_ULCAST_(1) <<  27)
 229
 230 /* MIPS32/64 EntryHI bit definitions */
 231 #define MIPS_ENTRYHI_EHINV      (_ULCAST_(1) << 10)
 232
 233 /*
 234  * R4x00 interrupt enable / cause bits
 235  */
 236 #define IE_SW0          (_ULCAST_(1) <<  8)
 237 #define IE_SW1          (_ULCAST_(1) <<  9)
 238 #define IE_IRQ0         (_ULCAST_(1) << 10)
 239 #define IE_IRQ1         (_ULCAST_(1) << 11)
 240 #define IE_IRQ2         (_ULCAST_(1) << 12)
 241 #define IE_IRQ3         (_ULCAST_(1) << 13)
 242 #define IE_IRQ4         (_ULCAST_(1) << 14)
 243 #define IE_IRQ5         (_ULCAST_(1) << 15)
 244
 245 /*
 246  * R4x00 interrupt cause bits
 247  */
 248 #define C_SW0           (_ULCAST_(1) <<  8)
 249 #define C_SW1           (_ULCAST_(1) <<  9)
 250 #define C_IRQ0          (_ULCAST_(1) << 10)
 251 #define C_IRQ1          (_ULCAST_(1) << 11)
 252 #define C_IRQ2          (_ULCAST_(1) << 12)
 253 #define C_IRQ3          (_ULCAST_(1) << 13)
 254 #define C_IRQ4          (_ULCAST_(1) << 14)
 255 #define C_IRQ5          (_ULCAST_(1) << 15)
 256
 257 /*
 258  * Bitfields in the R4xx0 cp0 status register
 259  */
 260 #define ST0_IE                  0x00000001
 261 #define ST0_EXL                 0x00000002
 262 #define ST0_ERL                 0x00000004
 263 #define ST0_KSU                 0x00000018
 264 #  define KSU_USER              0x00000010
 265 #  define KSU_SUPERVISOR        0x00000008
 266 #  define KSU_KERNEL            0x00000000
 267 #define ST0_UX                  0x00000020
 268 #define ST0_SX                  0x00000040
 269 #define ST0_KX                  0x00000080
 270 #define ST0_DE                  0x00010000
 271 #define ST0_CE                  0x00020000
 272
 273 /*
 274  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
 275  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
 276  * processors.
 277  */
 278 #define ST0_CO                  0x08000000
 279
 280 /*
 281  * Bitfields in the R[23]000 cp0 status register.
 282  */
 283 #define ST0_IEC                 0x00000001
 284 #define ST0_KUC                 0x00000002
 285 #define ST0_IEP                 0x00000004
 286 #define ST0_KUP                 0x00000008
 287 #define ST0_IEO                 0x00000010
 288 #define ST0_KUO                 0x00000020
 289 /* bits 6 & 7 are reserved on R[23]000 */
 290 #define ST0_ISC                 0x00010000
 291 #define ST0_SWC                 0x00020000
 292 #define ST0_CM                  0x00080000
 293
 294 /*
 295  * Bits specific to the R4640/R4650
 296  */
 297 #define ST0_UM                  (_ULCAST_(1) <<  4)
 298 #define ST0_IL                  (_ULCAST_(1) << 23)
 299 #define ST0_DL                  (_ULCAST_(1) << 24)
 300
 301 /*
 302  * Enable the MIPS MDMX and DSP ASEs
 303  */
 304 #define ST0_MX                  0x01000000
 305
 306 /*
 307  * Status register bits available in all MIPS CPUs.
 308  */
 309 #define ST0_IM                  0x0000ff00
 310 #define  STATUSB_IP0            8
 311 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
 312 #define  STATUSB_IP1            9
 313 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
 314 #define  STATUSB_IP2            10
 315 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
 316 #define  STATUSB_IP3            11
 317 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
 318 #define  STATUSB_IP4            12
 319 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
 320 #define  STATUSB_IP5            13
 321 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
 322 #define  STATUSB_IP6            14
 323 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
 324 #define  STATUSB_IP7            15
 325 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
 326 #define  STATUSB_IP8            0
 327 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
 328 #define  STATUSB_IP9            1
 329 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
 330 #define  STATUSB_IP10           2
 331 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
 332 #define  STATUSB_IP11           3
 333 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
 334 #define  STATUSB_IP12           4
 335 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
 336 #define  STATUSB_IP13           5
 337 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
 338 #define  STATUSB_IP14           6
 339 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
 340 #define  STATUSB_IP15           7
 341 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
 342 #define ST0_CH                  0x00040000
 343 #define ST0_NMI                 0x00080000
 344 #define ST0_SR                  0x00100000
 345 #define ST0_TS                  0x00200000
 346 #define ST0_BEV                 0x00400000
 347 #define ST0_RE                  0x02000000
 348 #define ST0_FR                  0x04000000
 349 #define ST0_CU                  0xf0000000
 350 #define ST0_CU0                 0x10000000
 351 #define ST0_CU1                 0x20000000
 352 #define ST0_CU2                 0x40000000
 353 #define ST0_CU3                 0x80000000
 354 #define ST0_XX                  0x80000000      /* MIPS IV naming */
 355
 356 /*
 357  * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
 358  */
 359 #define INTCTLB_IPFDC           23
 360 #define INTCTLF_IPFDC           (_ULCAST_(7) << INTCTLB_IPFDC)
 361 #define INTCTLB_IPPCI           26
 362 #define INTCTLF_IPPCI           (_ULCAST_(7) << INTCTLB_IPPCI)
 363 #define INTCTLB_IPTI            29
 364 #define INTCTLF_IPTI            (_ULCAST_(7) << INTCTLB_IPTI)
 365
 366 /*
 367  * Bitfields and bit numbers in the coprocessor 0 cause register.
 368  *
 369  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 370  */
 371 #define CAUSEB_EXCCODE          2
 372 #define CAUSEF_EXCCODE          (_ULCAST_(31)  <<  2)
 373 #define CAUSEB_IP               8
 374 #define CAUSEF_IP               (_ULCAST_(255) <<  8)
 375 #define  CAUSEB_IP0             8
 376 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
 377 #define  CAUSEB_IP1             9
 378 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
 379 #define  CAUSEB_IP2             10
 380 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
 381 #define  CAUSEB_IP3             11
 382 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
 383 #define  CAUSEB_IP4             12
 384 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
 385 #define  CAUSEB_IP5             13
 386 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
 387 #define  CAUSEB_IP6             14
 388 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
 389 #define  CAUSEB_IP7             15
 390 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
 391 #define CAUSEB_FDCI             21
 392 #define CAUSEF_FDCI             (_ULCAST_(1)   << 21)
 393 #define CAUSEB_WP               22
 394 #define CAUSEF_WP               (_ULCAST_(1)   << 22)
 395 #define CAUSEB_IV               23
 396 #define CAUSEF_IV               (_ULCAST_(1)   << 23)
 397 #define CAUSEB_PCI              26
 398 #define CAUSEF_PCI              (_ULCAST_(1)   << 26)
 399 #define CAUSEB_DC               27
 400 #define CAUSEF_DC               (_ULCAST_(1)   << 27)
 401 #define CAUSEB_CE               28
 402 #define CAUSEF_CE               (_ULCAST_(3)   << 28)
 403 #define CAUSEB_TI               30
 404 #define CAUSEF_TI               (_ULCAST_(1)   << 30)
 405 #define CAUSEB_BD               31
 406 #define CAUSEF_BD               (_ULCAST_(1)   << 31)
 407
 408 /*
 409  * Cause.ExcCode trap codes.
 410  */
 411 #define EXCCODE_INT             0       /* Interrupt pending */
 412 #define EXCCODE_MOD             1       /* TLB modified fault */
 413 #define EXCCODE_TLBL            2       /* TLB miss on load or ifetch */
 414 #define EXCCODE_TLBS            3       /* TLB miss on a store */
 415 #define EXCCODE_ADEL            4       /* Address error on a load or ifetch */
 416 #define EXCCODE_ADES            5       /* Address error on a store */
 417 #define EXCCODE_IBE             6       /* Bus error on an ifetch */
 418 #define EXCCODE_DBE             7       /* Bus error on a load or store */
 419 #define EXCCODE_SYS             8       /* System call */
 420 #define EXCCODE_BP              9       /* Breakpoint */
 421 #define EXCCODE_RI              10      /* Reserved instruction exception */
 422 #define EXCCODE_CPU             11      /* Coprocessor unusable */
 423 #define EXCCODE_OV              12      /* Arithmetic overflow */
 424 #define EXCCODE_TR              13      /* Trap instruction */
 425 #define EXCCODE_MSAFPE          14      /* MSA floating point exception */
 426 #define EXCCODE_FPE             15      /* Floating point exception */
 427 #define EXCCODE_TLBRI           19      /* TLB Read-Inhibit exception */
 428 #define EXCCODE_TLBXI           20      /* TLB Execution-Inhibit exception */
 429 #define EXCCODE_MSADIS          21      /* MSA disabled exception */
 430 #define EXCCODE_MDMX            22      /* MDMX unusable exception */
 431 #define EXCCODE_WATCH           23      /* Watch address reference */
 432 #define EXCCODE_MCHECK          24      /* Machine check */
 433 #define EXCCODE_THREAD          25      /* Thread exceptions (MT) */
 434 #define EXCCODE_DSPDIS          26      /* DSP disabled exception */
 435 #define EXCCODE_GE              27      /* Virtualized guest exception (VZ) */
 436
 437 /* Implementation specific trap codes used by MIPS cores */
 438 #define MIPS_EXCCODE_TLBPAR     16      /* TLB parity error exception */
 439
 440 /*
 441  * Bits in the coprocessor 0 config register.
 442  */
 443 /* Generic bits.  */
 444 #define CONF_CM_CACHABLE_NO_WA          0
 445 #define CONF_CM_CACHABLE_WA             1
 446 #define CONF_CM_UNCACHED                2
 447 #define CONF_CM_CACHABLE_NONCOHERENT    3
 448 #define CONF_CM_CACHABLE_CE             4
 449 #define CONF_CM_CACHABLE_COW            5
 450 #define CONF_CM_CACHABLE_CUW            6
 451 #define CONF_CM_CACHABLE_ACCELERATED    7
 452 #define CONF_CM_CMASK                   7
 453 #define CONF_BE                 (_ULCAST_(1) << 15)
 454
 455 /* Bits common to various processors.  */
 456 #define CONF_CU                 (_ULCAST_(1) <<  3)
 457 #define CONF_DB                 (_ULCAST_(1) <<  4)
 458 #define CONF_IB                 (_ULCAST_(1) <<  5)
 459 #define CONF_DC                 (_ULCAST_(7) <<  6)
 460 #define CONF_IC                 (_ULCAST_(7) <<  9)
 461 #define CONF_EB                 (_ULCAST_(1) << 13)
 462 #define CONF_EM                 (_ULCAST_(1) << 14)
 463 #define CONF_SM                 (_ULCAST_(1) << 16)
 464 #define CONF_SC                 (_ULCAST_(1) << 17)
 465 #define CONF_EW                 (_ULCAST_(3) << 18)
 466 #define CONF_EP                 (_ULCAST_(15)<< 24)
 467 #define CONF_EC                 (_ULCAST_(7) << 28)
 468 #define CONF_CM                 (_ULCAST_(1) << 31)
 469
 470 /* Bits specific to the R4xx0.  */
 471 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
 472 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
 473 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
 474
 475 /* Bits specific to the R5000.  */
 476 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
 477 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
 478
 479 /* Bits specific to the RM7000.  */
 480 #define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
 481 #define RM7K_CONF_TE            (_ULCAST_(1) << 12)
 482 #define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
 483 #define RM7K_CONF_TC            (_ULCAST_(1) << 17)
 484 #define RM7K_CONF_SI            (_ULCAST_(3) << 20)
 485 #define RM7K_CONF_SC            (_ULCAST_(1) << 31)
 486
 487 /* Bits specific to the R10000.  */
 488 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
 489 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
 490 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
 491 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
 492 #define R10K_CONF_EC            (_ULCAST_(15)<<  9)
 493 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
 494 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
 495 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
 496 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
 497 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
 498 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
 499
 500 /* Bits specific to the VR41xx.  */
 501 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
 502 #define VR41_CONF_P4K           (_ULCAST_(1) << 13)
 503 #define VR41_CONF_BP            (_ULCAST_(1) << 16)
 504 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
 505 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
 506
 507 /* Bits specific to the R30xx.  */
 508 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
 509 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
 510 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
 511 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
 512 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
 513 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
 514 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
 515 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
 516 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
 517
 518 /* Bits specific to the TX49.  */
 519 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
 520 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
 521 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
 522 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
 523
 524 /* Bits specific to the MIPS32/64 PRA.  */
 525 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
 526 #define MIPS_CONF_MT_TLB        (_ULCAST_(1) <<  7)
 527 #define MIPS_CONF_MT_FTLB       (_ULCAST_(4) <<  7)
 528 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
 529 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
 530 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
 531
 532 /*
 533  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
 534  */
 535 #define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
 536 #define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
 537 #define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
 538 #define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
 539 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
 540 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
 541 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
 542 #define MIPS_CONF1_DA_SHF       7
 543 #define MIPS_CONF1_DA_SZ        3
 544 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
 545 #define MIPS_CONF1_DL_SHF       10
 546 #define MIPS_CONF1_DL_SZ        3
 547 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
 548 #define MIPS_CONF1_DS_SHF       13
 549 #define MIPS_CONF1_DS_SZ        3
 550 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
 551 #define MIPS_CONF1_IA_SHF       16
 552 #define MIPS_CONF1_IA_SZ        3
 553 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
 554 #define MIPS_CONF1_IL_SHF       19
 555 #define MIPS_CONF1_IL_SZ        3
 556 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
 557 #define MIPS_CONF1_IS_SHF       22
 558 #define MIPS_CONF1_IS_SZ        3
 559 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
 560 #define MIPS_CONF1_TLBS_SHIFT   (25)
 561 #define MIPS_CONF1_TLBS_SIZE    (6)
 562 #define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
 563
 564 #define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
 565 #define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
 566 #define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
 567 #define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
 568 #define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
 569 #define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
 570 #define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
 571 #define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
 572
 573 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
 574 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
 575 #define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
 576 #define MIPS_CONF3_CDMM         (_ULCAST_(1) <<  3)
 577 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
 578 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
 579 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 580 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
 581 #define MIPS_CONF3_ITL          (_ULCAST_(1) <<  8)
 582 #define MIPS_CONF3_CTXTC        (_ULCAST_(1) <<  9)
 583 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
 584 #define MIPS_CONF3_DSP2P        (_ULCAST_(1) << 11)
 585 #define MIPS_CONF3_RXI          (_ULCAST_(1) << 12)
 586 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 587 #define MIPS_CONF3_ISA          (_ULCAST_(3) << 14)
 588 #define MIPS_CONF3_ISA_OE       (_ULCAST_(1) << 16)
 589 #define MIPS_CONF3_MCU          (_ULCAST_(1) << 17)
 590 #define MIPS_CONF3_MMAR         (_ULCAST_(7) << 18)
 591 #define MIPS_CONF3_IPLW         (_ULCAST_(3) << 21)
 592 #define MIPS_CONF3_VZ           (_ULCAST_(1) << 23)
 593 #define MIPS_CONF3_PW           (_ULCAST_(1) << 24)
 594 #define MIPS_CONF3_SC           (_ULCAST_(1) << 25)
 595 #define MIPS_CONF3_BI           (_ULCAST_(1) << 26)
 596 #define MIPS_CONF3_BP           (_ULCAST_(1) << 27)
 597 #define MIPS_CONF3_MSA          (_ULCAST_(1) << 28)
 598 #define MIPS_CONF3_CMGCR        (_ULCAST_(1) << 29)
 599 #define MIPS_CONF3_BPG          (_ULCAST_(1) << 30)
 600
 601 #define MIPS_CONF4_MMUSIZEEXT_SHIFT     (0)
 602 #define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
 603 #define MIPS_CONF4_FTLBSETS_SHIFT       (0)
 604 #define MIPS_CONF4_FTLBSETS     (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
 605 #define MIPS_CONF4_FTLBWAYS_SHIFT       (4)
 606 #define MIPS_CONF4_FTLBWAYS     (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
 607 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT   (8)
 608 /* bits 10:8 in FTLB-only configurations */
 609 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 610 /* bits 12:8 in VTLB-FTLB only configurations */
 611 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 612 #define MIPS_CONF4_MMUEXTDEF    (_ULCAST_(3) << 14)
 613 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 614 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT        (_ULCAST_(2) << 14)
 615 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT        (_ULCAST_(3) << 14)
 616 #define MIPS_CONF4_KSCREXIST    (_ULCAST_(255) << 16)
 617 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT    (24)
 618 #define MIPS_CONF4_VTLBSIZEEXT  (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
 619 #define MIPS_CONF4_AE           (_ULCAST_(1) << 28)
 620 #define MIPS_CONF4_IE           (_ULCAST_(3) << 29)
 621 #define MIPS_CONF4_TLBINV       (_ULCAST_(2) << 29)
 622
 623 #define MIPS_CONF5_NF           (_ULCAST_(1) << 0)
 624 #define MIPS_CONF5_UFR          (_ULCAST_(1) << 2)
 625 #define MIPS_CONF5_MRP          (_ULCAST_(1) << 3)
 626 #define MIPS_CONF5_LLB          (_ULCAST_(1) << 4)
 627 #define MIPS_CONF5_MVH          (_ULCAST_(1) << 5)
 628 #define MIPS_CONF5_VP           (_ULCAST_(1) << 7)
 629 #define MIPS_CONF5_FRE          (_ULCAST_(1) << 8)
 630 #define MIPS_CONF5_UFE          (_ULCAST_(1) << 9)
 631 #define MIPS_CONF5_MSAEN        (_ULCAST_(1) << 27)
 632 #define MIPS_CONF5_EVA          (_ULCAST_(1) << 28)
 633 #define MIPS_CONF5_CV           (_ULCAST_(1) << 29)
 634 #define MIPS_CONF5_K            (_ULCAST_(1) << 30)
 635
 636 #define MIPS_CONF6_SYND         (_ULCAST_(1) << 13)
 637 /* proAptiv FTLB on/off bit */
 638 #define MIPS_CONF6_FTLBEN       (_ULCAST_(1) << 15)
 639 /* FTLB probability bits */
 640 #define MIPS_CONF6_FTLBP_SHIFT  (16)
 641
 642 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
 643
 644 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
 645
 646 #define MIPS_CONF7_IAR          (_ULCAST_(1) << 10)
 647 #define MIPS_CONF7_AR           (_ULCAST_(1) << 16)
 648 /* FTLB probability bits for R6 */
 649 #define MIPS_CONF7_FTLBP_SHIFT  (18)
 650
 651 /* MAAR bit definitions */
 652 #define MIPS_MAAR_ADDR          ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
 653 #define MIPS_MAAR_ADDR_SHIFT    12
 654 #define MIPS_MAAR_S             (_ULCAST_(1) << 1)
 655 #define MIPS_MAAR_V             (_ULCAST_(1) << 0)
 656
 657 /* CMGCRBase bit definitions */
 658 #define MIPS_CMGCRB_BASE        11
 659 #define MIPS_CMGCRF_BASE        (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
 660
 661 /*
 662  * Bits in the MIPS32 Memory Segmentation registers.
 663  */
 664 #define MIPS_SEGCFG_PA_SHIFT    9
 665 #define MIPS_SEGCFG_PA          (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
 666 #define MIPS_SEGCFG_AM_SHIFT    4
 667 #define MIPS_SEGCFG_AM          (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
 668 #define MIPS_SEGCFG_EU_SHIFT    3
 669 #define MIPS_SEGCFG_EU          (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
 670 #define MIPS_SEGCFG_C_SHIFT     0
 671 #define MIPS_SEGCFG_C           (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
 672
 673 #define MIPS_SEGCFG_UUSK        _ULCAST_(7)
 674 #define MIPS_SEGCFG_USK         _ULCAST_(5)
 675 #define MIPS_SEGCFG_MUSUK       _ULCAST_(4)
 676 #define MIPS_SEGCFG_MUSK        _ULCAST_(3)
 677 #define MIPS_SEGCFG_MSK         _ULCAST_(2)
 678 #define MIPS_SEGCFG_MK          _ULCAST_(1)
 679 #define MIPS_SEGCFG_UK          _ULCAST_(0)
 680
 681 #define MIPS_PWFIELD_GDI_SHIFT  24
 682 #define MIPS_PWFIELD_GDI_MASK   0x3f000000
 683 #define MIPS_PWFIELD_UDI_SHIFT  18
 684 #define MIPS_PWFIELD_UDI_MASK   0x00fc0000
 685 #define MIPS_PWFIELD_MDI_SHIFT  12
 686 #define MIPS_PWFIELD_MDI_MASK   0x0003f000
 687 #define MIPS_PWFIELD_PTI_SHIFT  6
 688 #define MIPS_PWFIELD_PTI_MASK   0x00000fc0
 689 #define MIPS_PWFIELD_PTEI_SHIFT 0
 690 #define MIPS_PWFIELD_PTEI_MASK  0x0000003f
 691
 692 #define MIPS_PWSIZE_GDW_SHIFT   24
 693 #define MIPS_PWSIZE_GDW_MASK    0x3f000000
 694 #define MIPS_PWSIZE_UDW_SHIFT   18
 695 #define MIPS_PWSIZE_UDW_MASK    0x00fc0000
 696 #define MIPS_PWSIZE_MDW_SHIFT   12
 697 #define MIPS_PWSIZE_MDW_MASK    0x0003f000
 698 #define MIPS_PWSIZE_PTW_SHIFT   6
 699 #define MIPS_PWSIZE_PTW_MASK    0x00000fc0
 700 #define MIPS_PWSIZE_PTEW_SHIFT  0
 701 #define MIPS_PWSIZE_PTEW_MASK   0x0000003f
 702
 703 #define MIPS_PWCTL_PWEN_SHIFT   31
 704 #define MIPS_PWCTL_PWEN_MASK    0x80000000
 705 #define MIPS_PWCTL_DPH_SHIFT    7
 706 #define MIPS_PWCTL_DPH_MASK     0x00000080
 707 #define MIPS_PWCTL_HUGEPG_SHIFT 6
 708 #define MIPS_PWCTL_HUGEPG_MASK  0x00000060
 709 #define MIPS_PWCTL_PSN_SHIFT    0
 710 #define MIPS_PWCTL_PSN_MASK     0x0000003f
 711
 712 /* CDMMBase register bit definitions */
 713 #define MIPS_CDMMBASE_SIZE_SHIFT 0
 714 #define MIPS_CDMMBASE_SIZE      (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
 715 #define MIPS_CDMMBASE_CI        (_ULCAST_(1) << 9)
 716 #define MIPS_CDMMBASE_EN        (_ULCAST_(1) << 10)
 717 #define MIPS_CDMMBASE_ADDR_SHIFT 11
 718 #define MIPS_CDMMBASE_ADDR_START 15
 719
 720 /*
 721  * Bitfields in the TX39 family CP0 Configuration Register 3
 722  */
 723 #define TX39_CONF_ICS_SHIFT     19
 724 #define TX39_CONF_ICS_MASK      0x00380000
 725 #define TX39_CONF_ICS_1KB       0x00000000
 726 #define TX39_CONF_ICS_2KB       0x00080000
 727 #define TX39_CONF_ICS_4KB       0x00100000
 728 #define TX39_CONF_ICS_8KB       0x00180000
 729 #define TX39_CONF_ICS_16KB      0x00200000
 730
 731 #define TX39_CONF_DCS_SHIFT     16
 732 #define TX39_CONF_DCS_MASK      0x00070000
 733 #define TX39_CONF_DCS_1KB       0x00000000
 734 #define TX39_CONF_DCS_2KB       0x00010000
 735 #define TX39_CONF_DCS_4KB       0x00020000
 736 #define TX39_CONF_DCS_8KB       0x00030000
 737 #define TX39_CONF_DCS_16KB      0x00040000
 738
 739 #define TX39_CONF_CWFON         0x00004000
 740 #define TX39_CONF_WBON          0x00002000
 741 #define TX39_CONF_RF_SHIFT      10
 742 #define TX39_CONF_RF_MASK       0x00000c00
 743 #define TX39_CONF_DOZE          0x00000200
 744 #define TX39_CONF_HALT          0x00000100
 745 #define TX39_CONF_LOCK          0x00000080
 746 #define TX39_CONF_ICE           0x00000020
 747 #define TX39_CONF_DCE           0x00000010
 748 #define TX39_CONF_IRSIZE_SHIFT  2
 749 #define TX39_CONF_IRSIZE_MASK   0x0000000c
 750 #define TX39_CONF_DRSIZE_SHIFT  0
 751 #define TX39_CONF_DRSIZE_MASK   0x00000003
 752
 753 /*
 754  * Interesting Bits in the R10K CP0 Branch Diagnostic Register
 755  */
 756 /* Disable Branch Target Address Cache */
 757 #define R10K_DIAG_D_BTAC        (_ULCAST_(1) << 27)
 758 /* Enable Branch Prediction Global History */
 759 #define R10K_DIAG_E_GHIST       (_ULCAST_(1) << 26)
 760 /* Disable Branch Return Cache */
 761 #define R10K_DIAG_D_BRC         (_ULCAST_(1) << 22)
 762
 763 /*
 764  * Coprocessor 1 (FPU) register names
 765  */
 766 #define CP1_REVISION    $0
 767 #define CP1_UFR         $1
 768 #define CP1_UNFR        $4
 769 #define CP1_FCCR        $25
 770 #define CP1_FEXR        $26
 771 #define CP1_FENR        $28
 772 #define CP1_STATUS      $31
 773
 774
 775 /*
 776  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
 777  */
 778 #define MIPS_FPIR_S             (_ULCAST_(1) << 16)
 779 #define MIPS_FPIR_D             (_ULCAST_(1) << 17)
 780 #define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
 781 #define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
 782 #define MIPS_FPIR_W             (_ULCAST_(1) << 20)
 783 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
 784 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
 785 #define MIPS_FPIR_HAS2008       (_ULCAST_(1) << 23)
 786 #define MIPS_FPIR_UFRP          (_ULCAST_(1) << 28)
 787 #define MIPS_FPIR_FREP          (_ULCAST_(1) << 29)
 788
 789 /*
 790  * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
 791  */
 792 #define MIPS_FCCR_CONDX_S       0
 793 #define MIPS_FCCR_CONDX         (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
 794 #define MIPS_FCCR_COND0_S       0
 795 #define MIPS_FCCR_COND0         (_ULCAST_(1) << MIPS_FCCR_COND0_S)
 796 #define MIPS_FCCR_COND1_S       1
 797 #define MIPS_FCCR_COND1         (_ULCAST_(1) << MIPS_FCCR_COND1_S)
 798 #define MIPS_FCCR_COND2_S       2
 799 #define MIPS_FCCR_COND2         (_ULCAST_(1) << MIPS_FCCR_COND2_S)
 800 #define MIPS_FCCR_COND3_S       3
 801 #define MIPS_FCCR_COND3         (_ULCAST_(1) << MIPS_FCCR_COND3_S)
 802 #define MIPS_FCCR_COND4_S       4
 803 #define MIPS_FCCR_COND4         (_ULCAST_(1) << MIPS_FCCR_COND4_S)
 804 #define MIPS_FCCR_COND5_S       5
 805 #define MIPS_FCCR_COND5         (_ULCAST_(1) << MIPS_FCCR_COND5_S)
 806 #define MIPS_FCCR_COND6_S       6
 807 #define MIPS_FCCR_COND6         (_ULCAST_(1) << MIPS_FCCR_COND6_S)
 808 #define MIPS_FCCR_COND7_S       7
 809 #define MIPS_FCCR_COND7         (_ULCAST_(1) << MIPS_FCCR_COND7_S)
 810
 811 /*
 812  * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
 813  */
 814 #define MIPS_FENR_FS_S          2
 815 #define MIPS_FENR_FS            (_ULCAST_(1) << MIPS_FENR_FS_S)
 816
 817 /*
 818  * FPU Status Register Values
 819  */
 820 #define FPU_CSR_COND_S  23                                      /* $fcc0 */
 821 #define FPU_CSR_COND    (_ULCAST_(1) << FPU_CSR_COND_S)
 822
 823 #define FPU_CSR_FS_S    24              /* flush denormalised results to 0 */
 824 #define FPU_CSR_FS      (_ULCAST_(1) << FPU_CSR_FS_S)
 825
 826 #define FPU_CSR_CONDX_S 25                                      /* $fcc[7:1] */
 827 #define FPU_CSR_CONDX   (_ULCAST_(127) << FPU_CSR_CONDX_S)
 828 #define FPU_CSR_COND1_S 25                                      /* $fcc1 */
 829 #define FPU_CSR_COND1   (_ULCAST_(1) << FPU_CSR_COND1_S)
 830 #define FPU_CSR_COND2_S 26                                      /* $fcc2 */
 831 #define FPU_CSR_COND2   (_ULCAST_(1) << FPU_CSR_COND2_S)
 832 #define FPU_CSR_COND3_S 27                                      /* $fcc3 */
 833 #define FPU_CSR_COND3   (_ULCAST_(1) << FPU_CSR_COND3_S)
 834 #define FPU_CSR_COND4_S 28                                      /* $fcc4 */
 835 #define FPU_CSR_COND4   (_ULCAST_(1) << FPU_CSR_COND4_S)
 836 #define FPU_CSR_COND5_S 29                                      /* $fcc5 */
 837 #define FPU_CSR_COND5   (_ULCAST_(1) << FPU_CSR_COND5_S)
 838 #define FPU_CSR_COND6_S 30                                      /* $fcc6 */
 839 #define FPU_CSR_COND6   (_ULCAST_(1) << FPU_CSR_COND6_S)
 840 #define FPU_CSR_COND7_S 31                                      /* $fcc7 */
 841 #define FPU_CSR_COND7   (_ULCAST_(1) << FPU_CSR_COND7_S)
 842
 843 /*
 844  * Bits 22:20 of the FPU Status Register will be read as 0,
 845  * and should be written as zero.
 846  */
 847 #define FPU_CSR_RSVD    (_ULCAST_(7) << 20)
 848
 849 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
 850 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
 851
 852 /*
 853  * X the exception cause indicator
 854  * E the exception enable
 855  * S the sticky/flag bit
 856 */
 857 #define FPU_CSR_ALL_X   0x0003f000
 858 #define FPU_CSR_UNI_X   0x00020000
 859 #define FPU_CSR_INV_X   0x00010000
 860 #define FPU_CSR_DIV_X   0x00008000
 861 #define FPU_CSR_OVF_X   0x00004000
 862 #define FPU_CSR_UDF_X   0x00002000
 863 #define FPU_CSR_INE_X   0x00001000
 864
 865 #define FPU_CSR_ALL_E   0x00000f80
 866 #define FPU_CSR_INV_E   0x00000800
 867 #define FPU_CSR_DIV_E   0x00000400
 868 #define FPU_CSR_OVF_E   0x00000200
 869 #define FPU_CSR_UDF_E   0x00000100
 870 #define FPU_CSR_INE_E   0x00000080
 871
 872 #define FPU_CSR_ALL_S   0x0000007c
 873 #define FPU_CSR_INV_S   0x00000040
 874 #define FPU_CSR_DIV_S   0x00000020
 875 #define FPU_CSR_OVF_S   0x00000010
 876 #define FPU_CSR_UDF_S   0x00000008
 877 #define FPU_CSR_INE_S   0x00000004
 878
 879 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
 880 #define FPU_CSR_RM      0x00000003
 881 #define FPU_CSR_RN      0x0     /* nearest */
 882 #define FPU_CSR_RZ      0x1     /* towards zero */
 883 #define FPU_CSR_RU      0x2     /* towards +Infinity */
 884 #define FPU_CSR_RD      0x3     /* towards -Infinity */
 885
 886
 887 #ifndef __ASSEMBLY__
 888
 889 /*
 890  * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
 891  */
 892 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
 893     defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
 894 #define get_isa16_mode(x)               ((x) & 0x1)
 895 #define msk_isa16_mode(x)               ((x) & ~0x1)
 896 #define set_isa16_mode(x)               do { (x) |= 0x1; } while(0)
 897 #else
 898 #define get_isa16_mode(x)               0
 899 #define msk_isa16_mode(x)               (x)
 900 #define set_isa16_mode(x)               do { } while(0)
 901 #endif
 902
 903 /*
 904  * microMIPS instructions can be 16-bit or 32-bit in length. This
 905  * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
 906  */
 907 static inline int mm_insn_16bit(u16 insn)
 908 {
 909         u16 opcode = (insn >> 10) & 0x7;
 910
 911         return (opcode >= 1 && opcode <= 3) ? 1 : 0;
 912 }
 913
 914 /*
 915  * TLB Invalidate Flush
 916  */
 917 static inline void tlbinvf(void)
 918 {
 919         __asm__ __volatile__(
 920                 ".set push\n\t"
 921                 ".set noreorder\n\t"
 922                 ".word 0x42000004\n\t" /* tlbinvf */
 923                 ".set pop");
 924 }
 925
 926
 927 /*
 928  * Functions to access the R10000 performance counters.  These are basically
 929  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
 930  * performance counter number encoded into bits 1 ... 5 of the instruction.
 931  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
 932  * disassembler these will look like an access to sel 0 or 1.
 933  */
 934 #define read_r10k_perf_cntr(counter)                            \
 935 ({                                                              \
 936         unsigned int __res;                                     \
 937         __asm__ __volatile__(                                   \
 938         "mfpc\t%0, %1"                                          \
 939         : "=r" (__res)                                          \
 940         : "i" (counter));                                       \
 941                                                                 \
 942         __res;                                                  \
 943 })
 944
 945 #define write_r10k_perf_cntr(counter,val)                       \
 946 do {                                                            \
 947         __asm__ __volatile__(                                   \
 948         "mtpc\t%0, %1"                                          \
 949         :                                                       \
 950         : "r" (val), "i" (counter));                            \
 951 } while (0)
 952
 953 #define read_r10k_perf_event(counter)                           \
 954 ({                                                              \
 955         unsigned int __res;                                     \
 956         __asm__ __volatile__(                                   \
 957         "mfps\t%0, %1"                                          \
 958         : "=r" (__res)                                          \
 959         : "i" (counter));                                       \
 960                                                                 \
 961         __res;                                                  \
 962 })
 963
 964 #define write_r10k_perf_cntl(counter,val)                       \
 965 do {                                                            \
 966         __asm__ __volatile__(                                   \
 967         "mtps\t%0, %1"                                          \
 968         :                                                       \
 969         : "r" (val), "i" (counter));                            \
 970 } while (0)
 971
 972
 973 /*
 974  * Macros to access the system control coprocessor
 975  */
 976
 977 #define __read_32bit_c0_register(source, sel)                           \
 978 ({ unsigned int __res;                                                  \
 979         if (sel == 0)                                                   \
 980                 __asm__ __volatile__(                                   \
 981                         "mfc0\t%0, " #source "\n\t"                     \
 982                         : "=r" (__res));                                \
 983         else                                                            \
 984                 __asm__ __volatile__(                                   \
 985                         ".set\tmips32\n\t"                              \
 986                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
 987                         ".set\tmips0\n\t"                               \
 988                         : "=r" (__res));                                \
 989         __res;                                                          \
 990 })
 991
 992 #define __read_64bit_c0_register(source, sel)                           \
 993 ({ unsigned long long __res;                                            \
 994         if (sizeof(unsigned long) == 4)                                 \
 995                 __res = __read_64bit_c0_split(source, sel);             \
 996         else if (sel == 0)                                              \
 997                 __asm__ __volatile__(                                   \
 998                         ".set\tmips3\n\t"                               \
 999                         "dmfc0\t%0, " #source "\n\t"                    \
1000                         ".set\tmips0"                                   \
1001                         : "=r" (__res));                                \
1002         else                                                            \
1003                 __asm__ __volatile__(                                   \
1004                         ".set\tmips64\n\t"                              \
1005                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
1006                         ".set\tmips0"                                   \
1007                         : "=r" (__res));                                \
1008         __res;                                                          \
1009 })
1010
1011 #define __write_32bit_c0_register(register, sel, value)                 \
1012 do {                                                                    \
1013         if (sel == 0)                                                   \
1014                 __asm__ __volatile__(                                   \
1015                         "mtc0\t%z0, " #register "\n\t"                  \
1016                         : : "Jr" ((unsigned int)(value)));              \
1017         else                                                            \
1018                 __asm__ __volatile__(                                   \
1019                         ".set\tmips32\n\t"                              \
1020                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
1021                         ".set\tmips0"                                   \
1022                         : : "Jr" ((unsigned int)(value)));              \
1023 } while (0)
1024
1025 #define __write_64bit_c0_register(register, sel, value)                 \
1026 do {                                                                    \
1027         if (sizeof(unsigned long) == 4)                                 \
1028                 __write_64bit_c0_split(register, sel, value);           \
1029         else if (sel == 0)                                              \
1030                 __asm__ __volatile__(                                   \
1031                         ".set\tmips3\n\t"                               \
1032                         "dmtc0\t%z0, " #register "\n\t"                 \
1033                         ".set\tmips0"                                   \
1034                         : : "Jr" (value));                              \
1035         else                                                            \
1036                 __asm__ __volatile__(                                   \
1037                         ".set\tmips64\n\t"                              \
1038                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
1039                         ".set\tmips0"                                   \
1040                         : : "Jr" (value));                              \
1041 } while (0)
1042
1043 #define __read_ulong_c0_register(reg, sel)                              \
1044         ((sizeof(unsigned long) == 4) ?                                 \
1045         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
1046         (unsigned long) __read_64bit_c0_register(reg, sel))
1047
1048 #define __write_ulong_c0_register(reg, sel, val)                        \
1049 do {                                                                    \
1050         if (sizeof(unsigned long) == 4)                                 \
1051                 __write_32bit_c0_register(reg, sel, val);               \
1052         else                                                            \
1053                 __write_64bit_c0_register(reg, sel, val);               \
1054 } while (0)
1055
1056 /*
1057  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1058  */
1059 #define __read_32bit_c0_ctrl_register(source)                           \
1060 ({ unsigned int __res;                                                  \
1061         __asm__ __volatile__(                                           \
1062                 "cfc0\t%0, " #source "\n\t"                             \
1063                 : "=r" (__res));                                        \
1064         __res;                                                          \
1065 })
1066
1067 #define __write_32bit_c0_ctrl_register(register, value)                 \
1068 do {                                                                    \
1069         __asm__ __volatile__(                                           \
1070                 "ctc0\t%z0, " #register "\n\t"                          \
1071                 : : "Jr" ((unsigned int)(value)));                      \
1072 } while (0)
1073
1074 /*
1075  * These versions are only needed for systems with more than 38 bits of
1076  * physical address space running the 32-bit kernel.  That's none atm :-)
1077  */
1078 #define __read_64bit_c0_split(source, sel)                              \
1079 ({                                                                      \
1080         unsigned long long __val;                                       \
1081         unsigned long __flags;                                          \
1082                                                                         \
1083         local_irq_save(__flags);                                        \
1084         if (sel == 0)                                                   \
1085                 __asm__ __volatile__(                                   \
1086                         ".set\tmips64\n\t"                              \
1087                         "dmfc0\t%M0, " #source "\n\t"                   \
1088                         "dsll\t%L0, %M0, 32\n\t"                        \
1089                         "dsra\t%M0, %M0, 32\n\t"                        \
1090                         "dsra\t%L0, %L0, 32\n\t"                        \
1091                         ".set\tmips0"                                   \
1092                         : "=r" (__val));                                \
1093         else                                                            \
1094                 __asm__ __volatile__(                                   \
1095                         ".set\tmips64\n\t"                              \
1096                         "dmfc0\t%M0, " #source ", " #sel "\n\t"         \
1097                         "dsll\t%L0, %M0, 32\n\t"                        \
1098                         "dsra\t%M0, %M0, 32\n\t"                        \
1099                         "dsra\t%L0, %L0, 32\n\t"                        \
1100                         ".set\tmips0"                                   \
1101                         : "=r" (__val));                                \
1102         local_irq_restore(__flags);                                     \
1103                                                                         \
1104         __val;                                                          \
1105 })
1106
1107 #define __write_64bit_c0_split(source, sel, val)                        \
1108 do {                                                                    \
1109         unsigned long __flags;                                          \
1110                                                                         \
1111         local_irq_save(__flags);                                        \
1112         if (sel == 0)                                                   \
1113                 __asm__ __volatile__(                                   \
1114                         ".set\tmips64\n\t"                              \
1115                         "dsll\t%L0, %L0, 32\n\t"                        \
1116                         "dsrl\t%L0, %L0, 32\n\t"                        \
1117                         "dsll\t%M0, %M0, 32\n\t"                        \
1118                         "or\t%L0, %L0, %M0\n\t"                         \
1119                         "dmtc0\t%L0, " #source "\n\t"                   \
1120                         ".set\tmips0"                                   \
1121                         : : "r" (val));                                 \
1122         else                                                            \
1123                 __asm__ __volatile__(                                   \
1124                         ".set\tmips64\n\t"                              \
1125                         "dsll\t%L0, %L0, 32\n\t"                        \
1126                         "dsrl\t%L0, %L0, 32\n\t"                        \
1127                         "dsll\t%M0, %M0, 32\n\t"                        \
1128                         "or\t%L0, %L0, %M0\n\t"                         \
1129                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
1130                         ".set\tmips0"                                   \
1131                         : : "r" (val));                                 \
1132         local_irq_restore(__flags);                                     \
1133 } while (0)
1134
1135 #define __readx_32bit_c0_register(source)                               \
1136 ({                                                                      \
1137         unsigned int __res;                                             \
1138                                                                         \
1139         __asm__ __volatile__(                                           \
1140         "       .set    push                                    \n"     \
1141         "       .set    noat                                    \n"     \
1142         "       .set    mips32r2                                \n"     \
1143         "       .insn                                           \n"     \
1144         "       # mfhc0 $1, %1                                  \n"     \
1145         "       .word   (0x40410000 | ((%1 & 0x1f) << 11))      \n"     \
1146         "       move    %0, $1                                  \n"     \
1147         "       .set    pop                                     \n"     \
1148         : "=r" (__res)                                                  \
1149         : "i" (source));                                                \
1150         __res;                                                          \
1151 })
1152
1153 #define __writex_32bit_c0_register(register, value)                     \
1154 do {                                                                    \
1155         __asm__ __volatile__(                                           \
1156         "       .set    push                                    \n"     \
1157         "       .set    noat                                    \n"     \
1158         "       .set    mips32r2                                \n"     \
1159         "       move    $1, %0                                  \n"     \
1160         "       # mthc0 $1, %1                                  \n"     \
1161         "       .insn                                           \n"     \
1162         "       .word   (0x40c10000 | ((%1 & 0x1f) << 11))      \n"     \
1163         "       .set    pop                                     \n"     \
1164         :                                                               \
1165         : "r" (value), "i" (register));                                 \
1166 } while (0)
1167
1168 #define read_c0_index()         __read_32bit_c0_register($0, 0)
1169 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
1170
1171 #define read_c0_random()        __read_32bit_c0_register($1, 0)
1172 #define write_c0_random(val)    __write_32bit_c0_register($1, 0, val)
1173
1174 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
1175 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
1176
1177 #define readx_c0_entrylo0()     __readx_32bit_c0_register(2)
1178 #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
1179
1180 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
1181 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
1182
1183 #define readx_c0_entrylo1()     __readx_32bit_c0_register(3)
1184 #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
1185
1186 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
1187 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
1188
1189 #define read_c0_context()       __read_ulong_c0_register($4, 0)
1190 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
1191
1192 #define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
1193 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1194
1195 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
1196 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
1197
1198 #define read_c0_pagegrain()     __read_32bit_c0_register($5, 1)
1199 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1200
1201 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
1202 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
1203
1204 #define read_c0_info()          __read_32bit_c0_register($7, 0)
1205
1206 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
1207 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
1208
1209 #define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
1210 #define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
1211
1212 #define read_c0_count()         __read_32bit_c0_register($9, 0)
1213 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
1214
1215 #define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
1216 #define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
1217
1218 #define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
1219 #define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
1220
1221 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
1222 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
1223
1224 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
1225 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
1226
1227 #define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
1228 #define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
1229
1230 #define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
1231 #define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
1232
1233 #define read_c0_status()        __read_32bit_c0_register($12, 0)
1234
1235 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
1236
1237 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
1238 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
1239
1240 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
1241 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
1242
1243 #define read_c0_prid()          __read_32bit_c0_register($15, 0)
1244
1245 #define read_c0_cmgcrbase()     __read_ulong_c0_register($15, 3)
1246
1247 #define read_c0_config()        __read_32bit_c0_register($16, 0)
1248 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
1249 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
1250 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
1251 #define read_c0_config4()       __read_32bit_c0_register($16, 4)
1252 #define read_c0_config5()       __read_32bit_c0_register($16, 5)
1253 #define read_c0_config6()       __read_32bit_c0_register($16, 6)
1254 #define read_c0_config7()       __read_32bit_c0_register($16, 7)
1255 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
1256 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
1257 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
1258 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
1259 #define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
1260 #define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
1261 #define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
1262 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
1263
1264 #define read_c0_lladdr()        __read_ulong_c0_register($17, 0)
1265 #define write_c0_lladdr(val)    __write_ulong_c0_register($17, 0, val)
1266 #define read_c0_maar()          __read_ulong_c0_register($17, 1)
1267 #define write_c0_maar(val)      __write_ulong_c0_register($17, 1, val)
1268 #define read_c0_maari()         __read_32bit_c0_register($17, 2)
1269 #define write_c0_maari(val)     __write_32bit_c0_register($17, 2, val)
1270
1271 /*
1272  * The WatchLo register.  There may be up to 8 of them.
1273  */
1274 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
1275 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
1276 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
1277 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
1278 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
1279 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
1280 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
1281 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
1282 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
1283 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
1284 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
1285 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
1286 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
1287 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
1288 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
1289 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
1290
1291 /*
1292  * The WatchHi register.  There may be up to 8 of them.
1293  */
1294 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
1295 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
1296 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
1297 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
1298 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
1299 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
1300 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
1301 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
1302
1303 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
1304 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
1305 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
1306 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
1307 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
1308 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
1309 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
1310 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
1311
1312 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
1313 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
1314
1315 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
1316 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1317
1318 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
1319 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1320
1321 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
1322 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
1323
1324 /* R10K CP0 Branch Diagnostic register is 64bits wide */
1325 #define read_c0_r10k_diag()     __read_64bit_c0_register($22, 0)
1326 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1327
1328 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
1329 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
1330
1331 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
1332 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
1333
1334 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
1335 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
1336
1337 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
1338 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
1339
1340 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
1341 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
1342
1343 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
1344 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
1345
1346 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
1347 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
1348
1349 /*
1350  * MIPS32 / MIPS64 performance counters
1351  */
1352 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
1353 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1354 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
1355 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1356 #define read_c0_perfcntr0_64()  __read_64bit_c0_register($25, 1)
1357 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1358 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
1359 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1360 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
1361 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1362 #define read_c0_perfcntr1_64()  __read_64bit_c0_register($25, 3)
1363 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1364 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
1365 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1366 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
1367 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1368 #define read_c0_perfcntr2_64()  __read_64bit_c0_register($25, 5)
1369 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1370 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
1371 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1372 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
1373 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1374 #define read_c0_perfcntr3_64()  __read_64bit_c0_register($25, 7)
1375 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1376
1377 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
1378 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
1379
1380 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
1381 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1382
1383 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
1384
1385 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
1386 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1387
1388 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
1389 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
1390
1391 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
1392 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
1393
1394 #define read_c0_ddatalo()       __read_32bit_c0_register($28, 3)
1395 #define write_c0_ddatalo(val)   __write_32bit_c0_register($28, 3, val)
1396
1397 #define read_c0_staglo()        __read_32bit_c0_register($28, 4)
1398 #define write_c0_staglo(val)    __write_32bit_c0_register($28, 4, val)
1399
1400 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
1401 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
1402
1403 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
1404 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
1405
1406 /* MIPSR2 */
1407 #define read_c0_hwrena()        __read_32bit_c0_register($7, 0)
1408 #define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
1409
1410 #define read_c0_intctl()        __read_32bit_c0_register($12, 1)
1411 #define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
1412
1413 #define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
1414 #define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
1415
1416 #define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
1417 #define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
1418
1419 #define read_c0_ebase()         __read_32bit_c0_register($15, 1)
1420 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
1421
1422 #define read_c0_cdmmbase()      __read_ulong_c0_register($15, 2)
1423 #define write_c0_cdmmbase(val)  __write_ulong_c0_register($15, 2, val)
1424
1425 /* MIPSR3 */
1426 #define read_c0_segctl0()       __read_32bit_c0_register($5, 2)
1427 #define write_c0_segctl0(val)   __write_32bit_c0_register($5, 2, val)
1428
1429 #define read_c0_segctl1()       __read_32bit_c0_register($5, 3)
1430 #define write_c0_segctl1(val)   __write_32bit_c0_register($5, 3, val)
1431
1432 #define read_c0_segctl2()       __read_32bit_c0_register($5, 4)
1433 #define write_c0_segctl2(val)   __write_32bit_c0_register($5, 4, val)
1434
1435 /* Hardware Page Table Walker */
1436 #define read_c0_pwbase()        __read_ulong_c0_register($5, 5)
1437 #define write_c0_pwbase(val)    __write_ulong_c0_register($5, 5, val)
1438
1439 #define read_c0_pwfield()       __read_ulong_c0_register($5, 6)
1440 #define write_c0_pwfield(val)   __write_ulong_c0_register($5, 6, val)
1441
1442 #define read_c0_pwsize()        __read_ulong_c0_register($5, 7)
1443 #define write_c0_pwsize(val)    __write_ulong_c0_register($5, 7, val)
1444
1445 #define read_c0_pwctl()         __read_32bit_c0_register($6, 6)
1446 #define write_c0_pwctl(val)     __write_32bit_c0_register($6, 6, val)
1447
1448 /* Cavium OCTEON (cnMIPS) */
1449 #define read_c0_cvmcount()      __read_ulong_c0_register($9, 6)
1450 #define write_c0_cvmcount(val)  __write_ulong_c0_register($9, 6, val)
1451
1452 #define read_c0_cvmctl()        __read_64bit_c0_register($9, 7)
1453 #define write_c0_cvmctl(val)    __write_64bit_c0_register($9, 7, val)
1454
1455 #define read_c0_cvmmemctl()     __read_64bit_c0_register($11, 7)
1456 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1457 /*
1458  * The cacheerr registers are not standardized.  On OCTEON, they are
1459  * 64 bits wide.
1460  */
1461 #define read_octeon_c0_icacheerr()      __read_64bit_c0_register($27, 0)
1462 #define write_octeon_c0_icacheerr(val)  __write_64bit_c0_register($27, 0, val)
1463
1464 #define read_octeon_c0_dcacheerr()      __read_64bit_c0_register($27, 1)
1465 #define write_octeon_c0_dcacheerr(val)  __write_64bit_c0_register($27, 1, val)
1466
1467 /* BMIPS3300 */
1468 #define read_c0_brcm_config_0()         __read_32bit_c0_register($22, 0)
1469 #define write_c0_brcm_config_0(val)     __write_32bit_c0_register($22, 0, val)
1470
1471 #define read_c0_brcm_bus_pll()          __read_32bit_c0_register($22, 4)
1472 #define write_c0_brcm_bus_pll(val)      __write_32bit_c0_register($22, 4, val)
1473
1474 #define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
1475 #define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
1476
1477 /* BMIPS43xx */
1478 #define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
1479 #define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
1480
1481 #define read_c0_brcm_cmt_ctrl()         __read_32bit_c0_register($22, 2)
1482 #define write_c0_brcm_cmt_ctrl(val)     __write_32bit_c0_register($22, 2, val)
1483
1484 #define read_c0_brcm_cmt_local()        __read_32bit_c0_register($22, 3)
1485 #define write_c0_brcm_cmt_local(val)    __write_32bit_c0_register($22, 3, val)
1486
1487 #define read_c0_brcm_config_1()         __read_32bit_c0_register($22, 5)
1488 #define write_c0_brcm_config_1(val)     __write_32bit_c0_register($22, 5, val)
1489
1490 #define read_c0_brcm_cbr()              __read_32bit_c0_register($22, 6)
1491 #define write_c0_brcm_cbr(val)          __write_32bit_c0_register($22, 6, val)
1492
1493 /* BMIPS5000 */
1494 #define read_c0_brcm_config()           __read_32bit_c0_register($22, 0)
1495 #define write_c0_brcm_config(val)       __write_32bit_c0_register($22, 0, val)
1496
1497 #define read_c0_brcm_mode()             __read_32bit_c0_register($22, 1)
1498 #define write_c0_brcm_mode(val)         __write_32bit_c0_register($22, 1, val)
1499
1500 #define read_c0_brcm_action()           __read_32bit_c0_register($22, 2)
1501 #define write_c0_brcm_action(val)       __write_32bit_c0_register($22, 2, val)
1502
1503 #define read_c0_brcm_edsp()             __read_32bit_c0_register($22, 3)
1504 #define write_c0_brcm_edsp(val)         __write_32bit_c0_register($22, 3, val)
1505
1506 #define read_c0_brcm_bootvec()          __read_32bit_c0_register($22, 4)
1507 #define write_c0_brcm_bootvec(val)      __write_32bit_c0_register($22, 4, val)
1508
1509 #define read_c0_brcm_sleepcount()       __read_32bit_c0_register($22, 7)
1510 #define write_c0_brcm_sleepcount(val)   __write_32bit_c0_register($22, 7, val)
1511
1512 /*
1513  * Macros to access the floating point coprocessor control registers
1514  */
1515 #define _read_32bit_cp1_register(source, gas_hardfloat)                 \
1516 ({                                                                      \
1517         unsigned int __res;                                             \
1518                                                                         \
1519         __asm__ __volatile__(                                           \
1520         "       .set    push                                    \n"     \
1521         "       .set    reorder                                 \n"     \
1522         "       # gas fails to assemble cfc1 for some archs,    \n"     \
1523         "       # like Octeon.                                  \n"     \
1524         "       .set    mips1                                   \n"     \
1525         "       "STR(gas_hardfloat)"                            \n"     \
1526         "       cfc1    %0,"STR(source)"                        \n"     \
1527         "       .set    pop                                     \n"     \
1528         : "=r" (__res));                                                \
1529         __res;                                                          \
1530 })
1531
1532 #define _write_32bit_cp1_register(dest, val, gas_hardfloat)             \
1533 do {                                                                    \
1534         __asm__ __volatile__(                                           \
1535         "       .set    push                                    \n"     \
1536         "       .set    reorder                                 \n"     \
1537         "       "STR(gas_hardfloat)"                            \n"     \
1538         "       ctc1    %0,"STR(dest)"                          \n"     \
1539         "       .set    pop                                     \n"     \
1540         : : "r" (val));                                                 \
1541 } while (0)
1542
1543 #ifdef GAS_HAS_SET_HARDFLOAT
1544 #define read_32bit_cp1_register(source)                                 \
1545         _read_32bit_cp1_register(source, .set hardfloat)
1546 #define write_32bit_cp1_register(dest, val)                             \
1547         _write_32bit_cp1_register(dest, val, .set hardfloat)
1548 #else
1549 #define read_32bit_cp1_register(source)                                 \
1550         _read_32bit_cp1_register(source, )
1551 #define write_32bit_cp1_register(dest, val)                             \
1552         _write_32bit_cp1_register(dest, val, )
1553 #endif
1554
1555 #ifdef HAVE_AS_DSP
1556 #define rddsp(mask)                                                     \
1557 ({                                                                      \
1558         unsigned int __dspctl;                                          \
1559                                                                         \
1560         __asm__ __volatile__(                                           \
1561         "       .set push                                       \n"     \
1562         "       .set dsp                                        \n"     \
1563         "       rddsp   %0, %x1                                 \n"     \
1564         "       .set pop                                        \n"     \
1565         : "=r" (__dspctl)                                               \
1566         : "i" (mask));                                                  \
1567         __dspctl;                                                       \
1568 })
1569
1570 #define wrdsp(val, mask)                                                \
1571 do {                                                                    \
1572         __asm__ __volatile__(                                           \
1573         "       .set push                                       \n"     \
1574         "       .set dsp                                        \n"     \
1575         "       wrdsp   %0, %x1                                 \n"     \
1576         "       .set pop                                        \n"     \
1577         :                                                               \
1578         : "r" (val), "i" (mask));                                       \
1579 } while (0)
1580
1581 #define mflo0()                                                         \
1582 ({                                                                      \
1583         long mflo0;                                                     \
1584         __asm__(                                                        \
1585         "       .set push                                       \n"     \
1586         "       .set dsp                                        \n"     \
1587         "       mflo %0, $ac0                                   \n"     \
1588         "       .set pop                                        \n"     \
1589         : "=r" (mflo0));                                                \
1590         mflo0;                                                          \
1591 })
1592
1593 #define mflo1()                                                         \
1594 ({                                                                      \
1595         long mflo1;                                                     \
1596         __asm__(                                                        \
1597         "       .set push                                       \n"     \
1598         "       .set dsp                                        \n"     \
1599         "       mflo %0, $ac1                                   \n"     \
1600         "       .set pop                                        \n"     \
1601         : "=r" (mflo1));                                                \
1602         mflo1;                                                          \
1603 })
1604
1605 #define mflo2()                                                         \
1606 ({                                                                      \
1607         long mflo2;                                                     \
1608         __asm__(                                                        \
1609         "       .set push                                       \n"     \
1610         "       .set dsp                                        \n"     \
1611         "       mflo %0, $ac2                                   \n"     \
1612         "       .set pop                                        \n"     \
1613         : "=r" (mflo2));                                                \
1614         mflo2;                                                          \
1615 })
1616
1617 #define mflo3()                                                         \
1618 ({                                                                      \
1619         long mflo3;                                                     \
1620         __asm__(                                                        \
1621         "       .set push                                       \n"     \
1622         "       .set dsp                                        \n"     \
1623         "       mflo %0, $ac3                                   \n"     \
1624         "       .set pop                                        \n"     \
1625         : "=r" (mflo3));                                                \
1626         mflo3;                                                          \
1627 })
1628
1629 #define mfhi0()                                                         \
1630 ({                                                                      \
1631         long mfhi0;                                                     \
1632         __asm__(                                                        \
1633         "       .set push                                       \n"     \
1634         "       .set dsp                                        \n"     \
1635         "       mfhi %0, $ac0                                   \n"     \
1636         "       .set pop                                        \n"     \
1637         : "=r" (mfhi0));                                                \
1638         mfhi0;                                                          \
1639 })
1640
1641 #define mfhi1()                                                         \
1642 ({                                                                      \
1643         long mfhi1;                                                     \
1644         __asm__(                                                        \
1645         "       .set push                                       \n"     \
1646         "       .set dsp                                        \n"     \
1647         "       mfhi %0, $ac1                                   \n"     \
1648         "       .set pop                                        \n"     \
1649         : "=r" (mfhi1));                                                \
1650         mfhi1;                                                          \
1651 })
1652
1653 #define mfhi2()                                                         \
1654 ({                                                                      \
1655         long mfhi2;                                                     \
1656         __asm__(                                                        \
1657         "       .set push                                       \n"     \
1658         "       .set dsp                                        \n"     \
1659         "       mfhi %0, $ac2                                   \n"     \
1660         "       .set pop                                        \n"     \
1661         : "=r" (mfhi2));                                                \
1662         mfhi2;                                                          \
1663 })
1664
1665 #define mfhi3()                                                         \
1666 ({                                                                      \
1667         long mfhi3;                                                     \
1668         __asm__(                                                        \
1669         "       .set push                                       \n"     \
1670         "       .set dsp                                        \n"     \
1671         "       mfhi %0, $ac3                                   \n"     \
1672         "       .set pop                                        \n"     \
1673         : "=r" (mfhi3));                                                \
1674         mfhi3;                                                          \
1675 })
1676
1677
1678 #define mtlo0(x)                                                        \
1679 ({                                                                      \
1680         __asm__(                                                        \
1681         "       .set push                                       \n"     \
1682         "       .set dsp                                        \n"     \
1683         "       mtlo %0, $ac0                                   \n"     \
1684         "       .set pop                                        \n"     \
1685         :                                                               \
1686         : "r" (x));                                                     \
1687 })
1688
1689 #define mtlo1(x)                                                        \
1690 ({                                                                      \
1691         __asm__(                                                        \
1692         "       .set push                                       \n"     \
1693         "       .set dsp                                        \n"     \
1694         "       mtlo %0, $ac1                                   \n"     \
1695         "       .set pop                                        \n"     \
1696         :                                                               \
1697         : "r" (x));                                                     \
1698 })
1699
1700 #define mtlo2(x)                                                        \
1701 ({                                                                      \
1702         __asm__(                                                        \
1703         "       .set push                                       \n"     \
1704         "       .set dsp                                        \n"     \
1705         "       mtlo %0, $ac2                                   \n"     \
1706         "       .set pop                                        \n"     \
1707         :                                                               \
1708         : "r" (x));                                                     \
1709 })
1710
1711 #define mtlo3(x)                                                        \
1712 ({                                                                      \
1713         __asm__(                                                        \
1714         "       .set push                                       \n"     \
1715         "       .set dsp                                        \n"     \
1716         "       mtlo %0, $ac3                                   \n"     \
1717         "       .set pop                                        \n"     \
1718         :                                                               \
1719         : "r" (x));                                                     \
1720 })
1721
1722 #define mthi0(x)                                                        \
1723 ({                                                                      \
1724         __asm__(                                                        \
1725         "       .set push                                       \n"     \
1726         "       .set dsp                                        \n"     \
1727         "       mthi %0, $ac0                                   \n"     \
1728         "       .set pop                                        \n"     \
1729         :                                                               \
1730         : "r" (x));                                                     \
1731 })
1732
1733 #define mthi1(x)                                                        \
1734 ({                                                                      \
1735         __asm__(                                                        \
1736         "       .set push                                       \n"     \
1737         "       .set dsp                                        \n"     \
1738         "       mthi %0, $ac1                                   \n"     \
1739         "       .set pop                                        \n"     \
1740         :                                                               \
1741         : "r" (x));                                                     \
1742 })
1743
1744 #define mthi2(x)                                                        \
1745 ({                                                                      \
1746         __asm__(                                                        \
1747         "       .set push                                       \n"     \
1748         "       .set dsp                                        \n"     \
1749         "       mthi %0, $ac2                                   \n"     \
1750         "       .set pop                                        \n"     \
1751         :                                                               \
1752         : "r" (x));                                                     \
1753 })
1754
1755 #define mthi3(x)                                                        \
1756 ({                                                                      \
1757         __asm__(                                                        \
1758         "       .set push                                       \n"     \
1759         "       .set dsp                                        \n"     \
1760         "       mthi %0, $ac3                                   \n"     \
1761         "       .set pop                                        \n"     \
1762         :                                                               \
1763         : "r" (x));                                                     \
1764 })
1765
1766 #else
1767
1768 #ifdef CONFIG_CPU_MICROMIPS
1769 #define rddsp(mask)                                                     \
1770 ({                                                                      \
1771         unsigned int __res;                                             \
1772                                                                         \
1773         __asm__ __volatile__(                                           \
1774         "       .set    push                                    \n"     \
1775         "       .set    noat                                    \n"     \
1776         "       # rddsp $1, %x1                                 \n"     \
1777         "       .hword  ((0x0020067c | (%x1 << 14)) >> 16)      \n"     \
1778         "       .hword  ((0x0020067c | (%x1 << 14)) & 0xffff)   \n"     \
1779         "       move    %0, $1                                  \n"     \
1780         "       .set    pop                                     \n"     \
1781         : "=r" (__res)                                                  \
1782         : "i" (mask));                                                  \
1783         __res;                                                          \
1784 })
1785
1786 #define wrdsp(val, mask)                                                \
1787 do {                                                                    \
1788         __asm__ __volatile__(                                           \
1789         "       .set    push                                    \n"     \
1790         "       .set    noat                                    \n"     \
1791         "       move    $1, %0                                  \n"     \
1792         "       # wrdsp $1, %x1                                 \n"     \
1793         "       .hword  ((0x0020167c | (%x1 << 14)) >> 16)      \n"     \
1794         "       .hword  ((0x0020167c | (%x1 << 14)) & 0xffff)   \n"     \
1795         "       .set    pop                                     \n"     \
1796         :                                                               \
1797         : "r" (val), "i" (mask));                                       \
1798 } while (0)
1799
1800 #define _umips_dsp_mfxxx(ins)                                           \
1801 ({                                                                      \
1802         unsigned long __treg;                                           \
1803                                                                         \
1804         __asm__ __volatile__(                                           \
1805         "       .set    push                                    \n"     \
1806         "       .set    noat                                    \n"     \
1807         "       .hword  0x0001                                  \n"     \
1808         "       .hword  %x1                                     \n"     \
1809         "       move    %0, $1                                  \n"     \
1810         "       .set    pop                                     \n"     \
1811         : "=r" (__treg)                                                 \
1812         : "i" (ins));                                                   \
1813         __treg;                                                         \
1814 })
1815
1816 #define _umips_dsp_mtxxx(val, ins)                                      \
1817 do {                                                                    \
1818         __asm__ __volatile__(                                           \
1819         "       .set    push                                    \n"     \
1820         "       .set    noat                                    \n"     \
1821         "       move    $1, %0                                  \n"     \
1822         "       .hword  0x0001                                  \n"     \
1823         "       .hword  %x1                                     \n"     \
1824         "       .set    pop                                     \n"     \
1825         :                                                               \
1826         : "r" (val), "i" (ins));                                        \
1827 } while (0)
1828
1829 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
1830 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
1831
1832 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
1833 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
1834
1835 #define mflo0() _umips_dsp_mflo(0)
1836 #define mflo1() _umips_dsp_mflo(1)
1837 #define mflo2() _umips_dsp_mflo(2)
1838 #define mflo3() _umips_dsp_mflo(3)
1839
1840 #define mfhi0() _umips_dsp_mfhi(0)
1841 #define mfhi1() _umips_dsp_mfhi(1)
1842 #define mfhi2() _umips_dsp_mfhi(2)
1843 #define mfhi3() _umips_dsp_mfhi(3)
1844
1845 #define mtlo0(x) _umips_dsp_mtlo(x, 0)
1846 #define mtlo1(x) _umips_dsp_mtlo(x, 1)
1847 #define mtlo2(x) _umips_dsp_mtlo(x, 2)
1848 #define mtlo3(x) _umips_dsp_mtlo(x, 3)
1849
1850 #define mthi0(x) _umips_dsp_mthi(x, 0)
1851 #define mthi1(x) _umips_dsp_mthi(x, 1)
1852 #define mthi2(x) _umips_dsp_mthi(x, 2)
1853 #define mthi3(x) _umips_dsp_mthi(x, 3)
1854
1855 #else  /* !CONFIG_CPU_MICROMIPS */
1856 #define rddsp(mask)                                                     \
1857 ({                                                                      \
1858         unsigned int __res;                                             \
1859                                                                         \
1860         __asm__ __volatile__(                                           \
1861         "       .set    push                            \n"             \
1862         "       .set    noat                            \n"             \
1863         "       # rddsp $1, %x1                         \n"             \
1864         "       .word   0x7c000cb8 | (%x1 << 16)        \n"             \
1865         "       move    %0, $1                          \n"             \
1866         "       .set    pop                             \n"             \
1867         : "=r" (__res)                                                  \
1868         : "i" (mask));                                                  \
1869         __res;                                                          \
1870 })
1871
1872 #define wrdsp(val, mask)                                                \
1873 do {                                                                    \
1874         __asm__ __volatile__(                                           \
1875         "       .set    push                                    \n"     \
1876         "       .set    noat                                    \n"     \
1877         "       move    $1, %0                                  \n"     \
1878         "       # wrdsp $1, %x1                                 \n"     \
1879         "       .word   0x7c2004f8 | (%x1 << 11)                \n"     \
1880         "       .set    pop                                     \n"     \
1881         :                                                               \
1882         : "r" (val), "i" (mask));                                       \
1883 } while (0)
1884
1885 #define _dsp_mfxxx(ins)                                                 \
1886 ({                                                                      \
1887         unsigned long __treg;                                           \
1888                                                                         \
1889         __asm__ __volatile__(                                           \
1890         "       .set    push                                    \n"     \
1891         "       .set    noat                                    \n"     \
1892         "       .word   (0x00000810 | %1)                       \n"     \
1893         "       move    %0, $1                                  \n"     \
1894         "       .set    pop                                     \n"     \
1895         : "=r" (__treg)                                                 \
1896         : "i" (ins));                                                   \
1897         __treg;                                                         \
1898 })
1899
1900 #define _dsp_mtxxx(val, ins)                                            \
1901 do {                                                                    \
1902         __asm__ __volatile__(                                           \
1903         "       .set    push                                    \n"     \
1904         "       .set    noat                                    \n"     \
1905         "       move    $1, %0                                  \n"     \
1906         "       .word   (0x00200011 | %1)                       \n"     \
1907         "       .set    pop                                     \n"     \
1908         :                                                               \
1909         : "r" (val), "i" (ins));                                        \
1910 } while (0)
1911
1912 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
1913 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
1914
1915 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
1916 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1917
1918 #define mflo0() _dsp_mflo(0)
1919 #define mflo1() _dsp_mflo(1)
1920 #define mflo2() _dsp_mflo(2)
1921 #define mflo3() _dsp_mflo(3)
1922
1923 #define mfhi0() _dsp_mfhi(0)
1924 #define mfhi1() _dsp_mfhi(1)
1925 #define mfhi2() _dsp_mfhi(2)
1926 #define mfhi3() _dsp_mfhi(3)
1927
1928 #define mtlo0(x) _dsp_mtlo(x, 0)
1929 #define mtlo1(x) _dsp_mtlo(x, 1)
1930 #define mtlo2(x) _dsp_mtlo(x, 2)
1931 #define mtlo3(x) _dsp_mtlo(x, 3)
1932
1933 #define mthi0(x) _dsp_mthi(x, 0)
1934 #define mthi1(x) _dsp_mthi(x, 1)
1935 #define mthi2(x) _dsp_mthi(x, 2)
1936 #define mthi3(x) _dsp_mthi(x, 3)
1937
1938 #endif /* CONFIG_CPU_MICROMIPS */
1939 #endif
1940
1941 /*
1942  * TLB operations.
1943  *
1944  * It is responsibility of the caller to take care of any TLB hazards.
1945  */
1946 static inline void tlb_probe(void)
1947 {
1948         __asm__ __volatile__(
1949                 ".set noreorder\n\t"
1950                 "tlbp\n\t"
1951                 ".set reorder");
1952 }
1953
1954 static inline void tlb_read(void)
1955 {
1956 #if MIPS34K_MISSED_ITLB_WAR
1957         int res = 0;
1958
1959         __asm__ __volatile__(
1960         "       .set    push                                    \n"
1961         "       .set    noreorder                               \n"
1962         "       .set    noat                                    \n"
1963         "       .set    mips32r2                                \n"
1964         "       .word   0x41610001              # dvpe $1       \n"
1965         "       move    %0, $1                                  \n"
1966         "       ehb                                             \n"
1967         "       .set    pop                                     \n"
1968         : "=r" (res));
1969
1970         instruction_hazard();
1971 #endif
1972
1973         __asm__ __volatile__(
1974                 ".set noreorder\n\t"
1975                 "tlbr\n\t"
1976                 ".set reorder");
1977
1978 #if MIPS34K_MISSED_ITLB_WAR
1979         if ((res & _ULCAST_(1)))
1980                 __asm__ __volatile__(
1981                 "       .set    push                            \n"
1982                 "       .set    noreorder                       \n"
1983                 "       .set    noat                            \n"
1984                 "       .set    mips32r2                        \n"
1985                 "       .word   0x41600021      # evpe          \n"
1986                 "       ehb                                     \n"
1987                 "       .set    pop                             \n");
1988 #endif
1989 }
1990
1991 static inline void tlb_write_indexed(void)
1992 {
1993         __asm__ __volatile__(
1994                 ".set noreorder\n\t"
1995                 "tlbwi\n\t"
1996                 ".set reorder");
1997 }
1998
1999 static inline void tlb_write_random(void)
2000 {
2001         __asm__ __volatile__(
2002                 ".set noreorder\n\t"
2003                 "tlbwr\n\t"
2004                 ".set reorder");
2005 }
2006
2007 /*
2008  * Manipulate bits in a c0 register.
2009  */
2010 #define __BUILD_SET_C0(name)                                    \
2011 static inline unsigned int                                      \
2012 set_c0_##name(unsigned int set)                                 \
2013 {                                                               \
2014         unsigned int res, new;                                  \
2015                                                                 \
2016         res = read_c0_##name();                                 \
2017         new = res | set;                                        \
2018         write_c0_##name(new);                                   \
2019                                                                 \
2020         return res;                                             \
2021 }                                                               \
2022                                                                 \
2023 static inline unsigned int                                      \
2024 clear_c0_##name(unsigned int clear)                             \
2025 {                                                               \
2026         unsigned int res, new;                                  \
2027                                                                 \
2028         res = read_c0_##name();                                 \
2029         new = res & ~clear;                                     \
2030         write_c0_##name(new);                                   \
2031                                                                 \
2032         return res;                                             \
2033 }                                                               \
2034                                                                 \
2035 static inline unsigned int                                      \
2036 change_c0_##name(unsigned int change, unsigned int val)         \
2037 {                                                               \
2038         unsigned int res, new;                                  \
2039                                                                 \
2040         res = read_c0_##name();                                 \
2041         new = res & ~change;                                    \
2042         new |= (val & change);                                  \
2043         write_c0_##name(new);                                   \
2044                                                                 \
2045         return res;                                             \
2046 }
2047
2048 __BUILD_SET_C0(status)
2049 __BUILD_SET_C0(cause)
2050 __BUILD_SET_C0(config)
2051 __BUILD_SET_C0(config5)
2052 __BUILD_SET_C0(intcontrol)
2053 __BUILD_SET_C0(intctl)
2054 __BUILD_SET_C0(srsmap)
2055 __BUILD_SET_C0(pagegrain)
2056 __BUILD_SET_C0(brcm_config_0)
2057 __BUILD_SET_C0(brcm_bus_pll)
2058 __BUILD_SET_C0(brcm_reset)
2059 __BUILD_SET_C0(brcm_cmt_intr)
2060 __BUILD_SET_C0(brcm_cmt_ctrl)
2061 __BUILD_SET_C0(brcm_config)
2062 __BUILD_SET_C0(brcm_mode)
2063
2064 /*
2065  * Return low 10 bits of ebase.
2066  * Note that under KVM (MIPSVZ) this returns vcpu id.
2067  */
2068 static inline unsigned int get_ebase_cpunum(void)
2069 {
2070         return read_c0_ebase() & 0x3ff;
2071 }
2072
2073 #endif /* !__ASSEMBLY__ */
2074
2075 #endif /* _ASM_MIPSREGS_H */