2 * Switch a MMU context.
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
9 * Copyright (C) 1999 Silicon Graphics, Inc.
11 #ifndef _ASM_MMU_CONTEXT_H
12 #define _ASM_MMU_CONTEXT_H
14 #include <linux/errno.h>
15 #include <linux/sched.h>
16 #include <linux/smp.h>
17 #include <linux/slab.h>
18 #include <asm/cacheflush.h>
19 #include <asm/hazards.h>
20 #include <asm/tlbflush.h>
21 #ifdef CONFIG_MIPS_MT_SMTC
22 #include <asm/mipsmtregs.h>
25 #include <asm-generic/mm_hooks.h>
27 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
29 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \
30 tlbmiss_handler_setup_pgd((unsigned long)(pgd))
32 extern void tlbmiss_handler_setup_pgd(unsigned long pgd);
34 #define TLBMISS_HANDLER_SETUP() \
36 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \
37 write_c0_xcontext((unsigned long) smp_processor_id() << 51); \
40 #else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/
43 * For the fast tlb miss handlers, we keep a per cpu array of pointers
44 * to the current pgd for each processor. Also, the proc. id is stuffed
45 * into the context register.
47 extern unsigned long pgd_current[];
49 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \
50 pgd_current[smp_processor_id()] = (unsigned long)(pgd)
53 #define TLBMISS_HANDLER_SETUP() \
54 write_c0_context((unsigned long) smp_processor_id() << 25); \
55 back_to_back_c0_hazard(); \
56 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
59 #define TLBMISS_HANDLER_SETUP() \
60 write_c0_context((unsigned long) smp_processor_id() << 26); \
61 back_to_back_c0_hazard(); \
62 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
64 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
65 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
68 #define ASID_MASK 0xfc0
70 #elif defined(CONFIG_CPU_R8000)
73 #define ASID_MASK 0xff0
75 #elif defined(CONFIG_MIPS_MT_SMTC)
78 extern unsigned long smtc_asid_mask;
79 #define ASID_MASK (smtc_asid_mask)
80 #define HW_ASID_MASK 0xff
81 /* End SMTC/34K debug hack */
82 #else /* FIXME: not correct for R6000 */
85 #define ASID_MASK 0xff
89 #define cpu_context(cpu, mm) ((mm)->context.asid[cpu])
90 #define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK)
91 #define asid_cache(cpu) (cpu_data[cpu].asid_cache)
93 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
98 * All unused by hardware upper bits will be considered
99 * as a software asid extension.
101 #define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1)))
102 #define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)
104 #ifndef CONFIG_MIPS_MT_SMTC
105 /* Normal, classic MIPS get_new_mmu_context */
107 get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
109 unsigned long asid = asid_cache(cpu);
111 if (! ((asid += ASID_INC) & ASID_MASK) ) {
112 if (cpu_has_vtag_icache)
114 local_flush_tlb_all(); /* start new asid cycle */
115 if (!asid) /* fix version if needed */
116 asid = ASID_FIRST_VERSION;
118 cpu_context(cpu, mm) = asid_cache(cpu) = asid;
121 #else /* CONFIG_MIPS_MT_SMTC */
123 #define get_new_mmu_context(mm, cpu) smtc_get_new_mmu_context((mm), (cpu))
125 #endif /* CONFIG_MIPS_MT_SMTC */
128 * Initialize the context related info for a new mm_struct
132 init_new_context(struct task_struct *tsk, struct mm_struct *mm)
136 for_each_online_cpu(i)
137 cpu_context(i, mm) = 0;
142 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
143 struct task_struct *tsk)
145 unsigned int cpu = smp_processor_id();
147 #ifdef CONFIG_MIPS_MT_SMTC
148 unsigned long oldasid;
149 unsigned long mtflags;
150 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
151 local_irq_save(flags);
154 local_irq_save(flags);
155 #endif /* CONFIG_MIPS_MT_SMTC */
157 /* Check if our ASID is of an older version and thus invalid */
158 if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK)
159 get_new_mmu_context(next, cpu);
160 #ifdef CONFIG_MIPS_MT_SMTC
162 * If the EntryHi ASID being replaced happens to be
163 * the value flagged at ASID recycling time as having
164 * an extended life, clear the bit showing it being
165 * in use by this "CPU", and if that's the last bit,
166 * free up the ASID value for use and flush any old
167 * instances of it from the TLB.
169 oldasid = (read_c0_entryhi() & ASID_MASK);
170 if(smtc_live_asid[mytlb][oldasid]) {
171 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
172 if(smtc_live_asid[mytlb][oldasid] == 0)
173 smtc_flush_tlb_asid(oldasid);
176 * Tread softly on EntryHi, and so long as we support
177 * having ASID_MASK smaller than the hardware maximum,
178 * make sure no "soft" bits become "hard"...
180 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
181 cpu_asid(cpu, next));
182 ehb(); /* Make sure it propagates to TCStatus */
185 write_c0_entryhi(cpu_asid(cpu, next));
186 #endif /* CONFIG_MIPS_MT_SMTC */
187 TLBMISS_HANDLER_SETUP_PGD(next->pgd);
190 * Mark current->active_mm as not "active" anymore.
191 * We don't want to mislead possible IPI tlb flush routines.
193 cpumask_clear_cpu(cpu, mm_cpumask(prev));
194 cpumask_set_cpu(cpu, mm_cpumask(next));
196 local_irq_restore(flags);
200 * Destroy context related info for an mm_struct that is about
203 static inline void destroy_context(struct mm_struct *mm)
207 #define deactivate_mm(tsk, mm) do { } while (0)
210 * After we have set current->mm to a new value, this activates
211 * the context for the new mm so we see the new mappings.
214 activate_mm(struct mm_struct *prev, struct mm_struct *next)
217 unsigned int cpu = smp_processor_id();
219 #ifdef CONFIG_MIPS_MT_SMTC
220 unsigned long oldasid;
221 unsigned long mtflags;
222 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
223 #endif /* CONFIG_MIPS_MT_SMTC */
225 local_irq_save(flags);
227 /* Unconditionally get a new ASID. */
228 get_new_mmu_context(next, cpu);
230 #ifdef CONFIG_MIPS_MT_SMTC
231 /* See comments for similar code above */
233 oldasid = read_c0_entryhi() & ASID_MASK;
234 if(smtc_live_asid[mytlb][oldasid]) {
235 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
236 if(smtc_live_asid[mytlb][oldasid] == 0)
237 smtc_flush_tlb_asid(oldasid);
239 /* See comments for similar code above */
240 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
241 cpu_asid(cpu, next));
242 ehb(); /* Make sure it propagates to TCStatus */
245 write_c0_entryhi(cpu_asid(cpu, next));
246 #endif /* CONFIG_MIPS_MT_SMTC */
247 TLBMISS_HANDLER_SETUP_PGD(next->pgd);
249 /* mark mmu ownership change */
250 cpumask_clear_cpu(cpu, mm_cpumask(prev));
251 cpumask_set_cpu(cpu, mm_cpumask(next));
253 local_irq_restore(flags);
257 * If mm is currently active_mm, we can't really drop it. Instead,
258 * we will get a new one for it.
261 drop_mmu_context(struct mm_struct *mm, unsigned cpu)
264 #ifdef CONFIG_MIPS_MT_SMTC
265 unsigned long oldasid;
266 /* Can't use spinlock because called from TLB flush within DVPE */
267 unsigned int prevvpe;
268 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
269 #endif /* CONFIG_MIPS_MT_SMTC */
271 local_irq_save(flags);
273 if (cpumask_test_cpu(cpu, mm_cpumask(mm))) {
274 get_new_mmu_context(mm, cpu);
275 #ifdef CONFIG_MIPS_MT_SMTC
276 /* See comments for similar code above */
278 oldasid = (read_c0_entryhi() & ASID_MASK);
279 if (smtc_live_asid[mytlb][oldasid]) {
280 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
281 if(smtc_live_asid[mytlb][oldasid] == 0)
282 smtc_flush_tlb_asid(oldasid);
284 /* See comments for similar code above */
285 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK)
286 | cpu_asid(cpu, mm));
287 ehb(); /* Make sure it propagates to TCStatus */
289 #else /* not CONFIG_MIPS_MT_SMTC */
290 write_c0_entryhi(cpu_asid(cpu, mm));
291 #endif /* CONFIG_MIPS_MT_SMTC */
293 /* will get a new context next time */
294 #ifndef CONFIG_MIPS_MT_SMTC
295 cpu_context(cpu, mm) = 0;
299 /* SMTC shares the TLB (and ASIDs) across VPEs */
300 for_each_online_cpu(i) {
301 if((smtc_status & SMTC_TLB_SHARED)
302 || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))
303 cpu_context(i, mm) = 0;
305 #endif /* CONFIG_MIPS_MT_SMTC */
307 local_irq_restore(flags);
310 #endif /* _ASM_MMU_CONTEXT_H */