1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2010 Cavium Networks
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_NPEI_DEFS_H__
29 #define __CVMX_NPEI_DEFS_H__
31 #define CVMX_NPEI_BAR1_INDEXX(offset) (0x0000000000000000ull + ((offset) & 31) * 16)
32 #define CVMX_NPEI_BIST_STATUS (0x0000000000000580ull)
33 #define CVMX_NPEI_BIST_STATUS2 (0x0000000000000680ull)
34 #define CVMX_NPEI_CTL_PORT0 (0x0000000000000250ull)
35 #define CVMX_NPEI_CTL_PORT1 (0x0000000000000260ull)
36 #define CVMX_NPEI_CTL_STATUS (0x0000000000000570ull)
37 #define CVMX_NPEI_CTL_STATUS2 (0x0000000000003C00ull)
38 #define CVMX_NPEI_DATA_OUT_CNT (0x00000000000005F0ull)
39 #define CVMX_NPEI_DBG_DATA (0x0000000000000510ull)
40 #define CVMX_NPEI_DBG_SELECT (0x0000000000000500ull)
41 #define CVMX_NPEI_DMA0_INT_LEVEL (0x00000000000005C0ull)
42 #define CVMX_NPEI_DMA1_INT_LEVEL (0x00000000000005D0ull)
43 #define CVMX_NPEI_DMAX_COUNTS(offset) (0x0000000000000450ull + ((offset) & 7) * 16)
44 #define CVMX_NPEI_DMAX_DBELL(offset) (0x00000000000003B0ull + ((offset) & 7) * 16)
45 #define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) (0x0000000000000400ull + ((offset) & 7) * 16)
46 #define CVMX_NPEI_DMAX_NADDR(offset) (0x00000000000004A0ull + ((offset) & 7) * 16)
47 #define CVMX_NPEI_DMA_CNTS (0x00000000000005E0ull)
48 #define CVMX_NPEI_DMA_CONTROL (0x00000000000003A0ull)
49 #define CVMX_NPEI_DMA_PCIE_REQ_NUM (0x00000000000005B0ull)
50 #define CVMX_NPEI_DMA_STATE1 (0x00000000000006C0ull)
51 #define CVMX_NPEI_DMA_STATE1_P1 (0x0000000000000680ull)
52 #define CVMX_NPEI_DMA_STATE2 (0x00000000000006D0ull)
53 #define CVMX_NPEI_DMA_STATE2_P1 (0x0000000000000690ull)
54 #define CVMX_NPEI_DMA_STATE3_P1 (0x00000000000006A0ull)
55 #define CVMX_NPEI_DMA_STATE4_P1 (0x00000000000006B0ull)
56 #define CVMX_NPEI_DMA_STATE5_P1 (0x00000000000006C0ull)
57 #define CVMX_NPEI_INT_A_ENB (0x0000000000000560ull)
58 #define CVMX_NPEI_INT_A_ENB2 (0x0000000000003CE0ull)
59 #define CVMX_NPEI_INT_A_SUM (0x0000000000000550ull)
60 #define CVMX_NPEI_INT_ENB (0x0000000000000540ull)
61 #define CVMX_NPEI_INT_ENB2 (0x0000000000003CD0ull)
62 #define CVMX_NPEI_INT_INFO (0x0000000000000590ull)
63 #define CVMX_NPEI_INT_SUM (0x0000000000000530ull)
64 #define CVMX_NPEI_INT_SUM2 (0x0000000000003CC0ull)
65 #define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull)
66 #define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull)
67 #define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull)
68 #define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000340ull + ((offset) & 31) * 16 - 16*12)
69 #define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull)
70 #define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull)
71 #define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull)
72 #define CVMX_NPEI_MSI_ENB3 (0x0000000000003C80ull)
73 #define CVMX_NPEI_MSI_RCV0 (0x0000000000003C10ull)
74 #define CVMX_NPEI_MSI_RCV1 (0x0000000000003C20ull)
75 #define CVMX_NPEI_MSI_RCV2 (0x0000000000003C30ull)
76 #define CVMX_NPEI_MSI_RCV3 (0x0000000000003C40ull)
77 #define CVMX_NPEI_MSI_RD_MAP (0x0000000000003CA0ull)
78 #define CVMX_NPEI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
79 #define CVMX_NPEI_MSI_W1C_ENB1 (0x0000000000003D00ull)
80 #define CVMX_NPEI_MSI_W1C_ENB2 (0x0000000000003D10ull)
81 #define CVMX_NPEI_MSI_W1C_ENB3 (0x0000000000003D20ull)
82 #define CVMX_NPEI_MSI_W1S_ENB0 (0x0000000000003D30ull)
83 #define CVMX_NPEI_MSI_W1S_ENB1 (0x0000000000003D40ull)
84 #define CVMX_NPEI_MSI_W1S_ENB2 (0x0000000000003D50ull)
85 #define CVMX_NPEI_MSI_W1S_ENB3 (0x0000000000003D60ull)
86 #define CVMX_NPEI_MSI_WR_MAP (0x0000000000003C90ull)
87 #define CVMX_NPEI_PCIE_CREDIT_CNT (0x0000000000003D70ull)
88 #define CVMX_NPEI_PCIE_MSI_RCV (0x0000000000003CB0ull)
89 #define CVMX_NPEI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
90 #define CVMX_NPEI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
91 #define CVMX_NPEI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
92 #define CVMX_NPEI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
93 #define CVMX_NPEI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
94 #define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
95 #define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
96 #define CVMX_NPEI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
97 #define CVMX_NPEI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
98 #define CVMX_NPEI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
99 #define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
100 #define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
101 #define CVMX_NPEI_PKT_CNT_INT (0x0000000000001110ull)
102 #define CVMX_NPEI_PKT_CNT_INT_ENB (0x0000000000001130ull)
103 #define CVMX_NPEI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
104 #define CVMX_NPEI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
105 #define CVMX_NPEI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
106 #define CVMX_NPEI_PKT_DPADDR (0x0000000000001080ull)
107 #define CVMX_NPEI_PKT_INPUT_CONTROL (0x0000000000001150ull)
108 #define CVMX_NPEI_PKT_INSTR_ENB (0x0000000000001000ull)
109 #define CVMX_NPEI_PKT_INSTR_RD_SIZE (0x0000000000001190ull)
110 #define CVMX_NPEI_PKT_INSTR_SIZE (0x0000000000001020ull)
111 #define CVMX_NPEI_PKT_INT_LEVELS (0x0000000000001100ull)
112 #define CVMX_NPEI_PKT_IN_BP (0x00000000000006B0ull)
113 #define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
114 #define CVMX_NPEI_PKT_IN_INSTR_COUNTS (0x00000000000006A0ull)
115 #define CVMX_NPEI_PKT_IN_PCIE_PORT (0x00000000000011A0ull)
116 #define CVMX_NPEI_PKT_IPTR (0x0000000000001070ull)
117 #define CVMX_NPEI_PKT_OUTPUT_WMARK (0x0000000000001160ull)
118 #define CVMX_NPEI_PKT_OUT_BMODE (0x00000000000010D0ull)
119 #define CVMX_NPEI_PKT_OUT_ENB (0x0000000000001010ull)
120 #define CVMX_NPEI_PKT_PCIE_PORT (0x00000000000010E0ull)
121 #define CVMX_NPEI_PKT_PORT_IN_RST (0x0000000000000690ull)
122 #define CVMX_NPEI_PKT_SLIST_ES (0x0000000000001050ull)
123 #define CVMX_NPEI_PKT_SLIST_ID_SIZE (0x0000000000001180ull)
124 #define CVMX_NPEI_PKT_SLIST_NS (0x0000000000001040ull)
125 #define CVMX_NPEI_PKT_SLIST_ROR (0x0000000000001030ull)
126 #define CVMX_NPEI_PKT_TIME_INT (0x0000000000001120ull)
127 #define CVMX_NPEI_PKT_TIME_INT_ENB (0x0000000000001140ull)
128 #define CVMX_NPEI_RSL_INT_BLOCKS (0x0000000000000520ull)
129 #define CVMX_NPEI_SCRATCH_1 (0x0000000000000270ull)
130 #define CVMX_NPEI_STATE1 (0x0000000000000620ull)
131 #define CVMX_NPEI_STATE2 (0x0000000000000630ull)
132 #define CVMX_NPEI_STATE3 (0x0000000000000640ull)
133 #define CVMX_NPEI_WINDOW_CTL (0x0000000000000380ull)
134 #define CVMX_NPEI_WIN_RD_ADDR (0x0000000000000210ull)
135 #define CVMX_NPEI_WIN_RD_DATA (0x0000000000000240ull)
136 #define CVMX_NPEI_WIN_WR_ADDR (0x0000000000000200ull)
137 #define CVMX_NPEI_WIN_WR_DATA (0x0000000000000220ull)
138 #define CVMX_NPEI_WIN_WR_MASK (0x0000000000000230ull)
140 union cvmx_npei_bar1_indexx {
142 struct cvmx_npei_bar1_indexx_s {
143 uint32_t reserved_18_31:14;
144 uint32_t addr_idx:14;
149 struct cvmx_npei_bar1_indexx_s cn52xx;
150 struct cvmx_npei_bar1_indexx_s cn52xxp1;
151 struct cvmx_npei_bar1_indexx_s cn56xx;
152 struct cvmx_npei_bar1_indexx_s cn56xxp1;
155 union cvmx_npei_bist_status {
157 struct cvmx_npei_bist_status_s {
159 uint64_t reserved_60_62:3;
167 uint64_t reserved_50_52:3;
170 uint64_t reserved_36_47:12;
175 uint64_t reserved_31_31:1;
204 uint64_t reserved_2_2:1;
208 struct cvmx_npei_bist_status_cn52xx {
210 uint64_t reserved_60_62:3;
221 uint64_t reserved_48_49:2;
230 uint64_t reserved_36_39:4;
268 struct cvmx_npei_bist_status_cn52xxp1 {
269 uint64_t reserved_46_63:18;
317 struct cvmx_npei_bist_status_cn52xx cn56xx;
318 struct cvmx_npei_bist_status_cn56xxp1 {
319 uint64_t reserved_58_63:6;
381 union cvmx_npei_bist_status2 {
383 struct cvmx_npei_bist_status2_s {
384 uint64_t reserved_14_63:50;
400 struct cvmx_npei_bist_status2_s cn52xx;
401 struct cvmx_npei_bist_status2_s cn56xx;
404 union cvmx_npei_ctl_port0 {
406 struct cvmx_npei_ctl_port0_s {
407 uint64_t reserved_21_63:43;
408 uint64_t waitl_com:1;
418 uint64_t reserved_6_6:1;
425 struct cvmx_npei_ctl_port0_s cn52xx;
426 struct cvmx_npei_ctl_port0_s cn52xxp1;
427 struct cvmx_npei_ctl_port0_s cn56xx;
428 struct cvmx_npei_ctl_port0_s cn56xxp1;
431 union cvmx_npei_ctl_port1 {
433 struct cvmx_npei_ctl_port1_s {
434 uint64_t reserved_21_63:43;
435 uint64_t waitl_com:1;
445 uint64_t reserved_6_6:1;
452 struct cvmx_npei_ctl_port1_s cn52xx;
453 struct cvmx_npei_ctl_port1_s cn52xxp1;
454 struct cvmx_npei_ctl_port1_s cn56xx;
455 struct cvmx_npei_ctl_port1_s cn56xxp1;
458 union cvmx_npei_ctl_status {
460 struct cvmx_npei_ctl_status_s {
461 uint64_t reserved_44_63:20;
464 uint64_t cfg_rtry:16;
469 uint64_t host_mode:1;
472 struct cvmx_npei_ctl_status_s cn52xx;
473 struct cvmx_npei_ctl_status_cn52xxp1 {
474 uint64_t reserved_44_63:20;
477 uint64_t cfg_rtry:16;
478 uint64_t reserved_15_15:1;
481 uint64_t reserved_9_12:4;
482 uint64_t host_mode:1;
485 struct cvmx_npei_ctl_status_s cn56xx;
486 struct cvmx_npei_ctl_status_cn56xxp1 {
487 uint64_t reserved_15_63:49;
491 uint64_t host_mode:1;
496 union cvmx_npei_ctl_status2 {
498 struct cvmx_npei_ctl_status2_s {
499 uint64_t reserved_16_63:48;
511 struct cvmx_npei_ctl_status2_s cn52xx;
512 struct cvmx_npei_ctl_status2_s cn52xxp1;
513 struct cvmx_npei_ctl_status2_s cn56xx;
514 struct cvmx_npei_ctl_status2_s cn56xxp1;
517 union cvmx_npei_data_out_cnt {
519 struct cvmx_npei_data_out_cnt_s {
520 uint64_t reserved_44_63:20;
526 struct cvmx_npei_data_out_cnt_s cn52xx;
527 struct cvmx_npei_data_out_cnt_s cn52xxp1;
528 struct cvmx_npei_data_out_cnt_s cn56xx;
529 struct cvmx_npei_data_out_cnt_s cn56xxp1;
532 union cvmx_npei_dbg_data {
534 struct cvmx_npei_dbg_data_s {
535 uint64_t reserved_28_63:36;
536 uint64_t qlm0_rev_lanes:1;
537 uint64_t reserved_25_26:2;
543 struct cvmx_npei_dbg_data_cn52xx {
544 uint64_t reserved_29_63:35;
545 uint64_t qlm0_link_width:1;
546 uint64_t qlm0_rev_lanes:1;
547 uint64_t qlm1_mode:2;
553 struct cvmx_npei_dbg_data_cn52xx cn52xxp1;
554 struct cvmx_npei_dbg_data_cn56xx {
555 uint64_t reserved_29_63:35;
556 uint64_t qlm2_rev_lanes:1;
557 uint64_t qlm0_rev_lanes:1;
564 struct cvmx_npei_dbg_data_cn56xx cn56xxp1;
567 union cvmx_npei_dbg_select {
569 struct cvmx_npei_dbg_select_s {
570 uint64_t reserved_16_63:48;
573 struct cvmx_npei_dbg_select_s cn52xx;
574 struct cvmx_npei_dbg_select_s cn52xxp1;
575 struct cvmx_npei_dbg_select_s cn56xx;
576 struct cvmx_npei_dbg_select_s cn56xxp1;
579 union cvmx_npei_dmax_counts {
581 struct cvmx_npei_dmax_counts_s {
582 uint64_t reserved_39_63:25;
586 struct cvmx_npei_dmax_counts_s cn52xx;
587 struct cvmx_npei_dmax_counts_s cn52xxp1;
588 struct cvmx_npei_dmax_counts_s cn56xx;
589 struct cvmx_npei_dmax_counts_s cn56xxp1;
592 union cvmx_npei_dmax_dbell {
594 struct cvmx_npei_dmax_dbell_s {
595 uint32_t reserved_16_31:16;
598 struct cvmx_npei_dmax_dbell_s cn52xx;
599 struct cvmx_npei_dmax_dbell_s cn52xxp1;
600 struct cvmx_npei_dmax_dbell_s cn56xx;
601 struct cvmx_npei_dmax_dbell_s cn56xxp1;
604 union cvmx_npei_dmax_ibuff_saddr {
606 struct cvmx_npei_dmax_ibuff_saddr_s {
607 uint64_t reserved_37_63:27;
610 uint64_t reserved_0_6:7;
612 struct cvmx_npei_dmax_ibuff_saddr_s cn52xx;
613 struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 {
614 uint64_t reserved_36_63:28;
616 uint64_t reserved_0_6:7;
618 struct cvmx_npei_dmax_ibuff_saddr_s cn56xx;
619 struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 cn56xxp1;
622 union cvmx_npei_dmax_naddr {
624 struct cvmx_npei_dmax_naddr_s {
625 uint64_t reserved_36_63:28;
628 struct cvmx_npei_dmax_naddr_s cn52xx;
629 struct cvmx_npei_dmax_naddr_s cn52xxp1;
630 struct cvmx_npei_dmax_naddr_s cn56xx;
631 struct cvmx_npei_dmax_naddr_s cn56xxp1;
634 union cvmx_npei_dma0_int_level {
636 struct cvmx_npei_dma0_int_level_s {
640 struct cvmx_npei_dma0_int_level_s cn52xx;
641 struct cvmx_npei_dma0_int_level_s cn52xxp1;
642 struct cvmx_npei_dma0_int_level_s cn56xx;
643 struct cvmx_npei_dma0_int_level_s cn56xxp1;
646 union cvmx_npei_dma1_int_level {
648 struct cvmx_npei_dma1_int_level_s {
652 struct cvmx_npei_dma1_int_level_s cn52xx;
653 struct cvmx_npei_dma1_int_level_s cn52xxp1;
654 struct cvmx_npei_dma1_int_level_s cn56xx;
655 struct cvmx_npei_dma1_int_level_s cn56xxp1;
658 union cvmx_npei_dma_cnts {
660 struct cvmx_npei_dma_cnts_s {
664 struct cvmx_npei_dma_cnts_s cn52xx;
665 struct cvmx_npei_dma_cnts_s cn52xxp1;
666 struct cvmx_npei_dma_cnts_s cn56xx;
667 struct cvmx_npei_dma_cnts_s cn56xxp1;
670 union cvmx_npei_dma_control {
672 struct cvmx_npei_dma_control_s {
673 uint64_t reserved_40_63:24;
691 struct cvmx_npei_dma_control_s cn52xx;
692 struct cvmx_npei_dma_control_cn52xxp1 {
693 uint64_t reserved_38_63:26;
709 struct cvmx_npei_dma_control_s cn56xx;
710 struct cvmx_npei_dma_control_cn56xxp1 {
711 uint64_t reserved_39_63:25;
730 union cvmx_npei_dma_pcie_req_num {
732 struct cvmx_npei_dma_pcie_req_num_s {
734 uint64_t reserved_53_62:10;
736 uint64_t reserved_45_47:3;
738 uint64_t reserved_37_39:3;
740 uint64_t reserved_29_31:3;
742 uint64_t reserved_21_23:3;
744 uint64_t reserved_13_15:3;
746 uint64_t reserved_5_7:3;
749 struct cvmx_npei_dma_pcie_req_num_s cn52xx;
750 struct cvmx_npei_dma_pcie_req_num_s cn56xx;
753 union cvmx_npei_dma_state1 {
755 struct cvmx_npei_dma_state1_s {
756 uint64_t reserved_40_63:24;
763 struct cvmx_npei_dma_state1_s cn52xx;
766 union cvmx_npei_dma_state1_p1 {
768 struct cvmx_npei_dma_state1_p1_s {
769 uint64_t reserved_60_63:4;
781 struct cvmx_npei_dma_state1_p1_cn52xxp1 {
782 uint64_t reserved_60_63:4;
787 uint64_t reserved_25_31:7;
792 uint64_t reserved_0_4:5;
794 struct cvmx_npei_dma_state1_p1_s cn56xxp1;
797 union cvmx_npei_dma_state2 {
799 struct cvmx_npei_dma_state2_s {
800 uint64_t reserved_28_63:36;
802 uint64_t reserved_21_23:3;
804 uint64_t reserved_10_15:6;
807 struct cvmx_npei_dma_state2_s cn52xx;
810 union cvmx_npei_dma_state2_p1 {
812 struct cvmx_npei_dma_state2_p1_s {
813 uint64_t reserved_45_63:19;
820 struct cvmx_npei_dma_state2_p1_cn52xxp1 {
821 uint64_t reserved_45_63:19;
826 uint64_t reserved_0_8:9;
828 struct cvmx_npei_dma_state2_p1_s cn56xxp1;
831 union cvmx_npei_dma_state3_p1 {
833 struct cvmx_npei_dma_state3_p1_s {
834 uint64_t reserved_60_63:4;
835 uint64_t d0_drest:15;
836 uint64_t d1_drest:15;
837 uint64_t d2_drest:15;
838 uint64_t d3_drest:15;
840 struct cvmx_npei_dma_state3_p1_s cn52xxp1;
841 struct cvmx_npei_dma_state3_p1_s cn56xxp1;
844 union cvmx_npei_dma_state4_p1 {
846 struct cvmx_npei_dma_state4_p1_s {
847 uint64_t reserved_52_63:12;
848 uint64_t d0_dwest:13;
849 uint64_t d1_dwest:13;
850 uint64_t d2_dwest:13;
851 uint64_t d3_dwest:13;
853 struct cvmx_npei_dma_state4_p1_s cn52xxp1;
854 struct cvmx_npei_dma_state4_p1_s cn56xxp1;
857 union cvmx_npei_dma_state5_p1 {
859 struct cvmx_npei_dma_state5_p1_s {
860 uint64_t reserved_28_63:36;
861 uint64_t d4_drest:15;
862 uint64_t d4_dwest:13;
864 struct cvmx_npei_dma_state5_p1_s cn56xxp1;
867 union cvmx_npei_int_a_enb {
869 struct cvmx_npei_int_a_enb_s {
870 uint64_t reserved_10_63:54;
882 struct cvmx_npei_int_a_enb_s cn52xx;
883 struct cvmx_npei_int_a_enb_cn52xxp1 {
884 uint64_t reserved_2_63:62;
888 struct cvmx_npei_int_a_enb_s cn56xx;
891 union cvmx_npei_int_a_enb2 {
893 struct cvmx_npei_int_a_enb2_s {
894 uint64_t reserved_10_63:54;
906 struct cvmx_npei_int_a_enb2_s cn52xx;
907 struct cvmx_npei_int_a_enb2_cn52xxp1 {
908 uint64_t reserved_2_63:62;
912 struct cvmx_npei_int_a_enb2_s cn56xx;
915 union cvmx_npei_int_a_sum {
917 struct cvmx_npei_int_a_sum_s {
918 uint64_t reserved_10_63:54;
930 struct cvmx_npei_int_a_sum_s cn52xx;
931 struct cvmx_npei_int_a_sum_cn52xxp1 {
932 uint64_t reserved_2_63:62;
936 struct cvmx_npei_int_a_sum_s cn56xx;
939 union cvmx_npei_int_enb {
941 struct cvmx_npei_int_enb_s {
943 uint64_t reserved_62_62:1;
1007 struct cvmx_npei_int_enb_s cn52xx;
1008 struct cvmx_npei_int_enb_cn52xxp1 {
1009 uint64_t mio_inta:1;
1010 uint64_t reserved_62_62:1;
1016 uint64_t c1_up_wf:1;
1017 uint64_t c0_up_wf:1;
1018 uint64_t c1_un_wf:1;
1019 uint64_t c0_un_wf:1;
1020 uint64_t c1_un_bx:1;
1021 uint64_t c1_un_wi:1;
1022 uint64_t c1_un_b2:1;
1023 uint64_t c1_un_b1:1;
1024 uint64_t c1_un_b0:1;
1025 uint64_t c1_up_bx:1;
1026 uint64_t c1_up_wi:1;
1027 uint64_t c1_up_b2:1;
1028 uint64_t c1_up_b1:1;
1029 uint64_t c1_up_b0:1;
1030 uint64_t c0_un_bx:1;
1031 uint64_t c0_un_wi:1;
1032 uint64_t c0_un_b2:1;
1033 uint64_t c0_un_b1:1;
1034 uint64_t c0_un_b0:1;
1035 uint64_t c0_up_bx:1;
1036 uint64_t c0_up_wi:1;
1037 uint64_t c0_up_b2:1;
1038 uint64_t c0_up_b1:1;
1039 uint64_t c0_up_b0:1;
1040 uint64_t c1_hpint:1;
1047 uint64_t c0_hpint:1;
1064 uint64_t reserved_8_8:1;
1074 struct cvmx_npei_int_enb_s cn56xx;
1075 struct cvmx_npei_int_enb_cn56xxp1 {
1076 uint64_t mio_inta:1;
1077 uint64_t reserved_61_62:2;
1082 uint64_t c1_up_wf:1;
1083 uint64_t c0_up_wf:1;
1084 uint64_t c1_un_wf:1;
1085 uint64_t c0_un_wf:1;
1086 uint64_t c1_un_bx:1;
1087 uint64_t c1_un_wi:1;
1088 uint64_t c1_un_b2:1;
1089 uint64_t c1_un_b1:1;
1090 uint64_t c1_un_b0:1;
1091 uint64_t c1_up_bx:1;
1092 uint64_t c1_up_wi:1;
1093 uint64_t c1_up_b2:1;
1094 uint64_t c1_up_b1:1;
1095 uint64_t c1_up_b0:1;
1096 uint64_t c0_un_bx:1;
1097 uint64_t c0_un_wi:1;
1098 uint64_t c0_un_b2:1;
1099 uint64_t c0_un_b1:1;
1100 uint64_t c0_un_b0:1;
1101 uint64_t c0_up_bx:1;
1102 uint64_t c0_up_wi:1;
1103 uint64_t c0_up_b2:1;
1104 uint64_t c0_up_b1:1;
1105 uint64_t c0_up_b0:1;
1106 uint64_t c1_hpint:1;
1109 uint64_t reserved_29_29:1;
1111 uint64_t reserved_27_27:1;
1113 uint64_t c0_hpint:1;
1116 uint64_t reserved_22_22:1;
1118 uint64_t reserved_20_20:1;
1142 union cvmx_npei_int_enb2 {
1144 struct cvmx_npei_int_enb2_s {
1145 uint64_t reserved_62_63:2;
1151 uint64_t c1_up_wf:1;
1152 uint64_t c0_up_wf:1;
1153 uint64_t c1_un_wf:1;
1154 uint64_t c0_un_wf:1;
1155 uint64_t c1_un_bx:1;
1156 uint64_t c1_un_wi:1;
1157 uint64_t c1_un_b2:1;
1158 uint64_t c1_un_b1:1;
1159 uint64_t c1_un_b0:1;
1160 uint64_t c1_up_bx:1;
1161 uint64_t c1_up_wi:1;
1162 uint64_t c1_up_b2:1;
1163 uint64_t c1_up_b1:1;
1164 uint64_t c1_up_b0:1;
1165 uint64_t c0_un_bx:1;
1166 uint64_t c0_un_wi:1;
1167 uint64_t c0_un_b2:1;
1168 uint64_t c0_un_b1:1;
1169 uint64_t c0_un_b0:1;
1170 uint64_t c0_up_bx:1;
1171 uint64_t c0_up_wi:1;
1172 uint64_t c0_up_b2:1;
1173 uint64_t c0_up_b1:1;
1174 uint64_t c0_up_b0:1;
1175 uint64_t c1_hpint:1;
1182 uint64_t c0_hpint:1;
1209 struct cvmx_npei_int_enb2_s cn52xx;
1210 struct cvmx_npei_int_enb2_cn52xxp1 {
1211 uint64_t reserved_62_63:2;
1217 uint64_t c1_up_wf:1;
1218 uint64_t c0_up_wf:1;
1219 uint64_t c1_un_wf:1;
1220 uint64_t c0_un_wf:1;
1221 uint64_t c1_un_bx:1;
1222 uint64_t c1_un_wi:1;
1223 uint64_t c1_un_b2:1;
1224 uint64_t c1_un_b1:1;
1225 uint64_t c1_un_b0:1;
1226 uint64_t c1_up_bx:1;
1227 uint64_t c1_up_wi:1;
1228 uint64_t c1_up_b2:1;
1229 uint64_t c1_up_b1:1;
1230 uint64_t c1_up_b0:1;
1231 uint64_t c0_un_bx:1;
1232 uint64_t c0_un_wi:1;
1233 uint64_t c0_un_b2:1;
1234 uint64_t c0_un_b1:1;
1235 uint64_t c0_un_b0:1;
1236 uint64_t c0_up_bx:1;
1237 uint64_t c0_up_wi:1;
1238 uint64_t c0_up_b2:1;
1239 uint64_t c0_up_b1:1;
1240 uint64_t c0_up_b0:1;
1241 uint64_t c1_hpint:1;
1248 uint64_t c0_hpint:1;
1265 uint64_t reserved_8_8:1;
1275 struct cvmx_npei_int_enb2_s cn56xx;
1276 struct cvmx_npei_int_enb2_cn56xxp1 {
1277 uint64_t reserved_61_63:3;
1282 uint64_t c1_up_wf:1;
1283 uint64_t c0_up_wf:1;
1284 uint64_t c1_un_wf:1;
1285 uint64_t c0_un_wf:1;
1286 uint64_t c1_un_bx:1;
1287 uint64_t c1_un_wi:1;
1288 uint64_t c1_un_b2:1;
1289 uint64_t c1_un_b1:1;
1290 uint64_t c1_un_b0:1;
1291 uint64_t c1_up_bx:1;
1292 uint64_t c1_up_wi:1;
1293 uint64_t c1_up_b2:1;
1294 uint64_t c1_up_b1:1;
1295 uint64_t c1_up_b0:1;
1296 uint64_t c0_un_bx:1;
1297 uint64_t c0_un_wi:1;
1298 uint64_t c0_un_b2:1;
1299 uint64_t c0_un_b1:1;
1300 uint64_t c0_un_b0:1;
1301 uint64_t c0_up_bx:1;
1302 uint64_t c0_up_wi:1;
1303 uint64_t c0_up_b2:1;
1304 uint64_t c0_up_b1:1;
1305 uint64_t c0_up_b0:1;
1306 uint64_t c1_hpint:1;
1309 uint64_t reserved_29_29:1;
1311 uint64_t reserved_27_27:1;
1313 uint64_t c0_hpint:1;
1316 uint64_t reserved_22_22:1;
1318 uint64_t reserved_20_20:1;
1342 union cvmx_npei_int_info {
1344 struct cvmx_npei_int_info_s {
1345 uint64_t reserved_12_63:52;
1349 struct cvmx_npei_int_info_s cn52xx;
1350 struct cvmx_npei_int_info_s cn56xx;
1351 struct cvmx_npei_int_info_s cn56xxp1;
1354 union cvmx_npei_int_sum {
1356 struct cvmx_npei_int_sum_s {
1357 uint64_t mio_inta:1;
1358 uint64_t reserved_62_62:1;
1364 uint64_t c1_up_wf:1;
1365 uint64_t c0_up_wf:1;
1366 uint64_t c1_un_wf:1;
1367 uint64_t c0_un_wf:1;
1368 uint64_t c1_un_bx:1;
1369 uint64_t c1_un_wi:1;
1370 uint64_t c1_un_b2:1;
1371 uint64_t c1_un_b1:1;
1372 uint64_t c1_un_b0:1;
1373 uint64_t c1_up_bx:1;
1374 uint64_t c1_up_wi:1;
1375 uint64_t c1_up_b2:1;
1376 uint64_t c1_up_b1:1;
1377 uint64_t c1_up_b0:1;
1378 uint64_t c0_un_bx:1;
1379 uint64_t c0_un_wi:1;
1380 uint64_t c0_un_b2:1;
1381 uint64_t c0_un_b1:1;
1382 uint64_t c0_un_b0:1;
1383 uint64_t c0_up_bx:1;
1384 uint64_t c0_up_wi:1;
1385 uint64_t c0_up_b2:1;
1386 uint64_t c0_up_b1:1;
1387 uint64_t c0_up_b0:1;
1388 uint64_t c1_hpint:1;
1395 uint64_t c0_hpint:1;
1422 struct cvmx_npei_int_sum_s cn52xx;
1423 struct cvmx_npei_int_sum_cn52xxp1 {
1424 uint64_t mio_inta:1;
1425 uint64_t reserved_62_62:1;
1431 uint64_t c1_up_wf:1;
1432 uint64_t c0_up_wf:1;
1433 uint64_t c1_un_wf:1;
1434 uint64_t c0_un_wf:1;
1435 uint64_t c1_un_bx:1;
1436 uint64_t c1_un_wi:1;
1437 uint64_t c1_un_b2:1;
1438 uint64_t c1_un_b1:1;
1439 uint64_t c1_un_b0:1;
1440 uint64_t c1_up_bx:1;
1441 uint64_t c1_up_wi:1;
1442 uint64_t c1_up_b2:1;
1443 uint64_t c1_up_b1:1;
1444 uint64_t c1_up_b0:1;
1445 uint64_t c0_un_bx:1;
1446 uint64_t c0_un_wi:1;
1447 uint64_t c0_un_b2:1;
1448 uint64_t c0_un_b1:1;
1449 uint64_t c0_un_b0:1;
1450 uint64_t c0_up_bx:1;
1451 uint64_t c0_up_wi:1;
1452 uint64_t c0_up_b2:1;
1453 uint64_t c0_up_b1:1;
1454 uint64_t c0_up_b0:1;
1455 uint64_t c1_hpint:1;
1462 uint64_t c0_hpint:1;
1469 uint64_t reserved_15_18:4;
1476 uint64_t reserved_8_8:1;
1486 struct cvmx_npei_int_sum_s cn56xx;
1487 struct cvmx_npei_int_sum_cn56xxp1 {
1488 uint64_t mio_inta:1;
1489 uint64_t reserved_61_62:2;
1494 uint64_t c1_up_wf:1;
1495 uint64_t c0_up_wf:1;
1496 uint64_t c1_un_wf:1;
1497 uint64_t c0_un_wf:1;
1498 uint64_t c1_un_bx:1;
1499 uint64_t c1_un_wi:1;
1500 uint64_t c1_un_b2:1;
1501 uint64_t c1_un_b1:1;
1502 uint64_t c1_un_b0:1;
1503 uint64_t c1_up_bx:1;
1504 uint64_t c1_up_wi:1;
1505 uint64_t c1_up_b2:1;
1506 uint64_t c1_up_b1:1;
1507 uint64_t c1_up_b0:1;
1508 uint64_t c0_un_bx:1;
1509 uint64_t c0_un_wi:1;
1510 uint64_t c0_un_b2:1;
1511 uint64_t c0_un_b1:1;
1512 uint64_t c0_un_b0:1;
1513 uint64_t c0_up_bx:1;
1514 uint64_t c0_up_wi:1;
1515 uint64_t c0_up_b2:1;
1516 uint64_t c0_up_b1:1;
1517 uint64_t c0_up_b0:1;
1518 uint64_t c1_hpint:1;
1521 uint64_t reserved_29_29:1;
1523 uint64_t reserved_27_27:1;
1525 uint64_t c0_hpint:1;
1528 uint64_t reserved_22_22:1;
1530 uint64_t reserved_20_20:1;
1532 uint64_t reserved_15_18:4;
1551 union cvmx_npei_int_sum2 {
1553 struct cvmx_npei_int_sum2_s {
1554 uint64_t mio_inta:1;
1555 uint64_t reserved_62_62:1;
1561 uint64_t c1_up_wf:1;
1562 uint64_t c0_up_wf:1;
1563 uint64_t c1_un_wf:1;
1564 uint64_t c0_un_wf:1;
1565 uint64_t c1_un_bx:1;
1566 uint64_t c1_un_wi:1;
1567 uint64_t c1_un_b2:1;
1568 uint64_t c1_un_b1:1;
1569 uint64_t c1_un_b0:1;
1570 uint64_t c1_up_bx:1;
1571 uint64_t c1_up_wi:1;
1572 uint64_t c1_up_b2:1;
1573 uint64_t c1_up_b1:1;
1574 uint64_t c1_up_b0:1;
1575 uint64_t c0_un_bx:1;
1576 uint64_t c0_un_wi:1;
1577 uint64_t c0_un_b2:1;
1578 uint64_t c0_un_b1:1;
1579 uint64_t c0_un_b0:1;
1580 uint64_t c0_up_bx:1;
1581 uint64_t c0_up_wi:1;
1582 uint64_t c0_up_b2:1;
1583 uint64_t c0_up_b1:1;
1584 uint64_t c0_up_b0:1;
1585 uint64_t c1_hpint:1;
1592 uint64_t c0_hpint:1;
1599 uint64_t reserved_15_18:4;
1606 uint64_t reserved_8_8:1;
1616 struct cvmx_npei_int_sum2_s cn52xx;
1617 struct cvmx_npei_int_sum2_s cn52xxp1;
1618 struct cvmx_npei_int_sum2_s cn56xx;
1621 union cvmx_npei_last_win_rdata0 {
1623 struct cvmx_npei_last_win_rdata0_s {
1626 struct cvmx_npei_last_win_rdata0_s cn52xx;
1627 struct cvmx_npei_last_win_rdata0_s cn52xxp1;
1628 struct cvmx_npei_last_win_rdata0_s cn56xx;
1629 struct cvmx_npei_last_win_rdata0_s cn56xxp1;
1632 union cvmx_npei_last_win_rdata1 {
1634 struct cvmx_npei_last_win_rdata1_s {
1637 struct cvmx_npei_last_win_rdata1_s cn52xx;
1638 struct cvmx_npei_last_win_rdata1_s cn52xxp1;
1639 struct cvmx_npei_last_win_rdata1_s cn56xx;
1640 struct cvmx_npei_last_win_rdata1_s cn56xxp1;
1643 union cvmx_npei_mem_access_ctl {
1645 struct cvmx_npei_mem_access_ctl_s {
1646 uint64_t reserved_14_63:50;
1647 uint64_t max_word:4;
1650 struct cvmx_npei_mem_access_ctl_s cn52xx;
1651 struct cvmx_npei_mem_access_ctl_s cn52xxp1;
1652 struct cvmx_npei_mem_access_ctl_s cn56xx;
1653 struct cvmx_npei_mem_access_ctl_s cn56xxp1;
1656 union cvmx_npei_mem_access_subidx {
1658 struct cvmx_npei_mem_access_subidx_s {
1659 uint64_t reserved_42_63:22;
1671 struct cvmx_npei_mem_access_subidx_s cn52xx;
1672 struct cvmx_npei_mem_access_subidx_s cn52xxp1;
1673 struct cvmx_npei_mem_access_subidx_s cn56xx;
1674 struct cvmx_npei_mem_access_subidx_s cn56xxp1;
1677 union cvmx_npei_msi_enb0 {
1679 struct cvmx_npei_msi_enb0_s {
1682 struct cvmx_npei_msi_enb0_s cn52xx;
1683 struct cvmx_npei_msi_enb0_s cn52xxp1;
1684 struct cvmx_npei_msi_enb0_s cn56xx;
1685 struct cvmx_npei_msi_enb0_s cn56xxp1;
1688 union cvmx_npei_msi_enb1 {
1690 struct cvmx_npei_msi_enb1_s {
1693 struct cvmx_npei_msi_enb1_s cn52xx;
1694 struct cvmx_npei_msi_enb1_s cn52xxp1;
1695 struct cvmx_npei_msi_enb1_s cn56xx;
1696 struct cvmx_npei_msi_enb1_s cn56xxp1;
1699 union cvmx_npei_msi_enb2 {
1701 struct cvmx_npei_msi_enb2_s {
1704 struct cvmx_npei_msi_enb2_s cn52xx;
1705 struct cvmx_npei_msi_enb2_s cn52xxp1;
1706 struct cvmx_npei_msi_enb2_s cn56xx;
1707 struct cvmx_npei_msi_enb2_s cn56xxp1;
1710 union cvmx_npei_msi_enb3 {
1712 struct cvmx_npei_msi_enb3_s {
1715 struct cvmx_npei_msi_enb3_s cn52xx;
1716 struct cvmx_npei_msi_enb3_s cn52xxp1;
1717 struct cvmx_npei_msi_enb3_s cn56xx;
1718 struct cvmx_npei_msi_enb3_s cn56xxp1;
1721 union cvmx_npei_msi_rcv0 {
1723 struct cvmx_npei_msi_rcv0_s {
1726 struct cvmx_npei_msi_rcv0_s cn52xx;
1727 struct cvmx_npei_msi_rcv0_s cn52xxp1;
1728 struct cvmx_npei_msi_rcv0_s cn56xx;
1729 struct cvmx_npei_msi_rcv0_s cn56xxp1;
1732 union cvmx_npei_msi_rcv1 {
1734 struct cvmx_npei_msi_rcv1_s {
1737 struct cvmx_npei_msi_rcv1_s cn52xx;
1738 struct cvmx_npei_msi_rcv1_s cn52xxp1;
1739 struct cvmx_npei_msi_rcv1_s cn56xx;
1740 struct cvmx_npei_msi_rcv1_s cn56xxp1;
1743 union cvmx_npei_msi_rcv2 {
1745 struct cvmx_npei_msi_rcv2_s {
1748 struct cvmx_npei_msi_rcv2_s cn52xx;
1749 struct cvmx_npei_msi_rcv2_s cn52xxp1;
1750 struct cvmx_npei_msi_rcv2_s cn56xx;
1751 struct cvmx_npei_msi_rcv2_s cn56xxp1;
1754 union cvmx_npei_msi_rcv3 {
1756 struct cvmx_npei_msi_rcv3_s {
1759 struct cvmx_npei_msi_rcv3_s cn52xx;
1760 struct cvmx_npei_msi_rcv3_s cn52xxp1;
1761 struct cvmx_npei_msi_rcv3_s cn56xx;
1762 struct cvmx_npei_msi_rcv3_s cn56xxp1;
1765 union cvmx_npei_msi_rd_map {
1767 struct cvmx_npei_msi_rd_map_s {
1768 uint64_t reserved_16_63:48;
1772 struct cvmx_npei_msi_rd_map_s cn52xx;
1773 struct cvmx_npei_msi_rd_map_s cn52xxp1;
1774 struct cvmx_npei_msi_rd_map_s cn56xx;
1775 struct cvmx_npei_msi_rd_map_s cn56xxp1;
1778 union cvmx_npei_msi_w1c_enb0 {
1780 struct cvmx_npei_msi_w1c_enb0_s {
1783 struct cvmx_npei_msi_w1c_enb0_s cn52xx;
1784 struct cvmx_npei_msi_w1c_enb0_s cn56xx;
1787 union cvmx_npei_msi_w1c_enb1 {
1789 struct cvmx_npei_msi_w1c_enb1_s {
1792 struct cvmx_npei_msi_w1c_enb1_s cn52xx;
1793 struct cvmx_npei_msi_w1c_enb1_s cn56xx;
1796 union cvmx_npei_msi_w1c_enb2 {
1798 struct cvmx_npei_msi_w1c_enb2_s {
1801 struct cvmx_npei_msi_w1c_enb2_s cn52xx;
1802 struct cvmx_npei_msi_w1c_enb2_s cn56xx;
1805 union cvmx_npei_msi_w1c_enb3 {
1807 struct cvmx_npei_msi_w1c_enb3_s {
1810 struct cvmx_npei_msi_w1c_enb3_s cn52xx;
1811 struct cvmx_npei_msi_w1c_enb3_s cn56xx;
1814 union cvmx_npei_msi_w1s_enb0 {
1816 struct cvmx_npei_msi_w1s_enb0_s {
1819 struct cvmx_npei_msi_w1s_enb0_s cn52xx;
1820 struct cvmx_npei_msi_w1s_enb0_s cn56xx;
1823 union cvmx_npei_msi_w1s_enb1 {
1825 struct cvmx_npei_msi_w1s_enb1_s {
1828 struct cvmx_npei_msi_w1s_enb1_s cn52xx;
1829 struct cvmx_npei_msi_w1s_enb1_s cn56xx;
1832 union cvmx_npei_msi_w1s_enb2 {
1834 struct cvmx_npei_msi_w1s_enb2_s {
1837 struct cvmx_npei_msi_w1s_enb2_s cn52xx;
1838 struct cvmx_npei_msi_w1s_enb2_s cn56xx;
1841 union cvmx_npei_msi_w1s_enb3 {
1843 struct cvmx_npei_msi_w1s_enb3_s {
1846 struct cvmx_npei_msi_w1s_enb3_s cn52xx;
1847 struct cvmx_npei_msi_w1s_enb3_s cn56xx;
1850 union cvmx_npei_msi_wr_map {
1852 struct cvmx_npei_msi_wr_map_s {
1853 uint64_t reserved_16_63:48;
1857 struct cvmx_npei_msi_wr_map_s cn52xx;
1858 struct cvmx_npei_msi_wr_map_s cn52xxp1;
1859 struct cvmx_npei_msi_wr_map_s cn56xx;
1860 struct cvmx_npei_msi_wr_map_s cn56xxp1;
1863 union cvmx_npei_pcie_credit_cnt {
1865 struct cvmx_npei_pcie_credit_cnt_s {
1866 uint64_t reserved_48_63:16;
1874 struct cvmx_npei_pcie_credit_cnt_s cn52xx;
1875 struct cvmx_npei_pcie_credit_cnt_s cn56xx;
1878 union cvmx_npei_pcie_msi_rcv {
1880 struct cvmx_npei_pcie_msi_rcv_s {
1881 uint64_t reserved_8_63:56;
1884 struct cvmx_npei_pcie_msi_rcv_s cn52xx;
1885 struct cvmx_npei_pcie_msi_rcv_s cn52xxp1;
1886 struct cvmx_npei_pcie_msi_rcv_s cn56xx;
1887 struct cvmx_npei_pcie_msi_rcv_s cn56xxp1;
1890 union cvmx_npei_pcie_msi_rcv_b1 {
1892 struct cvmx_npei_pcie_msi_rcv_b1_s {
1893 uint64_t reserved_16_63:48;
1895 uint64_t reserved_0_7:8;
1897 struct cvmx_npei_pcie_msi_rcv_b1_s cn52xx;
1898 struct cvmx_npei_pcie_msi_rcv_b1_s cn52xxp1;
1899 struct cvmx_npei_pcie_msi_rcv_b1_s cn56xx;
1900 struct cvmx_npei_pcie_msi_rcv_b1_s cn56xxp1;
1903 union cvmx_npei_pcie_msi_rcv_b2 {
1905 struct cvmx_npei_pcie_msi_rcv_b2_s {
1906 uint64_t reserved_24_63:40;
1908 uint64_t reserved_0_15:16;
1910 struct cvmx_npei_pcie_msi_rcv_b2_s cn52xx;
1911 struct cvmx_npei_pcie_msi_rcv_b2_s cn52xxp1;
1912 struct cvmx_npei_pcie_msi_rcv_b2_s cn56xx;
1913 struct cvmx_npei_pcie_msi_rcv_b2_s cn56xxp1;
1916 union cvmx_npei_pcie_msi_rcv_b3 {
1918 struct cvmx_npei_pcie_msi_rcv_b3_s {
1919 uint64_t reserved_32_63:32;
1921 uint64_t reserved_0_23:24;
1923 struct cvmx_npei_pcie_msi_rcv_b3_s cn52xx;
1924 struct cvmx_npei_pcie_msi_rcv_b3_s cn52xxp1;
1925 struct cvmx_npei_pcie_msi_rcv_b3_s cn56xx;
1926 struct cvmx_npei_pcie_msi_rcv_b3_s cn56xxp1;
1929 union cvmx_npei_pktx_cnts {
1931 struct cvmx_npei_pktx_cnts_s {
1932 uint64_t reserved_54_63:10;
1936 struct cvmx_npei_pktx_cnts_s cn52xx;
1937 struct cvmx_npei_pktx_cnts_s cn56xx;
1940 union cvmx_npei_pktx_in_bp {
1942 struct cvmx_npei_pktx_in_bp_s {
1946 struct cvmx_npei_pktx_in_bp_s cn52xx;
1947 struct cvmx_npei_pktx_in_bp_s cn56xx;
1950 union cvmx_npei_pktx_instr_baddr {
1952 struct cvmx_npei_pktx_instr_baddr_s {
1954 uint64_t reserved_0_2:3;
1956 struct cvmx_npei_pktx_instr_baddr_s cn52xx;
1957 struct cvmx_npei_pktx_instr_baddr_s cn56xx;
1960 union cvmx_npei_pktx_instr_baoff_dbell {
1962 struct cvmx_npei_pktx_instr_baoff_dbell_s {
1966 struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx;
1967 struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx;
1970 union cvmx_npei_pktx_instr_fifo_rsize {
1972 struct cvmx_npei_pktx_instr_fifo_rsize_s {
1979 struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx;
1980 struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx;
1983 union cvmx_npei_pktx_instr_header {
1985 struct cvmx_npei_pktx_instr_header_s {
1986 uint64_t reserved_44_63:20;
1988 uint64_t reserved_38_42:5;
1989 uint64_t rparmode:2;
1990 uint64_t reserved_35_35:1;
1991 uint64_t rskp_len:7;
1992 uint64_t reserved_22_27:6;
1993 uint64_t use_ihdr:1;
1994 uint64_t reserved_16_20:5;
1995 uint64_t par_mode:2;
1996 uint64_t reserved_13_13:1;
1998 uint64_t reserved_0_5:6;
2000 struct cvmx_npei_pktx_instr_header_s cn52xx;
2001 struct cvmx_npei_pktx_instr_header_s cn56xx;
2004 union cvmx_npei_pktx_slist_baddr {
2006 struct cvmx_npei_pktx_slist_baddr_s {
2008 uint64_t reserved_0_3:4;
2010 struct cvmx_npei_pktx_slist_baddr_s cn52xx;
2011 struct cvmx_npei_pktx_slist_baddr_s cn56xx;
2014 union cvmx_npei_pktx_slist_baoff_dbell {
2016 struct cvmx_npei_pktx_slist_baoff_dbell_s {
2020 struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx;
2021 struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx;
2024 union cvmx_npei_pktx_slist_fifo_rsize {
2026 struct cvmx_npei_pktx_slist_fifo_rsize_s {
2027 uint64_t reserved_32_63:32;
2030 struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx;
2031 struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx;
2034 union cvmx_npei_pkt_cnt_int {
2036 struct cvmx_npei_pkt_cnt_int_s {
2037 uint64_t reserved_32_63:32;
2040 struct cvmx_npei_pkt_cnt_int_s cn52xx;
2041 struct cvmx_npei_pkt_cnt_int_s cn56xx;
2044 union cvmx_npei_pkt_cnt_int_enb {
2046 struct cvmx_npei_pkt_cnt_int_enb_s {
2047 uint64_t reserved_32_63:32;
2050 struct cvmx_npei_pkt_cnt_int_enb_s cn52xx;
2051 struct cvmx_npei_pkt_cnt_int_enb_s cn56xx;
2054 union cvmx_npei_pkt_data_out_es {
2056 struct cvmx_npei_pkt_data_out_es_s {
2059 struct cvmx_npei_pkt_data_out_es_s cn52xx;
2060 struct cvmx_npei_pkt_data_out_es_s cn56xx;
2063 union cvmx_npei_pkt_data_out_ns {
2065 struct cvmx_npei_pkt_data_out_ns_s {
2066 uint64_t reserved_32_63:32;
2069 struct cvmx_npei_pkt_data_out_ns_s cn52xx;
2070 struct cvmx_npei_pkt_data_out_ns_s cn56xx;
2073 union cvmx_npei_pkt_data_out_ror {
2075 struct cvmx_npei_pkt_data_out_ror_s {
2076 uint64_t reserved_32_63:32;
2079 struct cvmx_npei_pkt_data_out_ror_s cn52xx;
2080 struct cvmx_npei_pkt_data_out_ror_s cn56xx;
2083 union cvmx_npei_pkt_dpaddr {
2085 struct cvmx_npei_pkt_dpaddr_s {
2086 uint64_t reserved_32_63:32;
2089 struct cvmx_npei_pkt_dpaddr_s cn52xx;
2090 struct cvmx_npei_pkt_dpaddr_s cn56xx;
2093 union cvmx_npei_pkt_in_bp {
2095 struct cvmx_npei_pkt_in_bp_s {
2096 uint64_t reserved_32_63:32;
2099 struct cvmx_npei_pkt_in_bp_s cn52xx;
2100 struct cvmx_npei_pkt_in_bp_s cn56xx;
2103 union cvmx_npei_pkt_in_donex_cnts {
2105 struct cvmx_npei_pkt_in_donex_cnts_s {
2106 uint64_t reserved_32_63:32;
2109 struct cvmx_npei_pkt_in_donex_cnts_s cn52xx;
2110 struct cvmx_npei_pkt_in_donex_cnts_s cn56xx;
2113 union cvmx_npei_pkt_in_instr_counts {
2115 struct cvmx_npei_pkt_in_instr_counts_s {
2119 struct cvmx_npei_pkt_in_instr_counts_s cn52xx;
2120 struct cvmx_npei_pkt_in_instr_counts_s cn56xx;
2123 union cvmx_npei_pkt_in_pcie_port {
2125 struct cvmx_npei_pkt_in_pcie_port_s {
2128 struct cvmx_npei_pkt_in_pcie_port_s cn52xx;
2129 struct cvmx_npei_pkt_in_pcie_port_s cn56xx;
2132 union cvmx_npei_pkt_input_control {
2134 struct cvmx_npei_pkt_input_control_s {
2135 uint64_t reserved_23_63:41;
2137 uint64_t pbp_dhi:13;
2146 struct cvmx_npei_pkt_input_control_s cn52xx;
2147 struct cvmx_npei_pkt_input_control_s cn56xx;
2150 union cvmx_npei_pkt_instr_enb {
2152 struct cvmx_npei_pkt_instr_enb_s {
2153 uint64_t reserved_32_63:32;
2156 struct cvmx_npei_pkt_instr_enb_s cn52xx;
2157 struct cvmx_npei_pkt_instr_enb_s cn56xx;
2160 union cvmx_npei_pkt_instr_rd_size {
2162 struct cvmx_npei_pkt_instr_rd_size_s {
2165 struct cvmx_npei_pkt_instr_rd_size_s cn52xx;
2166 struct cvmx_npei_pkt_instr_rd_size_s cn56xx;
2169 union cvmx_npei_pkt_instr_size {
2171 struct cvmx_npei_pkt_instr_size_s {
2172 uint64_t reserved_32_63:32;
2175 struct cvmx_npei_pkt_instr_size_s cn52xx;
2176 struct cvmx_npei_pkt_instr_size_s cn56xx;
2179 union cvmx_npei_pkt_int_levels {
2181 struct cvmx_npei_pkt_int_levels_s {
2182 uint64_t reserved_54_63:10;
2186 struct cvmx_npei_pkt_int_levels_s cn52xx;
2187 struct cvmx_npei_pkt_int_levels_s cn56xx;
2190 union cvmx_npei_pkt_iptr {
2192 struct cvmx_npei_pkt_iptr_s {
2193 uint64_t reserved_32_63:32;
2196 struct cvmx_npei_pkt_iptr_s cn52xx;
2197 struct cvmx_npei_pkt_iptr_s cn56xx;
2200 union cvmx_npei_pkt_out_bmode {
2202 struct cvmx_npei_pkt_out_bmode_s {
2203 uint64_t reserved_32_63:32;
2206 struct cvmx_npei_pkt_out_bmode_s cn52xx;
2207 struct cvmx_npei_pkt_out_bmode_s cn56xx;
2210 union cvmx_npei_pkt_out_enb {
2212 struct cvmx_npei_pkt_out_enb_s {
2213 uint64_t reserved_32_63:32;
2216 struct cvmx_npei_pkt_out_enb_s cn52xx;
2217 struct cvmx_npei_pkt_out_enb_s cn56xx;
2220 union cvmx_npei_pkt_output_wmark {
2222 struct cvmx_npei_pkt_output_wmark_s {
2223 uint64_t reserved_32_63:32;
2226 struct cvmx_npei_pkt_output_wmark_s cn52xx;
2227 struct cvmx_npei_pkt_output_wmark_s cn56xx;
2230 union cvmx_npei_pkt_pcie_port {
2232 struct cvmx_npei_pkt_pcie_port_s {
2235 struct cvmx_npei_pkt_pcie_port_s cn52xx;
2236 struct cvmx_npei_pkt_pcie_port_s cn56xx;
2239 union cvmx_npei_pkt_port_in_rst {
2241 struct cvmx_npei_pkt_port_in_rst_s {
2243 uint64_t out_rst:32;
2245 struct cvmx_npei_pkt_port_in_rst_s cn52xx;
2246 struct cvmx_npei_pkt_port_in_rst_s cn56xx;
2249 union cvmx_npei_pkt_slist_es {
2251 struct cvmx_npei_pkt_slist_es_s {
2254 struct cvmx_npei_pkt_slist_es_s cn52xx;
2255 struct cvmx_npei_pkt_slist_es_s cn56xx;
2258 union cvmx_npei_pkt_slist_id_size {
2260 struct cvmx_npei_pkt_slist_id_size_s {
2261 uint64_t reserved_23_63:41;
2265 struct cvmx_npei_pkt_slist_id_size_s cn52xx;
2266 struct cvmx_npei_pkt_slist_id_size_s cn56xx;
2269 union cvmx_npei_pkt_slist_ns {
2271 struct cvmx_npei_pkt_slist_ns_s {
2272 uint64_t reserved_32_63:32;
2275 struct cvmx_npei_pkt_slist_ns_s cn52xx;
2276 struct cvmx_npei_pkt_slist_ns_s cn56xx;
2279 union cvmx_npei_pkt_slist_ror {
2281 struct cvmx_npei_pkt_slist_ror_s {
2282 uint64_t reserved_32_63:32;
2285 struct cvmx_npei_pkt_slist_ror_s cn52xx;
2286 struct cvmx_npei_pkt_slist_ror_s cn56xx;
2289 union cvmx_npei_pkt_time_int {
2291 struct cvmx_npei_pkt_time_int_s {
2292 uint64_t reserved_32_63:32;
2295 struct cvmx_npei_pkt_time_int_s cn52xx;
2296 struct cvmx_npei_pkt_time_int_s cn56xx;
2299 union cvmx_npei_pkt_time_int_enb {
2301 struct cvmx_npei_pkt_time_int_enb_s {
2302 uint64_t reserved_32_63:32;
2305 struct cvmx_npei_pkt_time_int_enb_s cn52xx;
2306 struct cvmx_npei_pkt_time_int_enb_s cn56xx;
2309 union cvmx_npei_rsl_int_blocks {
2311 struct cvmx_npei_rsl_int_blocks_s {
2312 uint64_t reserved_31_63:33;
2316 uint64_t reserved_24_27:4;
2319 uint64_t reserved_21_21:1;
2332 uint64_t reserved_8_8:1;
2342 struct cvmx_npei_rsl_int_blocks_s cn52xx;
2343 struct cvmx_npei_rsl_int_blocks_s cn52xxp1;
2344 struct cvmx_npei_rsl_int_blocks_s cn56xx;
2345 struct cvmx_npei_rsl_int_blocks_s cn56xxp1;
2348 union cvmx_npei_scratch_1 {
2350 struct cvmx_npei_scratch_1_s {
2353 struct cvmx_npei_scratch_1_s cn52xx;
2354 struct cvmx_npei_scratch_1_s cn52xxp1;
2355 struct cvmx_npei_scratch_1_s cn56xx;
2356 struct cvmx_npei_scratch_1_s cn56xxp1;
2359 union cvmx_npei_state1 {
2361 struct cvmx_npei_state1_s {
2367 struct cvmx_npei_state1_s cn52xx;
2368 struct cvmx_npei_state1_s cn52xxp1;
2369 struct cvmx_npei_state1_s cn56xx;
2370 struct cvmx_npei_state1_s cn56xxp1;
2373 union cvmx_npei_state2 {
2375 struct cvmx_npei_state2_s {
2376 uint64_t reserved_48_63:16;
2384 struct cvmx_npei_state2_s cn52xx;
2385 struct cvmx_npei_state2_s cn52xxp1;
2386 struct cvmx_npei_state2_s cn56xx;
2387 struct cvmx_npei_state2_s cn56xxp1;
2390 union cvmx_npei_state3 {
2392 struct cvmx_npei_state3_s {
2393 uint64_t reserved_56_63:8;
2399 struct cvmx_npei_state3_s cn52xx;
2400 struct cvmx_npei_state3_s cn52xxp1;
2401 struct cvmx_npei_state3_s cn56xx;
2402 struct cvmx_npei_state3_s cn56xxp1;
2405 union cvmx_npei_win_rd_addr {
2407 struct cvmx_npei_win_rd_addr_s {
2408 uint64_t reserved_51_63:13;
2411 uint64_t rd_addr:48;
2413 struct cvmx_npei_win_rd_addr_s cn52xx;
2414 struct cvmx_npei_win_rd_addr_s cn52xxp1;
2415 struct cvmx_npei_win_rd_addr_s cn56xx;
2416 struct cvmx_npei_win_rd_addr_s cn56xxp1;
2419 union cvmx_npei_win_rd_data {
2421 struct cvmx_npei_win_rd_data_s {
2422 uint64_t rd_data:64;
2424 struct cvmx_npei_win_rd_data_s cn52xx;
2425 struct cvmx_npei_win_rd_data_s cn52xxp1;
2426 struct cvmx_npei_win_rd_data_s cn56xx;
2427 struct cvmx_npei_win_rd_data_s cn56xxp1;
2430 union cvmx_npei_win_wr_addr {
2432 struct cvmx_npei_win_wr_addr_s {
2433 uint64_t reserved_49_63:15;
2435 uint64_t wr_addr:46;
2436 uint64_t reserved_0_1:2;
2438 struct cvmx_npei_win_wr_addr_s cn52xx;
2439 struct cvmx_npei_win_wr_addr_s cn52xxp1;
2440 struct cvmx_npei_win_wr_addr_s cn56xx;
2441 struct cvmx_npei_win_wr_addr_s cn56xxp1;
2444 union cvmx_npei_win_wr_data {
2446 struct cvmx_npei_win_wr_data_s {
2447 uint64_t wr_data:64;
2449 struct cvmx_npei_win_wr_data_s cn52xx;
2450 struct cvmx_npei_win_wr_data_s cn52xxp1;
2451 struct cvmx_npei_win_wr_data_s cn56xx;
2452 struct cvmx_npei_win_wr_data_s cn56xxp1;
2455 union cvmx_npei_win_wr_mask {
2457 struct cvmx_npei_win_wr_mask_s {
2458 uint64_t reserved_8_63:56;
2461 struct cvmx_npei_win_wr_mask_s cn52xx;
2462 struct cvmx_npei_win_wr_mask_s cn52xxp1;
2463 struct cvmx_npei_win_wr_mask_s cn56xx;
2464 struct cvmx_npei_win_wr_mask_s cn56xxp1;
2467 union cvmx_npei_window_ctl {
2469 struct cvmx_npei_window_ctl_s {
2470 uint64_t reserved_32_63:32;
2473 struct cvmx_npei_window_ctl_s cn52xx;
2474 struct cvmx_npei_window_ctl_s cn52xxp1;
2475 struct cvmx_npei_window_ctl_s cn56xx;
2476 struct cvmx_npei_window_ctl_s cn56xxp1;