1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2010 Cavium Networks
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_NPI_DEFS_H__
29 #define __CVMX_NPI_DEFS_H__
31 #define CVMX_NPI_BASE_ADDR_INPUT0 CVMX_NPI_BASE_ADDR_INPUTX(0)
32 #define CVMX_NPI_BASE_ADDR_INPUT1 CVMX_NPI_BASE_ADDR_INPUTX(1)
33 #define CVMX_NPI_BASE_ADDR_INPUT2 CVMX_NPI_BASE_ADDR_INPUTX(2)
34 #define CVMX_NPI_BASE_ADDR_INPUT3 CVMX_NPI_BASE_ADDR_INPUTX(3)
35 #define CVMX_NPI_BASE_ADDR_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000070ull) + ((offset) & 3) * 16)
36 #define CVMX_NPI_BASE_ADDR_OUTPUT0 CVMX_NPI_BASE_ADDR_OUTPUTX(0)
37 #define CVMX_NPI_BASE_ADDR_OUTPUT1 CVMX_NPI_BASE_ADDR_OUTPUTX(1)
38 #define CVMX_NPI_BASE_ADDR_OUTPUT2 CVMX_NPI_BASE_ADDR_OUTPUTX(2)
39 #define CVMX_NPI_BASE_ADDR_OUTPUT3 CVMX_NPI_BASE_ADDR_OUTPUTX(3)
40 #define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + ((offset) & 3) * 8)
41 #define CVMX_NPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F00000003F8ull))
42 #define CVMX_NPI_BUFF_SIZE_OUTPUT0 CVMX_NPI_BUFF_SIZE_OUTPUTX(0)
43 #define CVMX_NPI_BUFF_SIZE_OUTPUT1 CVMX_NPI_BUFF_SIZE_OUTPUTX(1)
44 #define CVMX_NPI_BUFF_SIZE_OUTPUT2 CVMX_NPI_BUFF_SIZE_OUTPUTX(2)
45 #define CVMX_NPI_BUFF_SIZE_OUTPUT3 CVMX_NPI_BUFF_SIZE_OUTPUTX(3)
46 #define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + ((offset) & 3) * 8)
47 #define CVMX_NPI_COMP_CTL (CVMX_ADD_IO_SEG(0x00011F0000000218ull))
48 #define CVMX_NPI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000000010ull))
49 #define CVMX_NPI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000000008ull))
50 #define CVMX_NPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000128ull))
51 #define CVMX_NPI_DMA_HIGHP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000148ull))
52 #define CVMX_NPI_DMA_HIGHP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000158ull))
53 #define CVMX_NPI_DMA_LOWP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000140ull))
54 #define CVMX_NPI_DMA_LOWP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000150ull))
55 #define CVMX_NPI_HIGHP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000120ull))
56 #define CVMX_NPI_HIGHP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000110ull))
57 #define CVMX_NPI_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000138ull))
58 #define CVMX_NPI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000000020ull))
59 #define CVMX_NPI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000000018ull))
60 #define CVMX_NPI_LOWP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000118ull))
61 #define CVMX_NPI_LOWP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000108ull))
62 #define CVMX_NPI_MEM_ACCESS_SUBID3 CVMX_NPI_MEM_ACCESS_SUBIDX(3)
63 #define CVMX_NPI_MEM_ACCESS_SUBID4 CVMX_NPI_MEM_ACCESS_SUBIDX(4)
64 #define CVMX_NPI_MEM_ACCESS_SUBID5 CVMX_NPI_MEM_ACCESS_SUBIDX(5)
65 #define CVMX_NPI_MEM_ACCESS_SUBID6 CVMX_NPI_MEM_ACCESS_SUBIDX(6)
66 #define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000028ull) + ((offset) & 7) * 8 - 8*3)
67 #define CVMX_NPI_MSI_RCV (0x0000000000000190ull)
68 #define CVMX_NPI_NPI_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000001190ull))
69 #define CVMX_NPI_NUM_DESC_OUTPUT0 CVMX_NPI_NUM_DESC_OUTPUTX(0)
70 #define CVMX_NPI_NUM_DESC_OUTPUT1 CVMX_NPI_NUM_DESC_OUTPUTX(1)
71 #define CVMX_NPI_NUM_DESC_OUTPUT2 CVMX_NPI_NUM_DESC_OUTPUTX(2)
72 #define CVMX_NPI_NUM_DESC_OUTPUT3 CVMX_NPI_NUM_DESC_OUTPUTX(3)
73 #define CVMX_NPI_NUM_DESC_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000050ull) + ((offset) & 3) * 8)
74 #define CVMX_NPI_OUTPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000100ull))
75 #define CVMX_NPI_P0_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(0)
76 #define CVMX_NPI_P0_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(0)
77 #define CVMX_NPI_P0_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(0)
78 #define CVMX_NPI_P0_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(0)
79 #define CVMX_NPI_P1_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(1)
80 #define CVMX_NPI_P1_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(1)
81 #define CVMX_NPI_P1_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(1)
82 #define CVMX_NPI_P1_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(1)
83 #define CVMX_NPI_P2_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(2)
84 #define CVMX_NPI_P2_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(2)
85 #define CVMX_NPI_P2_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(2)
86 #define CVMX_NPI_P2_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(2)
87 #define CVMX_NPI_P3_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(3)
88 #define CVMX_NPI_P3_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(3)
89 #define CVMX_NPI_P3_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(3)
90 #define CVMX_NPI_P3_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(3)
91 #define CVMX_NPI_PCI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000001100ull) + ((offset) & 31) * 4)
92 #define CVMX_NPI_PCI_BIST_REG (CVMX_ADD_IO_SEG(0x00011F00000011C0ull))
93 #define CVMX_NPI_PCI_BURST_SIZE (CVMX_ADD_IO_SEG(0x00011F00000000D8ull))
94 #define CVMX_NPI_PCI_CFG00 (CVMX_ADD_IO_SEG(0x00011F0000001800ull))
95 #define CVMX_NPI_PCI_CFG01 (CVMX_ADD_IO_SEG(0x00011F0000001804ull))
96 #define CVMX_NPI_PCI_CFG02 (CVMX_ADD_IO_SEG(0x00011F0000001808ull))
97 #define CVMX_NPI_PCI_CFG03 (CVMX_ADD_IO_SEG(0x00011F000000180Cull))
98 #define CVMX_NPI_PCI_CFG04 (CVMX_ADD_IO_SEG(0x00011F0000001810ull))
99 #define CVMX_NPI_PCI_CFG05 (CVMX_ADD_IO_SEG(0x00011F0000001814ull))
100 #define CVMX_NPI_PCI_CFG06 (CVMX_ADD_IO_SEG(0x00011F0000001818ull))
101 #define CVMX_NPI_PCI_CFG07 (CVMX_ADD_IO_SEG(0x00011F000000181Cull))
102 #define CVMX_NPI_PCI_CFG08 (CVMX_ADD_IO_SEG(0x00011F0000001820ull))
103 #define CVMX_NPI_PCI_CFG09 (CVMX_ADD_IO_SEG(0x00011F0000001824ull))
104 #define CVMX_NPI_PCI_CFG10 (CVMX_ADD_IO_SEG(0x00011F0000001828ull))
105 #define CVMX_NPI_PCI_CFG11 (CVMX_ADD_IO_SEG(0x00011F000000182Cull))
106 #define CVMX_NPI_PCI_CFG12 (CVMX_ADD_IO_SEG(0x00011F0000001830ull))
107 #define CVMX_NPI_PCI_CFG13 (CVMX_ADD_IO_SEG(0x00011F0000001834ull))
108 #define CVMX_NPI_PCI_CFG15 (CVMX_ADD_IO_SEG(0x00011F000000183Cull))
109 #define CVMX_NPI_PCI_CFG16 (CVMX_ADD_IO_SEG(0x00011F0000001840ull))
110 #define CVMX_NPI_PCI_CFG17 (CVMX_ADD_IO_SEG(0x00011F0000001844ull))
111 #define CVMX_NPI_PCI_CFG18 (CVMX_ADD_IO_SEG(0x00011F0000001848ull))
112 #define CVMX_NPI_PCI_CFG19 (CVMX_ADD_IO_SEG(0x00011F000000184Cull))
113 #define CVMX_NPI_PCI_CFG20 (CVMX_ADD_IO_SEG(0x00011F0000001850ull))
114 #define CVMX_NPI_PCI_CFG21 (CVMX_ADD_IO_SEG(0x00011F0000001854ull))
115 #define CVMX_NPI_PCI_CFG22 (CVMX_ADD_IO_SEG(0x00011F0000001858ull))
116 #define CVMX_NPI_PCI_CFG56 (CVMX_ADD_IO_SEG(0x00011F00000018E0ull))
117 #define CVMX_NPI_PCI_CFG57 (CVMX_ADD_IO_SEG(0x00011F00000018E4ull))
118 #define CVMX_NPI_PCI_CFG58 (CVMX_ADD_IO_SEG(0x00011F00000018E8ull))
119 #define CVMX_NPI_PCI_CFG59 (CVMX_ADD_IO_SEG(0x00011F00000018ECull))
120 #define CVMX_NPI_PCI_CFG60 (CVMX_ADD_IO_SEG(0x00011F00000018F0ull))
121 #define CVMX_NPI_PCI_CFG61 (CVMX_ADD_IO_SEG(0x00011F00000018F4ull))
122 #define CVMX_NPI_PCI_CFG62 (CVMX_ADD_IO_SEG(0x00011F00000018F8ull))
123 #define CVMX_NPI_PCI_CFG63 (CVMX_ADD_IO_SEG(0x00011F00000018FCull))
124 #define CVMX_NPI_PCI_CNT_REG (CVMX_ADD_IO_SEG(0x00011F00000011B8ull))
125 #define CVMX_NPI_PCI_CTL_STATUS_2 (CVMX_ADD_IO_SEG(0x00011F000000118Cull))
126 #define CVMX_NPI_PCI_INT_ARB_CFG (CVMX_ADD_IO_SEG(0x00011F0000000130ull))
127 #define CVMX_NPI_PCI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F00000011A0ull))
128 #define CVMX_NPI_PCI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F0000001198ull))
129 #define CVMX_NPI_PCI_READ_CMD (CVMX_ADD_IO_SEG(0x00011F0000000048ull))
130 #define CVMX_NPI_PCI_READ_CMD_6 (CVMX_ADD_IO_SEG(0x00011F0000001180ull))
131 #define CVMX_NPI_PCI_READ_CMD_C (CVMX_ADD_IO_SEG(0x00011F0000001184ull))
132 #define CVMX_NPI_PCI_READ_CMD_E (CVMX_ADD_IO_SEG(0x00011F0000001188ull))
133 #define CVMX_NPI_PCI_SCM_REG (CVMX_ADD_IO_SEG(0x00011F00000011A8ull))
134 #define CVMX_NPI_PCI_TSR_REG (CVMX_ADD_IO_SEG(0x00011F00000011B0ull))
135 #define CVMX_NPI_PORT32_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F00000001F8ull))
136 #define CVMX_NPI_PORT33_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000200ull))
137 #define CVMX_NPI_PORT34_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000208ull))
138 #define CVMX_NPI_PORT35_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000210ull))
139 #define CVMX_NPI_PORT_BP_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000001F0ull))
140 #define CVMX_NPI_PX_DBPAIR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000000180ull) + ((offset) & 3) * 8)
141 #define CVMX_NPI_PX_INSTR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000001C0ull) + ((offset) & 3) * 8)
142 #define CVMX_NPI_PX_INSTR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F00000001A0ull) + ((offset) & 3) * 8)
143 #define CVMX_NPI_PX_PAIR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000000160ull) + ((offset) & 3) * 8)
144 #define CVMX_NPI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000000000ull))
145 #define CVMX_NPI_SIZE_INPUT0 CVMX_NPI_SIZE_INPUTX(0)
146 #define CVMX_NPI_SIZE_INPUT1 CVMX_NPI_SIZE_INPUTX(1)
147 #define CVMX_NPI_SIZE_INPUT2 CVMX_NPI_SIZE_INPUTX(2)
148 #define CVMX_NPI_SIZE_INPUT3 CVMX_NPI_SIZE_INPUTX(3)
149 #define CVMX_NPI_SIZE_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000078ull) + ((offset) & 3) * 16)
150 #define CVMX_NPI_WIN_READ_TO (CVMX_ADD_IO_SEG(0x00011F00000001E0ull))
152 union cvmx_npi_base_addr_inputx {
154 struct cvmx_npi_base_addr_inputx_s {
156 uint64_t reserved_0_2:3;
158 struct cvmx_npi_base_addr_inputx_s cn30xx;
159 struct cvmx_npi_base_addr_inputx_s cn31xx;
160 struct cvmx_npi_base_addr_inputx_s cn38xx;
161 struct cvmx_npi_base_addr_inputx_s cn38xxp2;
162 struct cvmx_npi_base_addr_inputx_s cn50xx;
163 struct cvmx_npi_base_addr_inputx_s cn58xx;
164 struct cvmx_npi_base_addr_inputx_s cn58xxp1;
167 union cvmx_npi_base_addr_outputx {
169 struct cvmx_npi_base_addr_outputx_s {
171 uint64_t reserved_0_2:3;
173 struct cvmx_npi_base_addr_outputx_s cn30xx;
174 struct cvmx_npi_base_addr_outputx_s cn31xx;
175 struct cvmx_npi_base_addr_outputx_s cn38xx;
176 struct cvmx_npi_base_addr_outputx_s cn38xxp2;
177 struct cvmx_npi_base_addr_outputx_s cn50xx;
178 struct cvmx_npi_base_addr_outputx_s cn58xx;
179 struct cvmx_npi_base_addr_outputx_s cn58xxp1;
182 union cvmx_npi_bist_status {
184 struct cvmx_npi_bist_status_s {
185 uint64_t reserved_20_63:44;
207 struct cvmx_npi_bist_status_cn30xx {
208 uint64_t reserved_20_63:44;
221 uint64_t reserved_5_7:3;
228 struct cvmx_npi_bist_status_s cn31xx;
229 struct cvmx_npi_bist_status_s cn38xx;
230 struct cvmx_npi_bist_status_s cn38xxp2;
231 struct cvmx_npi_bist_status_cn50xx {
232 uint64_t reserved_20_63:44;
246 uint64_t reserved_5_6:2;
253 struct cvmx_npi_bist_status_s cn58xx;
254 struct cvmx_npi_bist_status_s cn58xxp1;
257 union cvmx_npi_buff_size_outputx {
259 struct cvmx_npi_buff_size_outputx_s {
260 uint64_t reserved_23_63:41;
264 struct cvmx_npi_buff_size_outputx_s cn30xx;
265 struct cvmx_npi_buff_size_outputx_s cn31xx;
266 struct cvmx_npi_buff_size_outputx_s cn38xx;
267 struct cvmx_npi_buff_size_outputx_s cn38xxp2;
268 struct cvmx_npi_buff_size_outputx_s cn50xx;
269 struct cvmx_npi_buff_size_outputx_s cn58xx;
270 struct cvmx_npi_buff_size_outputx_s cn58xxp1;
273 union cvmx_npi_comp_ctl {
275 struct cvmx_npi_comp_ctl_s {
276 uint64_t reserved_10_63:54;
280 struct cvmx_npi_comp_ctl_s cn50xx;
281 struct cvmx_npi_comp_ctl_s cn58xx;
282 struct cvmx_npi_comp_ctl_s cn58xxp1;
285 union cvmx_npi_ctl_status {
287 struct cvmx_npi_ctl_status_s {
288 uint64_t reserved_63_63:1;
305 uint64_t reserved_37_39:3;
307 uint64_t reserved_10_31:22;
310 struct cvmx_npi_ctl_status_cn30xx {
311 uint64_t reserved_63_63:1;
314 uint64_t reserved_51_53:3;
316 uint64_t reserved_47_49:3;
318 uint64_t reserved_43_45:3;
322 uint64_t reserved_37_39:3;
324 uint64_t reserved_10_31:22;
327 struct cvmx_npi_ctl_status_cn31xx {
328 uint64_t reserved_63_63:1;
331 uint64_t reserved_52_53:2;
334 uint64_t reserved_48_49:2;
337 uint64_t reserved_44_45:2;
342 uint64_t reserved_37_39:3;
344 uint64_t reserved_10_31:22;
347 struct cvmx_npi_ctl_status_s cn38xx;
348 struct cvmx_npi_ctl_status_s cn38xxp2;
349 struct cvmx_npi_ctl_status_cn31xx cn50xx;
350 struct cvmx_npi_ctl_status_s cn58xx;
351 struct cvmx_npi_ctl_status_s cn58xxp1;
354 union cvmx_npi_dbg_select {
356 struct cvmx_npi_dbg_select_s {
357 uint64_t reserved_16_63:48;
360 struct cvmx_npi_dbg_select_s cn30xx;
361 struct cvmx_npi_dbg_select_s cn31xx;
362 struct cvmx_npi_dbg_select_s cn38xx;
363 struct cvmx_npi_dbg_select_s cn38xxp2;
364 struct cvmx_npi_dbg_select_s cn50xx;
365 struct cvmx_npi_dbg_select_s cn58xx;
366 struct cvmx_npi_dbg_select_s cn58xxp1;
369 union cvmx_npi_dma_control {
371 struct cvmx_npi_dma_control_s {
372 uint64_t reserved_36_63:28;
386 struct cvmx_npi_dma_control_s cn30xx;
387 struct cvmx_npi_dma_control_s cn31xx;
388 struct cvmx_npi_dma_control_s cn38xx;
389 struct cvmx_npi_dma_control_s cn38xxp2;
390 struct cvmx_npi_dma_control_s cn50xx;
391 struct cvmx_npi_dma_control_s cn58xx;
392 struct cvmx_npi_dma_control_s cn58xxp1;
395 union cvmx_npi_dma_highp_counts {
397 struct cvmx_npi_dma_highp_counts_s {
398 uint64_t reserved_39_63:25;
402 struct cvmx_npi_dma_highp_counts_s cn30xx;
403 struct cvmx_npi_dma_highp_counts_s cn31xx;
404 struct cvmx_npi_dma_highp_counts_s cn38xx;
405 struct cvmx_npi_dma_highp_counts_s cn38xxp2;
406 struct cvmx_npi_dma_highp_counts_s cn50xx;
407 struct cvmx_npi_dma_highp_counts_s cn58xx;
408 struct cvmx_npi_dma_highp_counts_s cn58xxp1;
411 union cvmx_npi_dma_highp_naddr {
413 struct cvmx_npi_dma_highp_naddr_s {
414 uint64_t reserved_40_63:24;
418 struct cvmx_npi_dma_highp_naddr_s cn30xx;
419 struct cvmx_npi_dma_highp_naddr_s cn31xx;
420 struct cvmx_npi_dma_highp_naddr_s cn38xx;
421 struct cvmx_npi_dma_highp_naddr_s cn38xxp2;
422 struct cvmx_npi_dma_highp_naddr_s cn50xx;
423 struct cvmx_npi_dma_highp_naddr_s cn58xx;
424 struct cvmx_npi_dma_highp_naddr_s cn58xxp1;
427 union cvmx_npi_dma_lowp_counts {
429 struct cvmx_npi_dma_lowp_counts_s {
430 uint64_t reserved_39_63:25;
434 struct cvmx_npi_dma_lowp_counts_s cn30xx;
435 struct cvmx_npi_dma_lowp_counts_s cn31xx;
436 struct cvmx_npi_dma_lowp_counts_s cn38xx;
437 struct cvmx_npi_dma_lowp_counts_s cn38xxp2;
438 struct cvmx_npi_dma_lowp_counts_s cn50xx;
439 struct cvmx_npi_dma_lowp_counts_s cn58xx;
440 struct cvmx_npi_dma_lowp_counts_s cn58xxp1;
443 union cvmx_npi_dma_lowp_naddr {
445 struct cvmx_npi_dma_lowp_naddr_s {
446 uint64_t reserved_40_63:24;
450 struct cvmx_npi_dma_lowp_naddr_s cn30xx;
451 struct cvmx_npi_dma_lowp_naddr_s cn31xx;
452 struct cvmx_npi_dma_lowp_naddr_s cn38xx;
453 struct cvmx_npi_dma_lowp_naddr_s cn38xxp2;
454 struct cvmx_npi_dma_lowp_naddr_s cn50xx;
455 struct cvmx_npi_dma_lowp_naddr_s cn58xx;
456 struct cvmx_npi_dma_lowp_naddr_s cn58xxp1;
459 union cvmx_npi_highp_dbell {
461 struct cvmx_npi_highp_dbell_s {
462 uint64_t reserved_16_63:48;
465 struct cvmx_npi_highp_dbell_s cn30xx;
466 struct cvmx_npi_highp_dbell_s cn31xx;
467 struct cvmx_npi_highp_dbell_s cn38xx;
468 struct cvmx_npi_highp_dbell_s cn38xxp2;
469 struct cvmx_npi_highp_dbell_s cn50xx;
470 struct cvmx_npi_highp_dbell_s cn58xx;
471 struct cvmx_npi_highp_dbell_s cn58xxp1;
474 union cvmx_npi_highp_ibuff_saddr {
476 struct cvmx_npi_highp_ibuff_saddr_s {
477 uint64_t reserved_36_63:28;
480 struct cvmx_npi_highp_ibuff_saddr_s cn30xx;
481 struct cvmx_npi_highp_ibuff_saddr_s cn31xx;
482 struct cvmx_npi_highp_ibuff_saddr_s cn38xx;
483 struct cvmx_npi_highp_ibuff_saddr_s cn38xxp2;
484 struct cvmx_npi_highp_ibuff_saddr_s cn50xx;
485 struct cvmx_npi_highp_ibuff_saddr_s cn58xx;
486 struct cvmx_npi_highp_ibuff_saddr_s cn58xxp1;
489 union cvmx_npi_input_control {
491 struct cvmx_npi_input_control_s {
492 uint64_t reserved_23_63:41;
503 struct cvmx_npi_input_control_cn30xx {
504 uint64_t reserved_22_63:42;
514 struct cvmx_npi_input_control_cn30xx cn31xx;
515 struct cvmx_npi_input_control_s cn38xx;
516 struct cvmx_npi_input_control_cn30xx cn38xxp2;
517 struct cvmx_npi_input_control_s cn50xx;
518 struct cvmx_npi_input_control_s cn58xx;
519 struct cvmx_npi_input_control_s cn58xxp1;
522 union cvmx_npi_int_enb {
524 struct cvmx_npi_int_enb_s {
525 uint64_t reserved_62_63:2;
589 struct cvmx_npi_int_enb_cn30xx {
590 uint64_t reserved_62_63:2;
614 uint64_t reserved_36_38:3;
616 uint64_t reserved_32_34:3;
618 uint64_t reserved_28_30:3;
620 uint64_t reserved_24_26:3;
622 uint64_t reserved_20_22:3;
624 uint64_t reserved_16_18:3;
626 uint64_t reserved_12_14:3;
628 uint64_t reserved_8_10:3;
630 uint64_t reserved_4_6:3;
636 struct cvmx_npi_int_enb_cn31xx {
637 uint64_t reserved_62_63:2;
661 uint64_t reserved_37_38:2;
664 uint64_t reserved_33_34:2;
667 uint64_t reserved_29_30:2;
670 uint64_t reserved_25_26:2;
673 uint64_t reserved_21_22:2;
676 uint64_t reserved_17_18:2;
679 uint64_t reserved_13_14:2;
682 uint64_t reserved_9_10:2;
685 uint64_t reserved_5_6:2;
692 struct cvmx_npi_int_enb_s cn38xx;
693 struct cvmx_npi_int_enb_cn38xxp2 {
694 uint64_t reserved_42_63:22;
738 struct cvmx_npi_int_enb_cn31xx cn50xx;
739 struct cvmx_npi_int_enb_s cn58xx;
740 struct cvmx_npi_int_enb_s cn58xxp1;
743 union cvmx_npi_int_sum {
745 struct cvmx_npi_int_sum_s {
746 uint64_t reserved_62_63:2;
810 struct cvmx_npi_int_sum_cn30xx {
811 uint64_t reserved_62_63:2;
835 uint64_t reserved_36_38:3;
837 uint64_t reserved_32_34:3;
839 uint64_t reserved_28_30:3;
841 uint64_t reserved_24_26:3;
843 uint64_t reserved_20_22:3;
845 uint64_t reserved_16_18:3;
847 uint64_t reserved_12_14:3;
849 uint64_t reserved_8_10:3;
851 uint64_t reserved_4_6:3;
857 struct cvmx_npi_int_sum_cn31xx {
858 uint64_t reserved_62_63:2;
882 uint64_t reserved_37_38:2;
885 uint64_t reserved_33_34:2;
888 uint64_t reserved_29_30:2;
891 uint64_t reserved_25_26:2;
894 uint64_t reserved_21_22:2;
897 uint64_t reserved_17_18:2;
900 uint64_t reserved_13_14:2;
903 uint64_t reserved_9_10:2;
906 uint64_t reserved_5_6:2;
913 struct cvmx_npi_int_sum_s cn38xx;
914 struct cvmx_npi_int_sum_cn38xxp2 {
915 uint64_t reserved_42_63:22;
959 struct cvmx_npi_int_sum_cn31xx cn50xx;
960 struct cvmx_npi_int_sum_s cn58xx;
961 struct cvmx_npi_int_sum_s cn58xxp1;
964 union cvmx_npi_lowp_dbell {
966 struct cvmx_npi_lowp_dbell_s {
967 uint64_t reserved_16_63:48;
970 struct cvmx_npi_lowp_dbell_s cn30xx;
971 struct cvmx_npi_lowp_dbell_s cn31xx;
972 struct cvmx_npi_lowp_dbell_s cn38xx;
973 struct cvmx_npi_lowp_dbell_s cn38xxp2;
974 struct cvmx_npi_lowp_dbell_s cn50xx;
975 struct cvmx_npi_lowp_dbell_s cn58xx;
976 struct cvmx_npi_lowp_dbell_s cn58xxp1;
979 union cvmx_npi_lowp_ibuff_saddr {
981 struct cvmx_npi_lowp_ibuff_saddr_s {
982 uint64_t reserved_36_63:28;
985 struct cvmx_npi_lowp_ibuff_saddr_s cn30xx;
986 struct cvmx_npi_lowp_ibuff_saddr_s cn31xx;
987 struct cvmx_npi_lowp_ibuff_saddr_s cn38xx;
988 struct cvmx_npi_lowp_ibuff_saddr_s cn38xxp2;
989 struct cvmx_npi_lowp_ibuff_saddr_s cn50xx;
990 struct cvmx_npi_lowp_ibuff_saddr_s cn58xx;
991 struct cvmx_npi_lowp_ibuff_saddr_s cn58xxp1;
994 union cvmx_npi_mem_access_subidx {
996 struct cvmx_npi_mem_access_subidx_s {
997 uint64_t reserved_38_63:26;
1008 struct cvmx_npi_mem_access_subidx_s cn30xx;
1009 struct cvmx_npi_mem_access_subidx_cn31xx {
1010 uint64_t reserved_36_63:28;
1019 struct cvmx_npi_mem_access_subidx_s cn38xx;
1020 struct cvmx_npi_mem_access_subidx_cn31xx cn38xxp2;
1021 struct cvmx_npi_mem_access_subidx_s cn50xx;
1022 struct cvmx_npi_mem_access_subidx_s cn58xx;
1023 struct cvmx_npi_mem_access_subidx_s cn58xxp1;
1026 union cvmx_npi_msi_rcv {
1028 struct cvmx_npi_msi_rcv_s {
1029 uint64_t int_vec:64;
1031 struct cvmx_npi_msi_rcv_s cn30xx;
1032 struct cvmx_npi_msi_rcv_s cn31xx;
1033 struct cvmx_npi_msi_rcv_s cn38xx;
1034 struct cvmx_npi_msi_rcv_s cn38xxp2;
1035 struct cvmx_npi_msi_rcv_s cn50xx;
1036 struct cvmx_npi_msi_rcv_s cn58xx;
1037 struct cvmx_npi_msi_rcv_s cn58xxp1;
1040 union cvmx_npi_num_desc_outputx {
1042 struct cvmx_npi_num_desc_outputx_s {
1043 uint64_t reserved_32_63:32;
1046 struct cvmx_npi_num_desc_outputx_s cn30xx;
1047 struct cvmx_npi_num_desc_outputx_s cn31xx;
1048 struct cvmx_npi_num_desc_outputx_s cn38xx;
1049 struct cvmx_npi_num_desc_outputx_s cn38xxp2;
1050 struct cvmx_npi_num_desc_outputx_s cn50xx;
1051 struct cvmx_npi_num_desc_outputx_s cn58xx;
1052 struct cvmx_npi_num_desc_outputx_s cn58xxp1;
1055 union cvmx_npi_output_control {
1057 struct cvmx_npi_output_control_s {
1058 uint64_t reserved_49_63:15;
1060 uint64_t p3_bmode:1;
1061 uint64_t p2_bmode:1;
1062 uint64_t p1_bmode:1;
1063 uint64_t p0_bmode:1;
1080 uint64_t reserved_20_23:4;
1098 struct cvmx_npi_output_control_cn30xx {
1099 uint64_t reserved_45_63:19;
1100 uint64_t p0_bmode:1;
1101 uint64_t reserved_32_43:12;
1105 uint64_t reserved_25_27:3;
1107 uint64_t reserved_17_23:7;
1109 uint64_t reserved_4_15:12;
1114 struct cvmx_npi_output_control_cn31xx {
1115 uint64_t reserved_46_63:18;
1116 uint64_t p1_bmode:1;
1117 uint64_t p0_bmode:1;
1118 uint64_t reserved_36_43:8;
1125 uint64_t reserved_26_27:2;
1128 uint64_t reserved_18_23:6;
1131 uint64_t reserved_8_15:8;
1139 struct cvmx_npi_output_control_s cn38xx;
1140 struct cvmx_npi_output_control_cn38xxp2 {
1141 uint64_t reserved_48_63:16;
1142 uint64_t p3_bmode:1;
1143 uint64_t p2_bmode:1;
1144 uint64_t p1_bmode:1;
1145 uint64_t p0_bmode:1;
1162 uint64_t reserved_20_23:4;
1180 struct cvmx_npi_output_control_cn50xx {
1181 uint64_t reserved_49_63:15;
1183 uint64_t reserved_46_47:2;
1184 uint64_t p1_bmode:1;
1185 uint64_t p0_bmode:1;
1186 uint64_t reserved_36_43:8;
1193 uint64_t reserved_26_27:2;
1196 uint64_t reserved_18_23:6;
1199 uint64_t reserved_8_15:8;
1207 struct cvmx_npi_output_control_s cn58xx;
1208 struct cvmx_npi_output_control_s cn58xxp1;
1211 union cvmx_npi_px_dbpair_addr {
1213 struct cvmx_npi_px_dbpair_addr_s {
1214 uint64_t reserved_63_63:1;
1218 struct cvmx_npi_px_dbpair_addr_s cn30xx;
1219 struct cvmx_npi_px_dbpair_addr_s cn31xx;
1220 struct cvmx_npi_px_dbpair_addr_s cn38xx;
1221 struct cvmx_npi_px_dbpair_addr_s cn38xxp2;
1222 struct cvmx_npi_px_dbpair_addr_s cn50xx;
1223 struct cvmx_npi_px_dbpair_addr_s cn58xx;
1224 struct cvmx_npi_px_dbpair_addr_s cn58xxp1;
1227 union cvmx_npi_px_instr_addr {
1229 struct cvmx_npi_px_instr_addr_s {
1233 struct cvmx_npi_px_instr_addr_s cn30xx;
1234 struct cvmx_npi_px_instr_addr_s cn31xx;
1235 struct cvmx_npi_px_instr_addr_s cn38xx;
1236 struct cvmx_npi_px_instr_addr_s cn38xxp2;
1237 struct cvmx_npi_px_instr_addr_s cn50xx;
1238 struct cvmx_npi_px_instr_addr_s cn58xx;
1239 struct cvmx_npi_px_instr_addr_s cn58xxp1;
1242 union cvmx_npi_px_instr_cnts {
1244 struct cvmx_npi_px_instr_cnts_s {
1245 uint64_t reserved_38_63:26;
1249 struct cvmx_npi_px_instr_cnts_s cn30xx;
1250 struct cvmx_npi_px_instr_cnts_s cn31xx;
1251 struct cvmx_npi_px_instr_cnts_s cn38xx;
1252 struct cvmx_npi_px_instr_cnts_s cn38xxp2;
1253 struct cvmx_npi_px_instr_cnts_s cn50xx;
1254 struct cvmx_npi_px_instr_cnts_s cn58xx;
1255 struct cvmx_npi_px_instr_cnts_s cn58xxp1;
1258 union cvmx_npi_px_pair_cnts {
1260 struct cvmx_npi_px_pair_cnts_s {
1261 uint64_t reserved_37_63:27;
1265 struct cvmx_npi_px_pair_cnts_s cn30xx;
1266 struct cvmx_npi_px_pair_cnts_s cn31xx;
1267 struct cvmx_npi_px_pair_cnts_s cn38xx;
1268 struct cvmx_npi_px_pair_cnts_s cn38xxp2;
1269 struct cvmx_npi_px_pair_cnts_s cn50xx;
1270 struct cvmx_npi_px_pair_cnts_s cn58xx;
1271 struct cvmx_npi_px_pair_cnts_s cn58xxp1;
1274 union cvmx_npi_pci_burst_size {
1276 struct cvmx_npi_pci_burst_size_s {
1277 uint64_t reserved_14_63:50;
1281 struct cvmx_npi_pci_burst_size_s cn30xx;
1282 struct cvmx_npi_pci_burst_size_s cn31xx;
1283 struct cvmx_npi_pci_burst_size_s cn38xx;
1284 struct cvmx_npi_pci_burst_size_s cn38xxp2;
1285 struct cvmx_npi_pci_burst_size_s cn50xx;
1286 struct cvmx_npi_pci_burst_size_s cn58xx;
1287 struct cvmx_npi_pci_burst_size_s cn58xxp1;
1290 union cvmx_npi_pci_int_arb_cfg {
1292 struct cvmx_npi_pci_int_arb_cfg_s {
1293 uint64_t reserved_13_63:51;
1294 uint64_t hostmode:1;
1296 uint64_t reserved_5_7:3;
1298 uint64_t park_mod:1;
1299 uint64_t park_dev:3;
1301 struct cvmx_npi_pci_int_arb_cfg_cn30xx {
1302 uint64_t reserved_5_63:59;
1304 uint64_t park_mod:1;
1305 uint64_t park_dev:3;
1307 struct cvmx_npi_pci_int_arb_cfg_cn30xx cn31xx;
1308 struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xx;
1309 struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xxp2;
1310 struct cvmx_npi_pci_int_arb_cfg_s cn50xx;
1311 struct cvmx_npi_pci_int_arb_cfg_s cn58xx;
1312 struct cvmx_npi_pci_int_arb_cfg_s cn58xxp1;
1315 union cvmx_npi_pci_read_cmd {
1317 struct cvmx_npi_pci_read_cmd_s {
1318 uint64_t reserved_11_63:53;
1319 uint64_t cmd_size:11;
1321 struct cvmx_npi_pci_read_cmd_s cn30xx;
1322 struct cvmx_npi_pci_read_cmd_s cn31xx;
1323 struct cvmx_npi_pci_read_cmd_s cn38xx;
1324 struct cvmx_npi_pci_read_cmd_s cn38xxp2;
1325 struct cvmx_npi_pci_read_cmd_s cn50xx;
1326 struct cvmx_npi_pci_read_cmd_s cn58xx;
1327 struct cvmx_npi_pci_read_cmd_s cn58xxp1;
1330 union cvmx_npi_port32_instr_hdr {
1332 struct cvmx_npi_port32_instr_hdr_s {
1333 uint64_t reserved_44_63:20;
1336 uint64_t rparmode:2;
1338 uint64_t rskp_len:7;
1340 uint64_t use_ihdr:1;
1342 uint64_t par_mode:2;
1347 struct cvmx_npi_port32_instr_hdr_s cn30xx;
1348 struct cvmx_npi_port32_instr_hdr_s cn31xx;
1349 struct cvmx_npi_port32_instr_hdr_s cn38xx;
1350 struct cvmx_npi_port32_instr_hdr_s cn38xxp2;
1351 struct cvmx_npi_port32_instr_hdr_s cn50xx;
1352 struct cvmx_npi_port32_instr_hdr_s cn58xx;
1353 struct cvmx_npi_port32_instr_hdr_s cn58xxp1;
1356 union cvmx_npi_port33_instr_hdr {
1358 struct cvmx_npi_port33_instr_hdr_s {
1359 uint64_t reserved_44_63:20;
1362 uint64_t rparmode:2;
1364 uint64_t rskp_len:7;
1366 uint64_t use_ihdr:1;
1368 uint64_t par_mode:2;
1373 struct cvmx_npi_port33_instr_hdr_s cn31xx;
1374 struct cvmx_npi_port33_instr_hdr_s cn38xx;
1375 struct cvmx_npi_port33_instr_hdr_s cn38xxp2;
1376 struct cvmx_npi_port33_instr_hdr_s cn50xx;
1377 struct cvmx_npi_port33_instr_hdr_s cn58xx;
1378 struct cvmx_npi_port33_instr_hdr_s cn58xxp1;
1381 union cvmx_npi_port34_instr_hdr {
1383 struct cvmx_npi_port34_instr_hdr_s {
1384 uint64_t reserved_44_63:20;
1387 uint64_t rparmode:2;
1389 uint64_t rskp_len:7;
1391 uint64_t use_ihdr:1;
1393 uint64_t par_mode:2;
1398 struct cvmx_npi_port34_instr_hdr_s cn38xx;
1399 struct cvmx_npi_port34_instr_hdr_s cn38xxp2;
1400 struct cvmx_npi_port34_instr_hdr_s cn58xx;
1401 struct cvmx_npi_port34_instr_hdr_s cn58xxp1;
1404 union cvmx_npi_port35_instr_hdr {
1406 struct cvmx_npi_port35_instr_hdr_s {
1407 uint64_t reserved_44_63:20;
1410 uint64_t rparmode:2;
1412 uint64_t rskp_len:7;
1414 uint64_t use_ihdr:1;
1416 uint64_t par_mode:2;
1421 struct cvmx_npi_port35_instr_hdr_s cn38xx;
1422 struct cvmx_npi_port35_instr_hdr_s cn38xxp2;
1423 struct cvmx_npi_port35_instr_hdr_s cn58xx;
1424 struct cvmx_npi_port35_instr_hdr_s cn58xxp1;
1427 union cvmx_npi_port_bp_control {
1429 struct cvmx_npi_port_bp_control_s {
1430 uint64_t reserved_8_63:56;
1434 struct cvmx_npi_port_bp_control_s cn30xx;
1435 struct cvmx_npi_port_bp_control_s cn31xx;
1436 struct cvmx_npi_port_bp_control_s cn38xx;
1437 struct cvmx_npi_port_bp_control_s cn38xxp2;
1438 struct cvmx_npi_port_bp_control_s cn50xx;
1439 struct cvmx_npi_port_bp_control_s cn58xx;
1440 struct cvmx_npi_port_bp_control_s cn58xxp1;
1443 union cvmx_npi_rsl_int_blocks {
1445 struct cvmx_npi_rsl_int_blocks_s {
1446 uint64_t reserved_32_63:32;
1449 uint64_t reserved_28_29:2;
1463 uint64_t reserved_13_14:2;
1478 struct cvmx_npi_rsl_int_blocks_cn30xx {
1479 uint64_t reserved_32_63:32;
1513 struct cvmx_npi_rsl_int_blocks_cn30xx cn31xx;
1514 struct cvmx_npi_rsl_int_blocks_cn38xx {
1515 uint64_t reserved_32_63:32;
1549 struct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2;
1550 struct cvmx_npi_rsl_int_blocks_cn50xx {
1551 uint64_t reserved_31_63:33;
1555 uint64_t reserved_24_27:4;
1558 uint64_t reserved_21_21:1;
1564 uint64_t reserved_15_15:1;
1571 uint64_t reserved_8_8:1;
1581 struct cvmx_npi_rsl_int_blocks_cn38xx cn58xx;
1582 struct cvmx_npi_rsl_int_blocks_cn38xx cn58xxp1;
1585 union cvmx_npi_size_inputx {
1587 struct cvmx_npi_size_inputx_s {
1588 uint64_t reserved_32_63:32;
1591 struct cvmx_npi_size_inputx_s cn30xx;
1592 struct cvmx_npi_size_inputx_s cn31xx;
1593 struct cvmx_npi_size_inputx_s cn38xx;
1594 struct cvmx_npi_size_inputx_s cn38xxp2;
1595 struct cvmx_npi_size_inputx_s cn50xx;
1596 struct cvmx_npi_size_inputx_s cn58xx;
1597 struct cvmx_npi_size_inputx_s cn58xxp1;
1600 union cvmx_npi_win_read_to {
1602 struct cvmx_npi_win_read_to_s {
1603 uint64_t reserved_32_63:32;
1606 struct cvmx_npi_win_read_to_s cn30xx;
1607 struct cvmx_npi_win_read_to_s cn31xx;
1608 struct cvmx_npi_win_read_to_s cn38xx;
1609 struct cvmx_npi_win_read_to_s cn38xxp2;
1610 struct cvmx_npi_win_read_to_s cn50xx;
1611 struct cvmx_npi_win_read_to_s cn58xx;
1612 struct cvmx_npi_win_read_to_s cn58xxp1;