1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2008 Cavium Networks
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_NPI_DEFS_H__
29 #define __CVMX_NPI_DEFS_H__
31 #define CVMX_NPI_BASE_ADDR_INPUT0 \
32 CVMX_ADD_IO_SEG(0x00011F0000000070ull)
33 #define CVMX_NPI_BASE_ADDR_INPUT1 \
34 CVMX_ADD_IO_SEG(0x00011F0000000080ull)
35 #define CVMX_NPI_BASE_ADDR_INPUT2 \
36 CVMX_ADD_IO_SEG(0x00011F0000000090ull)
37 #define CVMX_NPI_BASE_ADDR_INPUT3 \
38 CVMX_ADD_IO_SEG(0x00011F00000000A0ull)
39 #define CVMX_NPI_BASE_ADDR_INPUTX(offset) \
40 CVMX_ADD_IO_SEG(0x00011F0000000070ull + (((offset) & 3) * 16))
41 #define CVMX_NPI_BASE_ADDR_OUTPUT0 \
42 CVMX_ADD_IO_SEG(0x00011F00000000B8ull)
43 #define CVMX_NPI_BASE_ADDR_OUTPUT1 \
44 CVMX_ADD_IO_SEG(0x00011F00000000C0ull)
45 #define CVMX_NPI_BASE_ADDR_OUTPUT2 \
46 CVMX_ADD_IO_SEG(0x00011F00000000C8ull)
47 #define CVMX_NPI_BASE_ADDR_OUTPUT3 \
48 CVMX_ADD_IO_SEG(0x00011F00000000D0ull)
49 #define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) \
50 CVMX_ADD_IO_SEG(0x00011F00000000B8ull + (((offset) & 3) * 8))
51 #define CVMX_NPI_BIST_STATUS \
52 CVMX_ADD_IO_SEG(0x00011F00000003F8ull)
53 #define CVMX_NPI_BUFF_SIZE_OUTPUT0 \
54 CVMX_ADD_IO_SEG(0x00011F00000000E0ull)
55 #define CVMX_NPI_BUFF_SIZE_OUTPUT1 \
56 CVMX_ADD_IO_SEG(0x00011F00000000E8ull)
57 #define CVMX_NPI_BUFF_SIZE_OUTPUT2 \
58 CVMX_ADD_IO_SEG(0x00011F00000000F0ull)
59 #define CVMX_NPI_BUFF_SIZE_OUTPUT3 \
60 CVMX_ADD_IO_SEG(0x00011F00000000F8ull)
61 #define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) \
62 CVMX_ADD_IO_SEG(0x00011F00000000E0ull + (((offset) & 3) * 8))
63 #define CVMX_NPI_COMP_CTL \
64 CVMX_ADD_IO_SEG(0x00011F0000000218ull)
65 #define CVMX_NPI_CTL_STATUS \
66 CVMX_ADD_IO_SEG(0x00011F0000000010ull)
67 #define CVMX_NPI_DBG_SELECT \
68 CVMX_ADD_IO_SEG(0x00011F0000000008ull)
69 #define CVMX_NPI_DMA_CONTROL \
70 CVMX_ADD_IO_SEG(0x00011F0000000128ull)
71 #define CVMX_NPI_DMA_HIGHP_COUNTS \
72 CVMX_ADD_IO_SEG(0x00011F0000000148ull)
73 #define CVMX_NPI_DMA_HIGHP_NADDR \
74 CVMX_ADD_IO_SEG(0x00011F0000000158ull)
75 #define CVMX_NPI_DMA_LOWP_COUNTS \
76 CVMX_ADD_IO_SEG(0x00011F0000000140ull)
77 #define CVMX_NPI_DMA_LOWP_NADDR \
78 CVMX_ADD_IO_SEG(0x00011F0000000150ull)
79 #define CVMX_NPI_HIGHP_DBELL \
80 CVMX_ADD_IO_SEG(0x00011F0000000120ull)
81 #define CVMX_NPI_HIGHP_IBUFF_SADDR \
82 CVMX_ADD_IO_SEG(0x00011F0000000110ull)
83 #define CVMX_NPI_INPUT_CONTROL \
84 CVMX_ADD_IO_SEG(0x00011F0000000138ull)
85 #define CVMX_NPI_INT_ENB \
86 CVMX_ADD_IO_SEG(0x00011F0000000020ull)
87 #define CVMX_NPI_INT_SUM \
88 CVMX_ADD_IO_SEG(0x00011F0000000018ull)
89 #define CVMX_NPI_LOWP_DBELL \
90 CVMX_ADD_IO_SEG(0x00011F0000000118ull)
91 #define CVMX_NPI_LOWP_IBUFF_SADDR \
92 CVMX_ADD_IO_SEG(0x00011F0000000108ull)
93 #define CVMX_NPI_MEM_ACCESS_SUBID3 \
94 CVMX_ADD_IO_SEG(0x00011F0000000028ull)
95 #define CVMX_NPI_MEM_ACCESS_SUBID4 \
96 CVMX_ADD_IO_SEG(0x00011F0000000030ull)
97 #define CVMX_NPI_MEM_ACCESS_SUBID5 \
98 CVMX_ADD_IO_SEG(0x00011F0000000038ull)
99 #define CVMX_NPI_MEM_ACCESS_SUBID6 \
100 CVMX_ADD_IO_SEG(0x00011F0000000040ull)
101 #define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) \
102 CVMX_ADD_IO_SEG(0x00011F0000000028ull + (((offset) & 7) * 8) - 8 * 3)
103 #define CVMX_NPI_MSI_RCV \
104 (0x0000000000000190ull)
105 #define CVMX_NPI_NPI_MSI_RCV \
106 CVMX_ADD_IO_SEG(0x00011F0000001190ull)
107 #define CVMX_NPI_NUM_DESC_OUTPUT0 \
108 CVMX_ADD_IO_SEG(0x00011F0000000050ull)
109 #define CVMX_NPI_NUM_DESC_OUTPUT1 \
110 CVMX_ADD_IO_SEG(0x00011F0000000058ull)
111 #define CVMX_NPI_NUM_DESC_OUTPUT2 \
112 CVMX_ADD_IO_SEG(0x00011F0000000060ull)
113 #define CVMX_NPI_NUM_DESC_OUTPUT3 \
114 CVMX_ADD_IO_SEG(0x00011F0000000068ull)
115 #define CVMX_NPI_NUM_DESC_OUTPUTX(offset) \
116 CVMX_ADD_IO_SEG(0x00011F0000000050ull + (((offset) & 3) * 8))
117 #define CVMX_NPI_OUTPUT_CONTROL \
118 CVMX_ADD_IO_SEG(0x00011F0000000100ull)
119 #define CVMX_NPI_P0_DBPAIR_ADDR \
120 CVMX_ADD_IO_SEG(0x00011F0000000180ull)
121 #define CVMX_NPI_P0_INSTR_ADDR \
122 CVMX_ADD_IO_SEG(0x00011F00000001C0ull)
123 #define CVMX_NPI_P0_INSTR_CNTS \
124 CVMX_ADD_IO_SEG(0x00011F00000001A0ull)
125 #define CVMX_NPI_P0_PAIR_CNTS \
126 CVMX_ADD_IO_SEG(0x00011F0000000160ull)
127 #define CVMX_NPI_P1_DBPAIR_ADDR \
128 CVMX_ADD_IO_SEG(0x00011F0000000188ull)
129 #define CVMX_NPI_P1_INSTR_ADDR \
130 CVMX_ADD_IO_SEG(0x00011F00000001C8ull)
131 #define CVMX_NPI_P1_INSTR_CNTS \
132 CVMX_ADD_IO_SEG(0x00011F00000001A8ull)
133 #define CVMX_NPI_P1_PAIR_CNTS \
134 CVMX_ADD_IO_SEG(0x00011F0000000168ull)
135 #define CVMX_NPI_P2_DBPAIR_ADDR \
136 CVMX_ADD_IO_SEG(0x00011F0000000190ull)
137 #define CVMX_NPI_P2_INSTR_ADDR \
138 CVMX_ADD_IO_SEG(0x00011F00000001D0ull)
139 #define CVMX_NPI_P2_INSTR_CNTS \
140 CVMX_ADD_IO_SEG(0x00011F00000001B0ull)
141 #define CVMX_NPI_P2_PAIR_CNTS \
142 CVMX_ADD_IO_SEG(0x00011F0000000170ull)
143 #define CVMX_NPI_P3_DBPAIR_ADDR \
144 CVMX_ADD_IO_SEG(0x00011F0000000198ull)
145 #define CVMX_NPI_P3_INSTR_ADDR \
146 CVMX_ADD_IO_SEG(0x00011F00000001D8ull)
147 #define CVMX_NPI_P3_INSTR_CNTS \
148 CVMX_ADD_IO_SEG(0x00011F00000001B8ull)
149 #define CVMX_NPI_P3_PAIR_CNTS \
150 CVMX_ADD_IO_SEG(0x00011F0000000178ull)
151 #define CVMX_NPI_PCI_BAR1_INDEXX(offset) \
152 CVMX_ADD_IO_SEG(0x00011F0000001100ull + (((offset) & 31) * 4))
153 #define CVMX_NPI_PCI_BIST_REG \
154 CVMX_ADD_IO_SEG(0x00011F00000011C0ull)
155 #define CVMX_NPI_PCI_BURST_SIZE \
156 CVMX_ADD_IO_SEG(0x00011F00000000D8ull)
157 #define CVMX_NPI_PCI_CFG00 \
158 CVMX_ADD_IO_SEG(0x00011F0000001800ull)
159 #define CVMX_NPI_PCI_CFG01 \
160 CVMX_ADD_IO_SEG(0x00011F0000001804ull)
161 #define CVMX_NPI_PCI_CFG02 \
162 CVMX_ADD_IO_SEG(0x00011F0000001808ull)
163 #define CVMX_NPI_PCI_CFG03 \
164 CVMX_ADD_IO_SEG(0x00011F000000180Cull)
165 #define CVMX_NPI_PCI_CFG04 \
166 CVMX_ADD_IO_SEG(0x00011F0000001810ull)
167 #define CVMX_NPI_PCI_CFG05 \
168 CVMX_ADD_IO_SEG(0x00011F0000001814ull)
169 #define CVMX_NPI_PCI_CFG06 \
170 CVMX_ADD_IO_SEG(0x00011F0000001818ull)
171 #define CVMX_NPI_PCI_CFG07 \
172 CVMX_ADD_IO_SEG(0x00011F000000181Cull)
173 #define CVMX_NPI_PCI_CFG08 \
174 CVMX_ADD_IO_SEG(0x00011F0000001820ull)
175 #define CVMX_NPI_PCI_CFG09 \
176 CVMX_ADD_IO_SEG(0x00011F0000001824ull)
177 #define CVMX_NPI_PCI_CFG10 \
178 CVMX_ADD_IO_SEG(0x00011F0000001828ull)
179 #define CVMX_NPI_PCI_CFG11 \
180 CVMX_ADD_IO_SEG(0x00011F000000182Cull)
181 #define CVMX_NPI_PCI_CFG12 \
182 CVMX_ADD_IO_SEG(0x00011F0000001830ull)
183 #define CVMX_NPI_PCI_CFG13 \
184 CVMX_ADD_IO_SEG(0x00011F0000001834ull)
185 #define CVMX_NPI_PCI_CFG15 \
186 CVMX_ADD_IO_SEG(0x00011F000000183Cull)
187 #define CVMX_NPI_PCI_CFG16 \
188 CVMX_ADD_IO_SEG(0x00011F0000001840ull)
189 #define CVMX_NPI_PCI_CFG17 \
190 CVMX_ADD_IO_SEG(0x00011F0000001844ull)
191 #define CVMX_NPI_PCI_CFG18 \
192 CVMX_ADD_IO_SEG(0x00011F0000001848ull)
193 #define CVMX_NPI_PCI_CFG19 \
194 CVMX_ADD_IO_SEG(0x00011F000000184Cull)
195 #define CVMX_NPI_PCI_CFG20 \
196 CVMX_ADD_IO_SEG(0x00011F0000001850ull)
197 #define CVMX_NPI_PCI_CFG21 \
198 CVMX_ADD_IO_SEG(0x00011F0000001854ull)
199 #define CVMX_NPI_PCI_CFG22 \
200 CVMX_ADD_IO_SEG(0x00011F0000001858ull)
201 #define CVMX_NPI_PCI_CFG56 \
202 CVMX_ADD_IO_SEG(0x00011F00000018E0ull)
203 #define CVMX_NPI_PCI_CFG57 \
204 CVMX_ADD_IO_SEG(0x00011F00000018E4ull)
205 #define CVMX_NPI_PCI_CFG58 \
206 CVMX_ADD_IO_SEG(0x00011F00000018E8ull)
207 #define CVMX_NPI_PCI_CFG59 \
208 CVMX_ADD_IO_SEG(0x00011F00000018ECull)
209 #define CVMX_NPI_PCI_CFG60 \
210 CVMX_ADD_IO_SEG(0x00011F00000018F0ull)
211 #define CVMX_NPI_PCI_CFG61 \
212 CVMX_ADD_IO_SEG(0x00011F00000018F4ull)
213 #define CVMX_NPI_PCI_CFG62 \
214 CVMX_ADD_IO_SEG(0x00011F00000018F8ull)
215 #define CVMX_NPI_PCI_CFG63 \
216 CVMX_ADD_IO_SEG(0x00011F00000018FCull)
217 #define CVMX_NPI_PCI_CNT_REG \
218 CVMX_ADD_IO_SEG(0x00011F00000011B8ull)
219 #define CVMX_NPI_PCI_CTL_STATUS_2 \
220 CVMX_ADD_IO_SEG(0x00011F000000118Cull)
221 #define CVMX_NPI_PCI_INT_ARB_CFG \
222 CVMX_ADD_IO_SEG(0x00011F0000000130ull)
223 #define CVMX_NPI_PCI_INT_ENB2 \
224 CVMX_ADD_IO_SEG(0x00011F00000011A0ull)
225 #define CVMX_NPI_PCI_INT_SUM2 \
226 CVMX_ADD_IO_SEG(0x00011F0000001198ull)
227 #define CVMX_NPI_PCI_READ_CMD \
228 CVMX_ADD_IO_SEG(0x00011F0000000048ull)
229 #define CVMX_NPI_PCI_READ_CMD_6 \
230 CVMX_ADD_IO_SEG(0x00011F0000001180ull)
231 #define CVMX_NPI_PCI_READ_CMD_C \
232 CVMX_ADD_IO_SEG(0x00011F0000001184ull)
233 #define CVMX_NPI_PCI_READ_CMD_E \
234 CVMX_ADD_IO_SEG(0x00011F0000001188ull)
235 #define CVMX_NPI_PCI_SCM_REG \
236 CVMX_ADD_IO_SEG(0x00011F00000011A8ull)
237 #define CVMX_NPI_PCI_TSR_REG \
238 CVMX_ADD_IO_SEG(0x00011F00000011B0ull)
239 #define CVMX_NPI_PORT32_INSTR_HDR \
240 CVMX_ADD_IO_SEG(0x00011F00000001F8ull)
241 #define CVMX_NPI_PORT33_INSTR_HDR \
242 CVMX_ADD_IO_SEG(0x00011F0000000200ull)
243 #define CVMX_NPI_PORT34_INSTR_HDR \
244 CVMX_ADD_IO_SEG(0x00011F0000000208ull)
245 #define CVMX_NPI_PORT35_INSTR_HDR \
246 CVMX_ADD_IO_SEG(0x00011F0000000210ull)
247 #define CVMX_NPI_PORT_BP_CONTROL \
248 CVMX_ADD_IO_SEG(0x00011F00000001F0ull)
249 #define CVMX_NPI_PX_DBPAIR_ADDR(offset) \
250 CVMX_ADD_IO_SEG(0x00011F0000000180ull + (((offset) & 3) * 8))
251 #define CVMX_NPI_PX_INSTR_ADDR(offset) \
252 CVMX_ADD_IO_SEG(0x00011F00000001C0ull + (((offset) & 3) * 8))
253 #define CVMX_NPI_PX_INSTR_CNTS(offset) \
254 CVMX_ADD_IO_SEG(0x00011F00000001A0ull + (((offset) & 3) * 8))
255 #define CVMX_NPI_PX_PAIR_CNTS(offset) \
256 CVMX_ADD_IO_SEG(0x00011F0000000160ull + (((offset) & 3) * 8))
257 #define CVMX_NPI_RSL_INT_BLOCKS \
258 CVMX_ADD_IO_SEG(0x00011F0000000000ull)
259 #define CVMX_NPI_SIZE_INPUT0 \
260 CVMX_ADD_IO_SEG(0x00011F0000000078ull)
261 #define CVMX_NPI_SIZE_INPUT1 \
262 CVMX_ADD_IO_SEG(0x00011F0000000088ull)
263 #define CVMX_NPI_SIZE_INPUT2 \
264 CVMX_ADD_IO_SEG(0x00011F0000000098ull)
265 #define CVMX_NPI_SIZE_INPUT3 \
266 CVMX_ADD_IO_SEG(0x00011F00000000A8ull)
267 #define CVMX_NPI_SIZE_INPUTX(offset) \
268 CVMX_ADD_IO_SEG(0x00011F0000000078ull + (((offset) & 3) * 16))
269 #define CVMX_NPI_WIN_READ_TO \
270 CVMX_ADD_IO_SEG(0x00011F00000001E0ull)
272 union cvmx_npi_base_addr_inputx {
274 struct cvmx_npi_base_addr_inputx_s {
276 uint64_t reserved_0_2:3;
278 struct cvmx_npi_base_addr_inputx_s cn30xx;
279 struct cvmx_npi_base_addr_inputx_s cn31xx;
280 struct cvmx_npi_base_addr_inputx_s cn38xx;
281 struct cvmx_npi_base_addr_inputx_s cn38xxp2;
282 struct cvmx_npi_base_addr_inputx_s cn50xx;
283 struct cvmx_npi_base_addr_inputx_s cn58xx;
284 struct cvmx_npi_base_addr_inputx_s cn58xxp1;
287 union cvmx_npi_base_addr_outputx {
289 struct cvmx_npi_base_addr_outputx_s {
291 uint64_t reserved_0_2:3;
293 struct cvmx_npi_base_addr_outputx_s cn30xx;
294 struct cvmx_npi_base_addr_outputx_s cn31xx;
295 struct cvmx_npi_base_addr_outputx_s cn38xx;
296 struct cvmx_npi_base_addr_outputx_s cn38xxp2;
297 struct cvmx_npi_base_addr_outputx_s cn50xx;
298 struct cvmx_npi_base_addr_outputx_s cn58xx;
299 struct cvmx_npi_base_addr_outputx_s cn58xxp1;
302 union cvmx_npi_bist_status {
304 struct cvmx_npi_bist_status_s {
305 uint64_t reserved_20_63:44;
327 struct cvmx_npi_bist_status_cn30xx {
328 uint64_t reserved_20_63:44;
341 uint64_t reserved_5_7:3;
348 struct cvmx_npi_bist_status_s cn31xx;
349 struct cvmx_npi_bist_status_s cn38xx;
350 struct cvmx_npi_bist_status_s cn38xxp2;
351 struct cvmx_npi_bist_status_cn50xx {
352 uint64_t reserved_20_63:44;
366 uint64_t reserved_5_6:2;
373 struct cvmx_npi_bist_status_s cn58xx;
374 struct cvmx_npi_bist_status_s cn58xxp1;
377 union cvmx_npi_buff_size_outputx {
379 struct cvmx_npi_buff_size_outputx_s {
380 uint64_t reserved_23_63:41;
384 struct cvmx_npi_buff_size_outputx_s cn30xx;
385 struct cvmx_npi_buff_size_outputx_s cn31xx;
386 struct cvmx_npi_buff_size_outputx_s cn38xx;
387 struct cvmx_npi_buff_size_outputx_s cn38xxp2;
388 struct cvmx_npi_buff_size_outputx_s cn50xx;
389 struct cvmx_npi_buff_size_outputx_s cn58xx;
390 struct cvmx_npi_buff_size_outputx_s cn58xxp1;
393 union cvmx_npi_comp_ctl {
395 struct cvmx_npi_comp_ctl_s {
396 uint64_t reserved_10_63:54;
400 struct cvmx_npi_comp_ctl_s cn50xx;
401 struct cvmx_npi_comp_ctl_s cn58xx;
402 struct cvmx_npi_comp_ctl_s cn58xxp1;
405 union cvmx_npi_ctl_status {
407 struct cvmx_npi_ctl_status_s {
408 uint64_t reserved_63_63:1;
425 uint64_t reserved_37_39:3;
427 uint64_t reserved_10_31:22;
430 struct cvmx_npi_ctl_status_cn30xx {
431 uint64_t reserved_63_63:1;
434 uint64_t reserved_51_53:3;
436 uint64_t reserved_47_49:3;
438 uint64_t reserved_43_45:3;
442 uint64_t reserved_37_39:3;
444 uint64_t reserved_10_31:22;
447 struct cvmx_npi_ctl_status_cn31xx {
448 uint64_t reserved_63_63:1;
451 uint64_t reserved_52_53:2;
454 uint64_t reserved_48_49:2;
457 uint64_t reserved_44_45:2;
462 uint64_t reserved_37_39:3;
464 uint64_t reserved_10_31:22;
467 struct cvmx_npi_ctl_status_s cn38xx;
468 struct cvmx_npi_ctl_status_s cn38xxp2;
469 struct cvmx_npi_ctl_status_cn31xx cn50xx;
470 struct cvmx_npi_ctl_status_s cn58xx;
471 struct cvmx_npi_ctl_status_s cn58xxp1;
474 union cvmx_npi_dbg_select {
476 struct cvmx_npi_dbg_select_s {
477 uint64_t reserved_16_63:48;
480 struct cvmx_npi_dbg_select_s cn30xx;
481 struct cvmx_npi_dbg_select_s cn31xx;
482 struct cvmx_npi_dbg_select_s cn38xx;
483 struct cvmx_npi_dbg_select_s cn38xxp2;
484 struct cvmx_npi_dbg_select_s cn50xx;
485 struct cvmx_npi_dbg_select_s cn58xx;
486 struct cvmx_npi_dbg_select_s cn58xxp1;
489 union cvmx_npi_dma_control {
491 struct cvmx_npi_dma_control_s {
492 uint64_t reserved_36_63:28;
506 struct cvmx_npi_dma_control_s cn30xx;
507 struct cvmx_npi_dma_control_s cn31xx;
508 struct cvmx_npi_dma_control_s cn38xx;
509 struct cvmx_npi_dma_control_s cn38xxp2;
510 struct cvmx_npi_dma_control_s cn50xx;
511 struct cvmx_npi_dma_control_s cn58xx;
512 struct cvmx_npi_dma_control_s cn58xxp1;
515 union cvmx_npi_dma_highp_counts {
517 struct cvmx_npi_dma_highp_counts_s {
518 uint64_t reserved_39_63:25;
522 struct cvmx_npi_dma_highp_counts_s cn30xx;
523 struct cvmx_npi_dma_highp_counts_s cn31xx;
524 struct cvmx_npi_dma_highp_counts_s cn38xx;
525 struct cvmx_npi_dma_highp_counts_s cn38xxp2;
526 struct cvmx_npi_dma_highp_counts_s cn50xx;
527 struct cvmx_npi_dma_highp_counts_s cn58xx;
528 struct cvmx_npi_dma_highp_counts_s cn58xxp1;
531 union cvmx_npi_dma_highp_naddr {
533 struct cvmx_npi_dma_highp_naddr_s {
534 uint64_t reserved_40_63:24;
538 struct cvmx_npi_dma_highp_naddr_s cn30xx;
539 struct cvmx_npi_dma_highp_naddr_s cn31xx;
540 struct cvmx_npi_dma_highp_naddr_s cn38xx;
541 struct cvmx_npi_dma_highp_naddr_s cn38xxp2;
542 struct cvmx_npi_dma_highp_naddr_s cn50xx;
543 struct cvmx_npi_dma_highp_naddr_s cn58xx;
544 struct cvmx_npi_dma_highp_naddr_s cn58xxp1;
547 union cvmx_npi_dma_lowp_counts {
549 struct cvmx_npi_dma_lowp_counts_s {
550 uint64_t reserved_39_63:25;
554 struct cvmx_npi_dma_lowp_counts_s cn30xx;
555 struct cvmx_npi_dma_lowp_counts_s cn31xx;
556 struct cvmx_npi_dma_lowp_counts_s cn38xx;
557 struct cvmx_npi_dma_lowp_counts_s cn38xxp2;
558 struct cvmx_npi_dma_lowp_counts_s cn50xx;
559 struct cvmx_npi_dma_lowp_counts_s cn58xx;
560 struct cvmx_npi_dma_lowp_counts_s cn58xxp1;
563 union cvmx_npi_dma_lowp_naddr {
565 struct cvmx_npi_dma_lowp_naddr_s {
566 uint64_t reserved_40_63:24;
570 struct cvmx_npi_dma_lowp_naddr_s cn30xx;
571 struct cvmx_npi_dma_lowp_naddr_s cn31xx;
572 struct cvmx_npi_dma_lowp_naddr_s cn38xx;
573 struct cvmx_npi_dma_lowp_naddr_s cn38xxp2;
574 struct cvmx_npi_dma_lowp_naddr_s cn50xx;
575 struct cvmx_npi_dma_lowp_naddr_s cn58xx;
576 struct cvmx_npi_dma_lowp_naddr_s cn58xxp1;
579 union cvmx_npi_highp_dbell {
581 struct cvmx_npi_highp_dbell_s {
582 uint64_t reserved_16_63:48;
585 struct cvmx_npi_highp_dbell_s cn30xx;
586 struct cvmx_npi_highp_dbell_s cn31xx;
587 struct cvmx_npi_highp_dbell_s cn38xx;
588 struct cvmx_npi_highp_dbell_s cn38xxp2;
589 struct cvmx_npi_highp_dbell_s cn50xx;
590 struct cvmx_npi_highp_dbell_s cn58xx;
591 struct cvmx_npi_highp_dbell_s cn58xxp1;
594 union cvmx_npi_highp_ibuff_saddr {
596 struct cvmx_npi_highp_ibuff_saddr_s {
597 uint64_t reserved_36_63:28;
600 struct cvmx_npi_highp_ibuff_saddr_s cn30xx;
601 struct cvmx_npi_highp_ibuff_saddr_s cn31xx;
602 struct cvmx_npi_highp_ibuff_saddr_s cn38xx;
603 struct cvmx_npi_highp_ibuff_saddr_s cn38xxp2;
604 struct cvmx_npi_highp_ibuff_saddr_s cn50xx;
605 struct cvmx_npi_highp_ibuff_saddr_s cn58xx;
606 struct cvmx_npi_highp_ibuff_saddr_s cn58xxp1;
609 union cvmx_npi_input_control {
611 struct cvmx_npi_input_control_s {
612 uint64_t reserved_23_63:41;
623 struct cvmx_npi_input_control_cn30xx {
624 uint64_t reserved_22_63:42;
634 struct cvmx_npi_input_control_cn30xx cn31xx;
635 struct cvmx_npi_input_control_s cn38xx;
636 struct cvmx_npi_input_control_cn30xx cn38xxp2;
637 struct cvmx_npi_input_control_s cn50xx;
638 struct cvmx_npi_input_control_s cn58xx;
639 struct cvmx_npi_input_control_s cn58xxp1;
642 union cvmx_npi_int_enb {
644 struct cvmx_npi_int_enb_s {
645 uint64_t reserved_62_63:2;
709 struct cvmx_npi_int_enb_cn30xx {
710 uint64_t reserved_62_63:2;
734 uint64_t reserved_36_38:3;
736 uint64_t reserved_32_34:3;
738 uint64_t reserved_28_30:3;
740 uint64_t reserved_24_26:3;
742 uint64_t reserved_20_22:3;
744 uint64_t reserved_16_18:3;
746 uint64_t reserved_12_14:3;
748 uint64_t reserved_8_10:3;
750 uint64_t reserved_4_6:3;
756 struct cvmx_npi_int_enb_cn31xx {
757 uint64_t reserved_62_63:2;
781 uint64_t reserved_37_38:2;
784 uint64_t reserved_33_34:2;
787 uint64_t reserved_29_30:2;
790 uint64_t reserved_25_26:2;
793 uint64_t reserved_21_22:2;
796 uint64_t reserved_17_18:2;
799 uint64_t reserved_13_14:2;
802 uint64_t reserved_9_10:2;
805 uint64_t reserved_5_6:2;
812 struct cvmx_npi_int_enb_s cn38xx;
813 struct cvmx_npi_int_enb_cn38xxp2 {
814 uint64_t reserved_42_63:22;
858 struct cvmx_npi_int_enb_cn31xx cn50xx;
859 struct cvmx_npi_int_enb_s cn58xx;
860 struct cvmx_npi_int_enb_s cn58xxp1;
863 union cvmx_npi_int_sum {
865 struct cvmx_npi_int_sum_s {
866 uint64_t reserved_62_63:2;
930 struct cvmx_npi_int_sum_cn30xx {
931 uint64_t reserved_62_63:2;
955 uint64_t reserved_36_38:3;
957 uint64_t reserved_32_34:3;
959 uint64_t reserved_28_30:3;
961 uint64_t reserved_24_26:3;
963 uint64_t reserved_20_22:3;
965 uint64_t reserved_16_18:3;
967 uint64_t reserved_12_14:3;
969 uint64_t reserved_8_10:3;
971 uint64_t reserved_4_6:3;
977 struct cvmx_npi_int_sum_cn31xx {
978 uint64_t reserved_62_63:2;
1002 uint64_t reserved_37_38:2;
1003 uint64_t i1_pperr:1;
1004 uint64_t i0_pperr:1;
1005 uint64_t reserved_33_34:2;
1006 uint64_t p1_ptout:1;
1007 uint64_t p0_ptout:1;
1008 uint64_t reserved_29_30:2;
1009 uint64_t p1_pperr:1;
1010 uint64_t p0_pperr:1;
1011 uint64_t reserved_25_26:2;
1012 uint64_t g1_rtout:1;
1013 uint64_t g0_rtout:1;
1014 uint64_t reserved_21_22:2;
1017 uint64_t reserved_17_18:2;
1018 uint64_t p1_rtout:1;
1019 uint64_t p0_rtout:1;
1020 uint64_t reserved_13_14:2;
1021 uint64_t i1_overf:1;
1022 uint64_t i0_overf:1;
1023 uint64_t reserved_9_10:2;
1024 uint64_t i1_rtout:1;
1025 uint64_t i0_rtout:1;
1026 uint64_t reserved_5_6:2;
1027 uint64_t po1_2sml:1;
1028 uint64_t po0_2sml:1;
1033 struct cvmx_npi_int_sum_s cn38xx;
1034 struct cvmx_npi_int_sum_cn38xxp2 {
1035 uint64_t reserved_42_63:22;
1039 uint64_t i3_pperr:1;
1040 uint64_t i2_pperr:1;
1041 uint64_t i1_pperr:1;
1042 uint64_t i0_pperr:1;
1043 uint64_t p3_ptout:1;
1044 uint64_t p2_ptout:1;
1045 uint64_t p1_ptout:1;
1046 uint64_t p0_ptout:1;
1047 uint64_t p3_pperr:1;
1048 uint64_t p2_pperr:1;
1049 uint64_t p1_pperr:1;
1050 uint64_t p0_pperr:1;
1051 uint64_t g3_rtout:1;
1052 uint64_t g2_rtout:1;
1053 uint64_t g1_rtout:1;
1054 uint64_t g0_rtout:1;
1059 uint64_t p3_rtout:1;
1060 uint64_t p2_rtout:1;
1061 uint64_t p1_rtout:1;
1062 uint64_t p0_rtout:1;
1063 uint64_t i3_overf:1;
1064 uint64_t i2_overf:1;
1065 uint64_t i1_overf:1;
1066 uint64_t i0_overf:1;
1067 uint64_t i3_rtout:1;
1068 uint64_t i2_rtout:1;
1069 uint64_t i1_rtout:1;
1070 uint64_t i0_rtout:1;
1071 uint64_t po3_2sml:1;
1072 uint64_t po2_2sml:1;
1073 uint64_t po1_2sml:1;
1074 uint64_t po0_2sml:1;
1079 struct cvmx_npi_int_sum_cn31xx cn50xx;
1080 struct cvmx_npi_int_sum_s cn58xx;
1081 struct cvmx_npi_int_sum_s cn58xxp1;
1084 union cvmx_npi_lowp_dbell {
1086 struct cvmx_npi_lowp_dbell_s {
1087 uint64_t reserved_16_63:48;
1090 struct cvmx_npi_lowp_dbell_s cn30xx;
1091 struct cvmx_npi_lowp_dbell_s cn31xx;
1092 struct cvmx_npi_lowp_dbell_s cn38xx;
1093 struct cvmx_npi_lowp_dbell_s cn38xxp2;
1094 struct cvmx_npi_lowp_dbell_s cn50xx;
1095 struct cvmx_npi_lowp_dbell_s cn58xx;
1096 struct cvmx_npi_lowp_dbell_s cn58xxp1;
1099 union cvmx_npi_lowp_ibuff_saddr {
1101 struct cvmx_npi_lowp_ibuff_saddr_s {
1102 uint64_t reserved_36_63:28;
1105 struct cvmx_npi_lowp_ibuff_saddr_s cn30xx;
1106 struct cvmx_npi_lowp_ibuff_saddr_s cn31xx;
1107 struct cvmx_npi_lowp_ibuff_saddr_s cn38xx;
1108 struct cvmx_npi_lowp_ibuff_saddr_s cn38xxp2;
1109 struct cvmx_npi_lowp_ibuff_saddr_s cn50xx;
1110 struct cvmx_npi_lowp_ibuff_saddr_s cn58xx;
1111 struct cvmx_npi_lowp_ibuff_saddr_s cn58xxp1;
1114 union cvmx_npi_mem_access_subidx {
1116 struct cvmx_npi_mem_access_subidx_s {
1117 uint64_t reserved_38_63:26;
1128 struct cvmx_npi_mem_access_subidx_s cn30xx;
1129 struct cvmx_npi_mem_access_subidx_cn31xx {
1130 uint64_t reserved_36_63:28;
1139 struct cvmx_npi_mem_access_subidx_s cn38xx;
1140 struct cvmx_npi_mem_access_subidx_cn31xx cn38xxp2;
1141 struct cvmx_npi_mem_access_subidx_s cn50xx;
1142 struct cvmx_npi_mem_access_subidx_s cn58xx;
1143 struct cvmx_npi_mem_access_subidx_s cn58xxp1;
1146 union cvmx_npi_msi_rcv {
1148 struct cvmx_npi_msi_rcv_s {
1149 uint64_t int_vec:64;
1151 struct cvmx_npi_msi_rcv_s cn30xx;
1152 struct cvmx_npi_msi_rcv_s cn31xx;
1153 struct cvmx_npi_msi_rcv_s cn38xx;
1154 struct cvmx_npi_msi_rcv_s cn38xxp2;
1155 struct cvmx_npi_msi_rcv_s cn50xx;
1156 struct cvmx_npi_msi_rcv_s cn58xx;
1157 struct cvmx_npi_msi_rcv_s cn58xxp1;
1160 union cvmx_npi_num_desc_outputx {
1162 struct cvmx_npi_num_desc_outputx_s {
1163 uint64_t reserved_32_63:32;
1166 struct cvmx_npi_num_desc_outputx_s cn30xx;
1167 struct cvmx_npi_num_desc_outputx_s cn31xx;
1168 struct cvmx_npi_num_desc_outputx_s cn38xx;
1169 struct cvmx_npi_num_desc_outputx_s cn38xxp2;
1170 struct cvmx_npi_num_desc_outputx_s cn50xx;
1171 struct cvmx_npi_num_desc_outputx_s cn58xx;
1172 struct cvmx_npi_num_desc_outputx_s cn58xxp1;
1175 union cvmx_npi_output_control {
1177 struct cvmx_npi_output_control_s {
1178 uint64_t reserved_49_63:15;
1180 uint64_t p3_bmode:1;
1181 uint64_t p2_bmode:1;
1182 uint64_t p1_bmode:1;
1183 uint64_t p0_bmode:1;
1200 uint64_t reserved_20_23:4;
1218 struct cvmx_npi_output_control_cn30xx {
1219 uint64_t reserved_45_63:19;
1220 uint64_t p0_bmode:1;
1221 uint64_t reserved_32_43:12;
1225 uint64_t reserved_25_27:3;
1227 uint64_t reserved_17_23:7;
1229 uint64_t reserved_4_15:12;
1234 struct cvmx_npi_output_control_cn31xx {
1235 uint64_t reserved_46_63:18;
1236 uint64_t p1_bmode:1;
1237 uint64_t p0_bmode:1;
1238 uint64_t reserved_36_43:8;
1245 uint64_t reserved_26_27:2;
1248 uint64_t reserved_18_23:6;
1251 uint64_t reserved_8_15:8;
1259 struct cvmx_npi_output_control_s cn38xx;
1260 struct cvmx_npi_output_control_cn38xxp2 {
1261 uint64_t reserved_48_63:16;
1262 uint64_t p3_bmode:1;
1263 uint64_t p2_bmode:1;
1264 uint64_t p1_bmode:1;
1265 uint64_t p0_bmode:1;
1282 uint64_t reserved_20_23:4;
1300 struct cvmx_npi_output_control_cn50xx {
1301 uint64_t reserved_49_63:15;
1303 uint64_t reserved_46_47:2;
1304 uint64_t p1_bmode:1;
1305 uint64_t p0_bmode:1;
1306 uint64_t reserved_36_43:8;
1313 uint64_t reserved_26_27:2;
1316 uint64_t reserved_18_23:6;
1319 uint64_t reserved_8_15:8;
1327 struct cvmx_npi_output_control_s cn58xx;
1328 struct cvmx_npi_output_control_s cn58xxp1;
1331 union cvmx_npi_px_dbpair_addr {
1333 struct cvmx_npi_px_dbpair_addr_s {
1334 uint64_t reserved_63_63:1;
1338 struct cvmx_npi_px_dbpair_addr_s cn30xx;
1339 struct cvmx_npi_px_dbpair_addr_s cn31xx;
1340 struct cvmx_npi_px_dbpair_addr_s cn38xx;
1341 struct cvmx_npi_px_dbpair_addr_s cn38xxp2;
1342 struct cvmx_npi_px_dbpair_addr_s cn50xx;
1343 struct cvmx_npi_px_dbpair_addr_s cn58xx;
1344 struct cvmx_npi_px_dbpair_addr_s cn58xxp1;
1347 union cvmx_npi_px_instr_addr {
1349 struct cvmx_npi_px_instr_addr_s {
1353 struct cvmx_npi_px_instr_addr_s cn30xx;
1354 struct cvmx_npi_px_instr_addr_s cn31xx;
1355 struct cvmx_npi_px_instr_addr_s cn38xx;
1356 struct cvmx_npi_px_instr_addr_s cn38xxp2;
1357 struct cvmx_npi_px_instr_addr_s cn50xx;
1358 struct cvmx_npi_px_instr_addr_s cn58xx;
1359 struct cvmx_npi_px_instr_addr_s cn58xxp1;
1362 union cvmx_npi_px_instr_cnts {
1364 struct cvmx_npi_px_instr_cnts_s {
1365 uint64_t reserved_38_63:26;
1369 struct cvmx_npi_px_instr_cnts_s cn30xx;
1370 struct cvmx_npi_px_instr_cnts_s cn31xx;
1371 struct cvmx_npi_px_instr_cnts_s cn38xx;
1372 struct cvmx_npi_px_instr_cnts_s cn38xxp2;
1373 struct cvmx_npi_px_instr_cnts_s cn50xx;
1374 struct cvmx_npi_px_instr_cnts_s cn58xx;
1375 struct cvmx_npi_px_instr_cnts_s cn58xxp1;
1378 union cvmx_npi_px_pair_cnts {
1380 struct cvmx_npi_px_pair_cnts_s {
1381 uint64_t reserved_37_63:27;
1385 struct cvmx_npi_px_pair_cnts_s cn30xx;
1386 struct cvmx_npi_px_pair_cnts_s cn31xx;
1387 struct cvmx_npi_px_pair_cnts_s cn38xx;
1388 struct cvmx_npi_px_pair_cnts_s cn38xxp2;
1389 struct cvmx_npi_px_pair_cnts_s cn50xx;
1390 struct cvmx_npi_px_pair_cnts_s cn58xx;
1391 struct cvmx_npi_px_pair_cnts_s cn58xxp1;
1394 union cvmx_npi_pci_burst_size {
1396 struct cvmx_npi_pci_burst_size_s {
1397 uint64_t reserved_14_63:50;
1401 struct cvmx_npi_pci_burst_size_s cn30xx;
1402 struct cvmx_npi_pci_burst_size_s cn31xx;
1403 struct cvmx_npi_pci_burst_size_s cn38xx;
1404 struct cvmx_npi_pci_burst_size_s cn38xxp2;
1405 struct cvmx_npi_pci_burst_size_s cn50xx;
1406 struct cvmx_npi_pci_burst_size_s cn58xx;
1407 struct cvmx_npi_pci_burst_size_s cn58xxp1;
1410 union cvmx_npi_pci_int_arb_cfg {
1412 struct cvmx_npi_pci_int_arb_cfg_s {
1413 uint64_t reserved_13_63:51;
1414 uint64_t hostmode:1;
1416 uint64_t reserved_5_7:3;
1418 uint64_t park_mod:1;
1419 uint64_t park_dev:3;
1421 struct cvmx_npi_pci_int_arb_cfg_cn30xx {
1422 uint64_t reserved_5_63:59;
1424 uint64_t park_mod:1;
1425 uint64_t park_dev:3;
1427 struct cvmx_npi_pci_int_arb_cfg_cn30xx cn31xx;
1428 struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xx;
1429 struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xxp2;
1430 struct cvmx_npi_pci_int_arb_cfg_s cn50xx;
1431 struct cvmx_npi_pci_int_arb_cfg_s cn58xx;
1432 struct cvmx_npi_pci_int_arb_cfg_s cn58xxp1;
1435 union cvmx_npi_pci_read_cmd {
1437 struct cvmx_npi_pci_read_cmd_s {
1438 uint64_t reserved_11_63:53;
1439 uint64_t cmd_size:11;
1441 struct cvmx_npi_pci_read_cmd_s cn30xx;
1442 struct cvmx_npi_pci_read_cmd_s cn31xx;
1443 struct cvmx_npi_pci_read_cmd_s cn38xx;
1444 struct cvmx_npi_pci_read_cmd_s cn38xxp2;
1445 struct cvmx_npi_pci_read_cmd_s cn50xx;
1446 struct cvmx_npi_pci_read_cmd_s cn58xx;
1447 struct cvmx_npi_pci_read_cmd_s cn58xxp1;
1450 union cvmx_npi_port32_instr_hdr {
1452 struct cvmx_npi_port32_instr_hdr_s {
1453 uint64_t reserved_44_63:20;
1456 uint64_t rparmode:2;
1458 uint64_t rskp_len:7;
1460 uint64_t use_ihdr:1;
1462 uint64_t par_mode:2;
1467 struct cvmx_npi_port32_instr_hdr_s cn30xx;
1468 struct cvmx_npi_port32_instr_hdr_s cn31xx;
1469 struct cvmx_npi_port32_instr_hdr_s cn38xx;
1470 struct cvmx_npi_port32_instr_hdr_s cn38xxp2;
1471 struct cvmx_npi_port32_instr_hdr_s cn50xx;
1472 struct cvmx_npi_port32_instr_hdr_s cn58xx;
1473 struct cvmx_npi_port32_instr_hdr_s cn58xxp1;
1476 union cvmx_npi_port33_instr_hdr {
1478 struct cvmx_npi_port33_instr_hdr_s {
1479 uint64_t reserved_44_63:20;
1482 uint64_t rparmode:2;
1484 uint64_t rskp_len:7;
1486 uint64_t use_ihdr:1;
1488 uint64_t par_mode:2;
1493 struct cvmx_npi_port33_instr_hdr_s cn31xx;
1494 struct cvmx_npi_port33_instr_hdr_s cn38xx;
1495 struct cvmx_npi_port33_instr_hdr_s cn38xxp2;
1496 struct cvmx_npi_port33_instr_hdr_s cn50xx;
1497 struct cvmx_npi_port33_instr_hdr_s cn58xx;
1498 struct cvmx_npi_port33_instr_hdr_s cn58xxp1;
1501 union cvmx_npi_port34_instr_hdr {
1503 struct cvmx_npi_port34_instr_hdr_s {
1504 uint64_t reserved_44_63:20;
1507 uint64_t rparmode:2;
1509 uint64_t rskp_len:7;
1511 uint64_t use_ihdr:1;
1513 uint64_t par_mode:2;
1518 struct cvmx_npi_port34_instr_hdr_s cn38xx;
1519 struct cvmx_npi_port34_instr_hdr_s cn38xxp2;
1520 struct cvmx_npi_port34_instr_hdr_s cn58xx;
1521 struct cvmx_npi_port34_instr_hdr_s cn58xxp1;
1524 union cvmx_npi_port35_instr_hdr {
1526 struct cvmx_npi_port35_instr_hdr_s {
1527 uint64_t reserved_44_63:20;
1530 uint64_t rparmode:2;
1532 uint64_t rskp_len:7;
1534 uint64_t use_ihdr:1;
1536 uint64_t par_mode:2;
1541 struct cvmx_npi_port35_instr_hdr_s cn38xx;
1542 struct cvmx_npi_port35_instr_hdr_s cn38xxp2;
1543 struct cvmx_npi_port35_instr_hdr_s cn58xx;
1544 struct cvmx_npi_port35_instr_hdr_s cn58xxp1;
1547 union cvmx_npi_port_bp_control {
1549 struct cvmx_npi_port_bp_control_s {
1550 uint64_t reserved_8_63:56;
1554 struct cvmx_npi_port_bp_control_s cn30xx;
1555 struct cvmx_npi_port_bp_control_s cn31xx;
1556 struct cvmx_npi_port_bp_control_s cn38xx;
1557 struct cvmx_npi_port_bp_control_s cn38xxp2;
1558 struct cvmx_npi_port_bp_control_s cn50xx;
1559 struct cvmx_npi_port_bp_control_s cn58xx;
1560 struct cvmx_npi_port_bp_control_s cn58xxp1;
1563 union cvmx_npi_rsl_int_blocks {
1565 struct cvmx_npi_rsl_int_blocks_s {
1566 uint64_t reserved_32_63:32;
1569 uint64_t reserved_28_29:2;
1583 uint64_t reserved_13_14:2;
1598 struct cvmx_npi_rsl_int_blocks_cn30xx {
1599 uint64_t reserved_32_63:32;
1633 struct cvmx_npi_rsl_int_blocks_cn30xx cn31xx;
1634 struct cvmx_npi_rsl_int_blocks_cn38xx {
1635 uint64_t reserved_32_63:32;
1669 struct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2;
1670 struct cvmx_npi_rsl_int_blocks_cn50xx {
1671 uint64_t reserved_31_63:33;
1675 uint64_t reserved_24_27:4;
1678 uint64_t reserved_21_21:1;
1684 uint64_t reserved_15_15:1;
1691 uint64_t reserved_8_8:1;
1701 struct cvmx_npi_rsl_int_blocks_cn38xx cn58xx;
1702 struct cvmx_npi_rsl_int_blocks_cn38xx cn58xxp1;
1705 union cvmx_npi_size_inputx {
1707 struct cvmx_npi_size_inputx_s {
1708 uint64_t reserved_32_63:32;
1711 struct cvmx_npi_size_inputx_s cn30xx;
1712 struct cvmx_npi_size_inputx_s cn31xx;
1713 struct cvmx_npi_size_inputx_s cn38xx;
1714 struct cvmx_npi_size_inputx_s cn38xxp2;
1715 struct cvmx_npi_size_inputx_s cn50xx;
1716 struct cvmx_npi_size_inputx_s cn58xx;
1717 struct cvmx_npi_size_inputx_s cn58xxp1;
1720 union cvmx_npi_win_read_to {
1722 struct cvmx_npi_win_read_to_s {
1723 uint64_t reserved_32_63:32;
1726 struct cvmx_npi_win_read_to_s cn30xx;
1727 struct cvmx_npi_win_read_to_s cn31xx;
1728 struct cvmx_npi_win_read_to_s cn38xx;
1729 struct cvmx_npi_win_read_to_s cn38xxp2;
1730 struct cvmx_npi_win_read_to_s cn50xx;
1731 struct cvmx_npi_win_read_to_s cn58xx;
1732 struct cvmx_npi_win_read_to_s cn58xxp1;