1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2012 Cavium Networks
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_PESCX_DEFS_H__
29 #define __CVMX_PESCX_DEFS_H__
31 #define CVMX_PESCX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1) * 0x8000000ull)
32 #define CVMX_PESCX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000418ull) + ((block_id) & 1) * 0x8000000ull)
33 #define CVMX_PESCX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000030ull) + ((block_id) & 1) * 0x8000000ull)
34 #define CVMX_PESCX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000028ull) + ((block_id) & 1) * 0x8000000ull)
35 #define CVMX_PESCX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000098ull) + ((block_id) & 1) * 0x8000000ull)
36 #define CVMX_PESCX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000000ull) + ((block_id) & 1) * 0x8000000ull)
37 #define CVMX_PESCX_CTL_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000400ull) + ((block_id) & 1) * 0x8000000ull)
38 #define CVMX_PESCX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000008ull) + ((block_id) & 1) * 0x8000000ull)
39 #define CVMX_PESCX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C80000A0ull) + ((block_id) & 1) * 0x8000000ull)
40 #define CVMX_PESCX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000020ull) + ((block_id) & 1) * 0x8000000ull)
41 #define CVMX_PESCX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000080ull) + ((block_id) & 1) * 0x8000000ull)
42 #define CVMX_PESCX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000088ull) + ((block_id) & 1) * 0x8000000ull)
43 #define CVMX_PESCX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000090ull) + ((block_id) & 1) * 0x8000000ull)
44 #define CVMX_PESCX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16)
45 #define CVMX_PESCX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16)
46 #define CVMX_PESCX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000038ull) + ((block_id) & 1) * 0x8000000ull)
48 union cvmx_pescx_bist_status {
50 struct cvmx_pescx_bist_status_s {
51 #ifdef __BIG_ENDIAN_BITFIELD
52 uint64_t reserved_13_63:51;
80 uint64_t reserved_13_63:51;
83 struct cvmx_pescx_bist_status_s cn52xx;
84 struct cvmx_pescx_bist_status_cn52xxp1 {
85 #ifdef __BIG_ENDIAN_BITFIELD
86 uint64_t reserved_12_63:52;
112 uint64_t reserved_12_63:52;
115 struct cvmx_pescx_bist_status_s cn56xx;
116 struct cvmx_pescx_bist_status_cn52xxp1 cn56xxp1;
119 union cvmx_pescx_bist_status2 {
121 struct cvmx_pescx_bist_status2_s {
122 #ifdef __BIG_ENDIAN_BITFIELD
123 uint64_t reserved_14_63:50;
153 uint64_t reserved_14_63:50;
156 struct cvmx_pescx_bist_status2_s cn52xx;
157 struct cvmx_pescx_bist_status2_s cn52xxp1;
158 struct cvmx_pescx_bist_status2_s cn56xx;
159 struct cvmx_pescx_bist_status2_s cn56xxp1;
162 union cvmx_pescx_cfg_rd {
164 struct cvmx_pescx_cfg_rd_s {
165 #ifdef __BIG_ENDIAN_BITFIELD
173 struct cvmx_pescx_cfg_rd_s cn52xx;
174 struct cvmx_pescx_cfg_rd_s cn52xxp1;
175 struct cvmx_pescx_cfg_rd_s cn56xx;
176 struct cvmx_pescx_cfg_rd_s cn56xxp1;
179 union cvmx_pescx_cfg_wr {
181 struct cvmx_pescx_cfg_wr_s {
182 #ifdef __BIG_ENDIAN_BITFIELD
190 struct cvmx_pescx_cfg_wr_s cn52xx;
191 struct cvmx_pescx_cfg_wr_s cn52xxp1;
192 struct cvmx_pescx_cfg_wr_s cn56xx;
193 struct cvmx_pescx_cfg_wr_s cn56xxp1;
196 union cvmx_pescx_cpl_lut_valid {
198 struct cvmx_pescx_cpl_lut_valid_s {
199 #ifdef __BIG_ENDIAN_BITFIELD
200 uint64_t reserved_32_63:32;
204 uint64_t reserved_32_63:32;
207 struct cvmx_pescx_cpl_lut_valid_s cn52xx;
208 struct cvmx_pescx_cpl_lut_valid_s cn52xxp1;
209 struct cvmx_pescx_cpl_lut_valid_s cn56xx;
210 struct cvmx_pescx_cpl_lut_valid_s cn56xxp1;
213 union cvmx_pescx_ctl_status {
215 struct cvmx_pescx_ctl_status_s {
216 #ifdef __BIG_ENDIAN_BITFIELD
217 uint64_t reserved_28_63:36;
225 uint64_t reserved_7_8:2;
230 uint64_t reserved_2_2:1;
236 uint64_t reserved_2_2:1;
241 uint64_t reserved_7_8:2;
249 uint64_t reserved_28_63:36;
252 struct cvmx_pescx_ctl_status_s cn52xx;
253 struct cvmx_pescx_ctl_status_s cn52xxp1;
254 struct cvmx_pescx_ctl_status_cn56xx {
255 #ifdef __BIG_ENDIAN_BITFIELD
256 uint64_t reserved_28_63:36;
260 uint64_t reserved_12_12:1;
264 uint64_t reserved_7_8:2;
269 uint64_t reserved_2_2:1;
275 uint64_t reserved_2_2:1;
280 uint64_t reserved_7_8:2;
284 uint64_t reserved_12_12:1;
288 uint64_t reserved_28_63:36;
291 struct cvmx_pescx_ctl_status_cn56xx cn56xxp1;
294 union cvmx_pescx_ctl_status2 {
296 struct cvmx_pescx_ctl_status2_s {
297 #ifdef __BIG_ENDIAN_BITFIELD
298 uint64_t reserved_2_63:62;
304 uint64_t reserved_2_63:62;
307 struct cvmx_pescx_ctl_status2_s cn52xx;
308 struct cvmx_pescx_ctl_status2_cn52xxp1 {
309 #ifdef __BIG_ENDIAN_BITFIELD
310 uint64_t reserved_1_63:63;
314 uint64_t reserved_1_63:63;
317 struct cvmx_pescx_ctl_status2_s cn56xx;
318 struct cvmx_pescx_ctl_status2_cn52xxp1 cn56xxp1;
321 union cvmx_pescx_dbg_info {
323 struct cvmx_pescx_dbg_info_s {
324 #ifdef __BIG_ENDIAN_BITFIELD
325 uint64_t reserved_31_63:33;
389 uint64_t reserved_31_63:33;
392 struct cvmx_pescx_dbg_info_s cn52xx;
393 struct cvmx_pescx_dbg_info_s cn52xxp1;
394 struct cvmx_pescx_dbg_info_s cn56xx;
395 struct cvmx_pescx_dbg_info_s cn56xxp1;
398 union cvmx_pescx_dbg_info_en {
400 struct cvmx_pescx_dbg_info_en_s {
401 #ifdef __BIG_ENDIAN_BITFIELD
402 uint64_t reserved_31_63:33;
466 uint64_t reserved_31_63:33;
469 struct cvmx_pescx_dbg_info_en_s cn52xx;
470 struct cvmx_pescx_dbg_info_en_s cn52xxp1;
471 struct cvmx_pescx_dbg_info_en_s cn56xx;
472 struct cvmx_pescx_dbg_info_en_s cn56xxp1;
475 union cvmx_pescx_diag_status {
477 struct cvmx_pescx_diag_status_s {
478 #ifdef __BIG_ENDIAN_BITFIELD
479 uint64_t reserved_4_63:60;
489 uint64_t reserved_4_63:60;
492 struct cvmx_pescx_diag_status_s cn52xx;
493 struct cvmx_pescx_diag_status_s cn52xxp1;
494 struct cvmx_pescx_diag_status_s cn56xx;
495 struct cvmx_pescx_diag_status_s cn56xxp1;
498 union cvmx_pescx_p2n_bar0_start {
500 struct cvmx_pescx_p2n_bar0_start_s {
501 #ifdef __BIG_ENDIAN_BITFIELD
503 uint64_t reserved_0_13:14;
505 uint64_t reserved_0_13:14;
509 struct cvmx_pescx_p2n_bar0_start_s cn52xx;
510 struct cvmx_pescx_p2n_bar0_start_s cn52xxp1;
511 struct cvmx_pescx_p2n_bar0_start_s cn56xx;
512 struct cvmx_pescx_p2n_bar0_start_s cn56xxp1;
515 union cvmx_pescx_p2n_bar1_start {
517 struct cvmx_pescx_p2n_bar1_start_s {
518 #ifdef __BIG_ENDIAN_BITFIELD
520 uint64_t reserved_0_25:26;
522 uint64_t reserved_0_25:26;
526 struct cvmx_pescx_p2n_bar1_start_s cn52xx;
527 struct cvmx_pescx_p2n_bar1_start_s cn52xxp1;
528 struct cvmx_pescx_p2n_bar1_start_s cn56xx;
529 struct cvmx_pescx_p2n_bar1_start_s cn56xxp1;
532 union cvmx_pescx_p2n_bar2_start {
534 struct cvmx_pescx_p2n_bar2_start_s {
535 #ifdef __BIG_ENDIAN_BITFIELD
537 uint64_t reserved_0_38:39;
539 uint64_t reserved_0_38:39;
543 struct cvmx_pescx_p2n_bar2_start_s cn52xx;
544 struct cvmx_pescx_p2n_bar2_start_s cn52xxp1;
545 struct cvmx_pescx_p2n_bar2_start_s cn56xx;
546 struct cvmx_pescx_p2n_bar2_start_s cn56xxp1;
549 union cvmx_pescx_p2p_barx_end {
551 struct cvmx_pescx_p2p_barx_end_s {
552 #ifdef __BIG_ENDIAN_BITFIELD
554 uint64_t reserved_0_11:12;
556 uint64_t reserved_0_11:12;
560 struct cvmx_pescx_p2p_barx_end_s cn52xx;
561 struct cvmx_pescx_p2p_barx_end_s cn52xxp1;
562 struct cvmx_pescx_p2p_barx_end_s cn56xx;
563 struct cvmx_pescx_p2p_barx_end_s cn56xxp1;
566 union cvmx_pescx_p2p_barx_start {
568 struct cvmx_pescx_p2p_barx_start_s {
569 #ifdef __BIG_ENDIAN_BITFIELD
571 uint64_t reserved_0_11:12;
573 uint64_t reserved_0_11:12;
577 struct cvmx_pescx_p2p_barx_start_s cn52xx;
578 struct cvmx_pescx_p2p_barx_start_s cn52xxp1;
579 struct cvmx_pescx_p2p_barx_start_s cn56xx;
580 struct cvmx_pescx_p2p_barx_start_s cn56xxp1;
583 union cvmx_pescx_tlp_credits {
585 struct cvmx_pescx_tlp_credits_s {
586 #ifdef __BIG_ENDIAN_BITFIELD
587 uint64_t reserved_0_63:64;
589 uint64_t reserved_0_63:64;
592 struct cvmx_pescx_tlp_credits_cn52xx {
593 #ifdef __BIG_ENDIAN_BITFIELD
594 uint64_t reserved_56_63:8;
610 uint64_t reserved_56_63:8;
613 struct cvmx_pescx_tlp_credits_cn52xxp1 {
614 #ifdef __BIG_ENDIAN_BITFIELD
615 uint64_t reserved_38_63:26;
631 uint64_t reserved_38_63:26;
634 struct cvmx_pescx_tlp_credits_cn52xx cn56xx;
635 struct cvmx_pescx_tlp_credits_cn52xxp1 cn56xxp1;