2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
7 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
9 #ifndef _ASM_PGTABLE_32_H
10 #define _ASM_PGTABLE_32_H
12 #include <asm/addrspace.h>
15 #include <linux/linkage.h>
16 #include <asm/cachectl.h>
17 #include <asm/fixmap.h>
19 #include <asm-generic/pgtable-nopmd.h>
21 extern int temp_tlb_entry __cpuinitdata;
24 * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
25 * starting at the top and working down. This is for populating the
26 * TLB before trap_init() puts the TLB miss handler in place. It
27 * should be used only for entries matching the actual page tables,
28 * to prevent inconsistencies.
30 extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
31 unsigned long entryhi, unsigned long pagemask);
34 * Basically we have the same two-level (which is the logical three level
35 * Linux page table layout folded) page tables as the i386. Some day
36 * when we have proper page coloring support we can have a 1% quicker
37 * tlb refill handling mechanism, but for now it is a bit slower but
38 * works even with the cache aliasing problem the R4k and above have.
41 /* PGDIR_SHIFT determines what a third-level page table entry can map */
42 #define PGDIR_SHIFT (2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2)
43 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
44 #define PGDIR_MASK (~(PGDIR_SIZE-1))
47 * Entries per page directory level: we use two-level, so
48 * we don't really have any PUD/PMD directory physically.
50 #define __PGD_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2)
51 #define PGD_ORDER (__PGD_ORDER >= 0 ? __PGD_ORDER : 0)
52 #define PUD_ORDER aieeee_attempt_to_allocate_pud
56 #define PTRS_PER_PGD (USER_PTRS_PER_PGD * 2)
57 #define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
59 #define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE)
60 #define FIRST_USER_ADDRESS 0UL
62 #define VMALLOC_START MAP_BASE
64 #define PKMAP_BASE (0xfe000000UL)
67 # define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE)
69 # define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
72 #ifdef CONFIG_PHYS_ADDR_T_64BIT
73 #define pte_ERROR(e) \
74 printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
76 #define pte_ERROR(e) \
77 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
79 #define pgd_ERROR(e) \
80 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
82 extern void load_pgd(unsigned long pg_dir);
84 extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)];
87 * Empty pgd/pmd entries point to the invalid_pte_table.
89 static inline int pmd_none(pmd_t pmd)
91 return pmd_val(pmd) == (unsigned long) invalid_pte_table;
94 #define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
96 static inline int pmd_present(pmd_t pmd)
98 return pmd_val(pmd) != (unsigned long) invalid_pte_table;
101 static inline void pmd_clear(pmd_t *pmdp)
103 pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
106 #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
107 #define pte_page(x) pfn_to_page(pte_pfn(x))
108 #define pte_pfn(x) ((unsigned long)((x).pte_high >> 6))
110 pfn_pte(unsigned long pfn, pgprot_t prot)
113 pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f);
114 pte.pte_low = pgprot_val(prot);
120 #define pte_page(x) pfn_to_page(pte_pfn(x))
122 #ifdef CONFIG_CPU_VR41XX
123 #define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
124 #define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
126 #define pte_pfn(x) ((unsigned long)((x).pte >> _PFN_SHIFT))
127 #define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot))
129 #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */
131 #define __pgd_offset(address) pgd_index(address)
132 #define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
133 #define __pmd_offset(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
135 /* to find an entry in a kernel page-table-directory */
136 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
138 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
140 /* to find an entry in a page-table-directory */
141 #define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr))
143 /* Find an entry in the third-level page table.. */
144 #define __pte_offset(address) \
145 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
146 #define pte_offset(dir, address) \
147 ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
148 #define pte_offset_kernel(dir, address) \
149 ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
151 #define pte_offset_map(dir, address) \
152 ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
153 #define pte_unmap(pte) ((void)(pte))
155 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
157 /* Swap entries must have VALID bit cleared. */
158 #define __swp_type(x) (((x).val >> 10) & 0x1f)
159 #define __swp_offset(x) ((x).val >> 15)
160 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 10) | ((offset) << 15) })
161 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
162 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
166 #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
168 /* Swap entries must have VALID and GLOBAL bits cleared. */
169 #define __swp_type(x) (((x).val >> 2) & 0x1f)
170 #define __swp_offset(x) ((x).val >> 7)
171 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((offset) << 7) })
172 #define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
173 #define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val })
178 * _PAGE_PRESENT at bit 0
179 * _PAGE_MODIFIED at bit 4
180 * _PAGE_GLOBAL at bit 6
181 * _PAGE_VALID at bit 7
183 #define __swp_type(x) (((x).val >> 8) & 0x1f)
184 #define __swp_offset(x) ((x).val >> 13)
185 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 8) | ((offset) << 13) })
186 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
187 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
189 #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */
191 #endif /* defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) */
193 #endif /* _ASM_PGTABLE_32_H */