2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 2002 by Ralf Baechle
7 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
8 * Copyright (C) 2002 Maciej W. Rozycki
10 #ifndef _ASM_PGTABLE_BITS_H
11 #define _ASM_PGTABLE_BITS_H
15 * Note that we shift the lower 32bits of each EntryLo[01] entry
16 * 6 bits to the left. That way we can convert the PFN into the
17 * physical address by a single 'and' operation and gain 6 additional
18 * bits for storing information which isn't present in a normal
21 * Similar to the Alpha port, we need to keep track of the ref
22 * and mod bits in software. We have a software "yeah you can read
23 * from this page" bit, and a hardware one which actually lets the
24 * process read from the page. On the same token we have a software
25 * writable bit and the real hardware one which actually lets the
26 * process write to the page, this keeps a mod bit via the hardware
29 * Certain revisions of the R4000 and R5000 have a bug where if a
30 * certain sequence occurs in the last 3 instructions of an executable
31 * page, and the following page is not mapped, the cpu can do
32 * unpredictable things. The code (when it is written) to deal with
33 * this problem will be in the update_mmu_cache() code for the r4k.
35 #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
38 * The following bits are implemented by the TLB hardware
40 #define _PAGE_GLOBAL_SHIFT 0
41 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
42 #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
43 #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
44 #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
45 #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
46 #define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1)
47 #define _CACHE_MASK (7 << _CACHE_SHIFT)
50 * The following bits are implemented in software
52 #define _PAGE_PRESENT_SHIFT (_CACHE_SHIFT + 3)
53 #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
54 #define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
55 #define _PAGE_READ (1 << _PAGE_READ_SHIFT)
56 #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
57 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
58 #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
59 #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
60 #define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
61 #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
63 #define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
65 #elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
68 * The following bits are implemented in software
70 #define _PAGE_PRESENT_SHIFT (0)
71 #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
72 #define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
73 #define _PAGE_READ (1 << _PAGE_READ_SHIFT)
74 #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
75 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
76 #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
77 #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
78 #define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
79 #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
82 * The following bits are implemented by the TLB hardware
84 #define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 4)
85 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
86 #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
87 #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
88 #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
89 #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
90 #define _CACHE_UNCACHED_SHIFT (_PAGE_DIRTY_SHIFT + 1)
91 #define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT)
92 #define _CACHE_MASK _CACHE_UNCACHED
94 #define _PFN_SHIFT PAGE_SHIFT
98 * Below are the "Normal" R4K cases
102 * The following bits are implemented in software
104 #define _PAGE_PRESENT_SHIFT 0
105 #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
106 /* R2 or later cores check for RI/XI support to determine _PAGE_READ */
107 #ifdef CONFIG_CPU_MIPSR2
108 #define _PAGE_WRITE_SHIFT (_PAGE_PRESENT_SHIFT + 1)
109 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
111 #define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
112 #define _PAGE_READ (1 << _PAGE_READ_SHIFT)
113 #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
114 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
116 #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
117 #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
118 #define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
119 #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
121 #if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
123 #define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
124 #define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT)
125 #define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT + 1)
126 #define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT)
128 /* Only R2 or newer cores have the XI bit */
129 #ifdef CONFIG_CPU_MIPSR2
130 #define _PAGE_NO_EXEC_SHIFT (_PAGE_SPLITTING_SHIFT + 1)
132 #define _PAGE_GLOBAL_SHIFT (_PAGE_SPLITTING_SHIFT + 1)
133 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
134 #endif /* CONFIG_CPU_MIPSR2 */
136 #endif /* CONFIG_64BIT && CONFIG_MIPS_HUGE_TLB_SUPPORT */
138 #ifdef CONFIG_CPU_MIPSR2
139 /* XI - page cannot be executed */
140 #ifndef _PAGE_NO_EXEC_SHIFT
141 #define _PAGE_NO_EXEC_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
143 #define _PAGE_NO_EXEC (cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0)
145 /* RI - page cannot be read */
146 #define _PAGE_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1)
147 #define _PAGE_READ (cpu_has_rixi ? 0 : (1 << _PAGE_READ_SHIFT))
148 #define _PAGE_NO_READ_SHIFT _PAGE_READ_SHIFT
149 #define _PAGE_NO_READ (cpu_has_rixi ? (1 << _PAGE_READ_SHIFT) : 0)
151 #define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
152 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
154 #else /* !CONFIG_CPU_MIPSR2 */
155 #define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
156 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
157 #endif /* CONFIG_CPU_MIPSR2 */
159 #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
160 #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
161 #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
162 #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
163 #define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1)
164 #define _CACHE_MASK (7 << _CACHE_SHIFT)
166 #define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
168 #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */
170 #ifndef _PAGE_NO_EXEC
171 #define _PAGE_NO_EXEC 0
173 #ifndef _PAGE_NO_READ
174 #define _PAGE_NO_READ 0
177 #define _PAGE_SILENT_READ _PAGE_VALID
178 #define _PAGE_SILENT_WRITE _PAGE_DIRTY
180 #define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1))
183 * The final layouts of the PTE bits are:
185 * 64-bit, R1 or earlier: CCC D V G [S H] M A W R P
186 * 32-bit, R1 or earler: CCC D V G M A W R P
187 * 64-bit, R2 or later: CCC D V G RI/R XI [S H] M A W P
188 * 32-bit, R2 or later: CCC D V G RI/R XI M A W P
194 * pte_to_entrylo converts a page table entry (PTE) into a Mips
197 static inline uint64_t pte_to_entrylo(unsigned long pte_val)
199 #ifdef CONFIG_CPU_MIPSR2
203 sa = 31 - _PAGE_NO_READ_SHIFT;
205 sa = 63 - _PAGE_NO_READ_SHIFT;
208 * C has no way to express that this is a DSRL
209 * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily
210 * in the fast path this is done in assembly
212 return (pte_val >> _PAGE_GLOBAL_SHIFT) |
213 ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa);
217 return pte_val >> _PAGE_GLOBAL_SHIFT;
224 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
226 #define _CACHE_CACHABLE_NONCOHERENT 0
227 #define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED
229 #elif defined(CONFIG_CPU_SB1)
231 /* No penalty for being coherent on the SB1, so just
232 use it for "noncoherent" spaces, too. Shouldn't hurt. */
234 #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
236 #elif defined(CONFIG_CPU_LOONGSON3)
238 /* Using COHERENT flag for NONCOHERENT doesn't hurt. */
240 #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */
241 #define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */
243 #elif defined(CONFIG_MACH_JZ4740)
245 /* Ingenic uses the WA bit to achieve write-combine memory writes */
246 #define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)
250 #ifndef _CACHE_CACHABLE_NO_WA
251 #define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT)
253 #ifndef _CACHE_CACHABLE_WA
254 #define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT)
256 #ifndef _CACHE_UNCACHED
257 #define _CACHE_UNCACHED (2<<_CACHE_SHIFT)
259 #ifndef _CACHE_CACHABLE_NONCOHERENT
260 #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)
262 #ifndef _CACHE_CACHABLE_CE
263 #define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT)
265 #ifndef _CACHE_CACHABLE_COW
266 #define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT)
268 #ifndef _CACHE_CACHABLE_CUW
269 #define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT)
271 #ifndef _CACHE_UNCACHED_ACCELERATED
272 #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
275 #define __READABLE (_PAGE_SILENT_READ | _PAGE_READ | _PAGE_ACCESSED)
276 #define __WRITEABLE (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED)
278 #define _PAGE_CHG_MASK (_PAGE_ACCESSED | _PAGE_MODIFIED | \
279 _PFN_MASK | _CACHE_MASK)
281 #endif /* _ASM_PGTABLE_BITS_H */