2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 Waldorf GMBH
7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
8 * Copyright (C) 1996 Paul M. Antoine
9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
11 #ifndef _ASM_PROCESSOR_H
12 #define _ASM_PROCESSOR_H
14 #include <linux/cpumask.h>
15 #include <linux/threads.h>
17 #include <asm/cachectl.h>
19 #include <asm/cpu-info.h>
20 #include <asm/mipsregs.h>
21 #include <asm/prefetch.h>
22 #include <asm/system.h>
25 * Return current * instruction pointer ("program counter").
27 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
30 * System setup and hardware flags..
32 extern void (*cpu_wait)(void);
34 extern unsigned int vced_count, vcei_count;
37 * A special page (the vdso) is mapped into all processes at the very
38 * top of the virtual memory space.
40 #define SPECIAL_PAGES_SIZE PAGE_SIZE
44 * User space process size: 2GB. This is hardcoded into a few places,
45 * so don't change it unless you know what you are doing.
47 #define TASK_SIZE 0x7fff8000UL
48 #define STACK_TOP ((TASK_SIZE & PAGE_MASK) - SPECIAL_PAGES_SIZE)
51 * This decides where the kernel will search for a free chunk of vm
52 * space during mmap's.
54 #define TASK_UNMAPPED_BASE ((TASK_SIZE / 3) & ~(PAGE_SIZE))
59 * User space process size: 1TB. This is hardcoded into a few places,
60 * so don't change it unless you know what you are doing. TASK_SIZE
61 * is limited to 1TB by the R4000 architecture; R10000 and better can
62 * support 16TB; the architectural reserve for future expansion is
65 #define TASK_SIZE32 0x7fff8000UL
66 #define TASK_SIZE 0x10000000000UL
68 (((test_thread_flag(TIF_32BIT_ADDR) ? \
69 TASK_SIZE32 : TASK_SIZE) & PAGE_MASK) - SPECIAL_PAGES_SIZE)
72 * This decides where the kernel will search for a free chunk of vm
73 * space during mmap's.
75 #define TASK_UNMAPPED_BASE \
76 (test_thread_flag(TIF_32BIT_ADDR) ? \
77 PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3))
78 #define TASK_SIZE_OF(tsk) \
79 (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE)
83 #define STACK_TOP_MAX TASK_SIZE
86 #define NUM_FPU_REGS 32
88 typedef __u64 fpureg_t;
91 * It would be nice to add some more fields for emulator statistics, but there
92 * are a number of fixed offsets in offset.h and elsewhere that would have to
93 * be recalculated by hand. So the additional information will be private to
94 * the FPU emulator for now. See asm-mips/fpu_emulator.h.
97 struct mips_fpu_struct {
98 fpureg_t fpr[NUM_FPU_REGS];
102 #define NUM_DSP_REGS 6
104 typedef __u32 dspreg_t;
106 struct mips_dsp_state {
107 dspreg_t dspr[NUM_DSP_REGS];
108 unsigned int dspcontrol;
111 #define INIT_CPUMASK { \
115 struct mips3264_watch_reg_state {
116 /* The width of watchlo is 32 in a 32 bit kernel and 64 in a
117 64 bit kernel. We use unsigned long as it has the same
119 unsigned long watchlo[NUM_WATCH_REGS];
120 /* Only the mask and IRW bits from watchhi. */
121 u16 watchhi[NUM_WATCH_REGS];
124 union mips_watch_reg_state {
125 struct mips3264_watch_reg_state mips3264;
128 #ifdef CONFIG_CPU_CAVIUM_OCTEON
130 struct octeon_cop2_state {
131 /* DMFC2 rt, 0x0201 */
132 unsigned long cop2_crc_iv;
133 /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
134 unsigned long cop2_crc_length;
135 /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
136 unsigned long cop2_crc_poly;
137 /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
138 unsigned long cop2_llm_dat[2];
139 /* DMFC2 rt, 0x0084 */
140 unsigned long cop2_3des_iv;
141 /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
142 unsigned long cop2_3des_key[3];
143 /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
144 unsigned long cop2_3des_result;
145 /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
146 unsigned long cop2_aes_inp0;
147 /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
148 unsigned long cop2_aes_iv[2];
149 /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
151 unsigned long cop2_aes_key[4];
152 /* DMFC2 rt, 0x0110 */
153 unsigned long cop2_aes_keylen;
154 /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
155 unsigned long cop2_aes_result[2];
156 /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
157 * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
158 * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
159 * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
160 * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
161 unsigned long cop2_hsh_datw[15];
162 /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
163 * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
164 * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
165 unsigned long cop2_hsh_ivw[8];
166 /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
167 unsigned long cop2_gfm_mult[2];
168 /* DMFC2 rt, 0x025E - Pass2 */
169 unsigned long cop2_gfm_poly;
170 /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
171 unsigned long cop2_gfm_result[2];
173 #define INIT_OCTEON_COP2 {0,}
175 struct octeon_cvmseg_state {
176 unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
177 [cpu_dcache_line_size() / sizeof(unsigned long)];
186 #define ARCH_MIN_TASKALIGN 8
191 * If you change thread_struct remember to change the #defines below too!
193 struct thread_struct {
194 /* Saved main processor registers. */
196 unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
197 unsigned long reg29, reg30, reg31;
199 /* Saved cp0 stuff. */
200 unsigned long cp0_status;
202 /* Saved fpu/fpu emulator stuff. */
203 struct mips_fpu_struct fpu;
204 #ifdef CONFIG_MIPS_MT_FPAFF
205 /* Emulated instruction count */
206 unsigned long emulated_fp;
207 /* Saved per-thread scheduler affinity mask */
208 cpumask_t user_cpus_allowed;
209 #endif /* CONFIG_MIPS_MT_FPAFF */
211 /* Saved state of the DSP ASE, if available. */
212 struct mips_dsp_state dsp;
214 /* Saved watch register state, if available. */
215 union mips_watch_reg_state watch;
217 /* Other stuff associated with the thread. */
218 unsigned long cp0_badvaddr; /* Last user fault */
219 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
220 unsigned long error_code;
221 unsigned long trap_no;
222 unsigned long irix_trampoline; /* Wheee... */
223 unsigned long irix_oldctx;
224 #ifdef CONFIG_CPU_CAVIUM_OCTEON
225 struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
226 struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
228 struct mips_abi *abi;
231 #ifdef CONFIG_MIPS_MT_FPAFF
234 .user_cpus_allowed = INIT_CPUMASK,
237 #endif /* CONFIG_MIPS_MT_FPAFF */
239 #ifdef CONFIG_CPU_CAVIUM_OCTEON
240 #define OCTEON_INIT \
241 .cp2 = INIT_OCTEON_COP2,
244 #endif /* CONFIG_CPU_CAVIUM_OCTEON */
246 #define INIT_THREAD { \
248 * Saved main processor registers \
266 * Saved FPU/FPU emulator stuff \
273 * FPU affinity state (null if not FPAFF) \
284 * saved watch register stuff \
286 .watch = {{{0,},},}, \
288 * Other stuff associated with the process \
294 .irix_trampoline = 0, \
297 * Cavium Octeon specifics (null if not Octeon) \
304 /* Free all resources held by a thread. */
305 #define release_thread(thread) do { } while(0)
307 /* Prepare to copy thread state - unlazy all lazy status */
308 #define prepare_to_copy(tsk) do { } while (0)
310 extern long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
312 extern unsigned long thread_saved_pc(struct task_struct *tsk);
315 * Do necessary setup to start up a newly executed thread.
317 extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
319 unsigned long get_wchan(struct task_struct *p);
321 #define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
322 THREAD_SIZE - 32 - sizeof(struct pt_regs))
323 #define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))
324 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
325 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
326 #define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
328 #define cpu_relax() barrier()
331 * Return_address is a replacement for __builtin_return_address(count)
332 * which on certain architectures cannot reasonably be implemented in GCC
333 * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386).
334 * Note that __builtin_return_address(x>=1) is forbidden because GCC
335 * aborts compilation on some CPUs. It's simply not possible to unwind
336 * some CPU's stackframes.
338 * __builtin_return_address works only for non-leaf functions. We avoid the
339 * overhead of a function call by forcing the compiler to save the return
340 * address register on the stack.
342 #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
344 #ifdef CONFIG_CPU_HAS_PREFETCH
346 #define ARCH_HAS_PREFETCH
347 #define prefetch(x) __builtin_prefetch((x), 0, 1)
349 #define ARCH_HAS_PREFETCHW
350 #define prefetchw(x) __builtin_prefetch((x), 1, 1)
354 #endif /* _ASM_PROCESSOR_H */