5 * Definitions for SMTC multitasking on MIPS MT cores
8 #include <asm/mips_mt.h>
9 #include <asm/smtc_ipi.h>
12 * System-wide SMTC status information
15 extern unsigned int smtc_status;
17 #define SMTC_TLB_SHARED 0x00000001
18 #define SMTC_MTC_ACTIVE 0x00000002
21 * TLB/ASID Management information
24 #define MAX_SMTC_TLBS 2
25 #define MAX_SMTC_ASIDS 256
30 typedef short asiduse;
37 * VPE Management information
40 #define MAX_SMTC_VPES MAX_SMTC_TLBS /* FIXME: May not always be true. */
42 extern asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
47 void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu);
48 void self_ipi(struct smtc_ipi *);
49 void smtc_flush_tlb_asid(unsigned long asid);
50 extern int smtc_build_cpu_map(int startslot);
51 extern void smtc_prepare_cpus(int cpus);
52 extern void smtc_smp_finish(void);
53 extern void smtc_boot_secondary(int cpu, struct task_struct *t);
54 extern void smtc_cpus_done(void);
55 extern void smtc_init_secondary(void);
59 * Sharing the TLB between multiple VPEs means that the
60 * "random" index selection function is not allowed to
61 * select the current value of the Index register. To
62 * avoid additional TLB pressure, the Index registers
63 * are "parked" with an non-Valid value.
66 #define PARKED_INDEX ((unsigned int)0x80000000)
69 * Define low-level interrupt mask for IPIs, if necessary.
70 * By default, use SW interrupt 1, which requires no external
71 * hardware support, but which works only for single-core
74 #ifndef MIPS_CPU_IPI_IRQ
75 #define MIPS_CPU_IPI_IRQ 1
78 #endif /* _ASM_SMTC_MT_H */