2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle
7 * Copyright (C) 1994, 1995, 1996 Paul M. Antoine.
8 * Copyright (C) 1999 Silicon Graphics, Inc.
9 * Copyright (C) 2007 Maciej W. Rozycki
11 #ifndef _ASM_STACKFRAME_H
12 #define _ASM_STACKFRAME_H
14 #include <linux/threads.h>
17 #include <asm/asmmacro.h>
18 #include <asm/mipsregs.h>
19 #include <asm/asm-offsets.h>
20 #include <asm/thread_info.h>
23 * For SMTC kernel, global IE should be left set, and interrupts
24 * controlled exclusively via IXMT.
26 #ifdef CONFIG_MIPS_MT_SMTC
28 #elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
34 #ifdef CONFIG_MIPS_MT_SMTC
35 #include <asm/mipsmtregs.h>
36 #endif /* CONFIG_MIPS_MT_SMTC */
46 #ifdef CONFIG_CPU_HAS_SMARTMIPS
60 LONG_S $10, PT_R10(sp)
61 LONG_S $11, PT_R11(sp)
62 LONG_S $12, PT_R12(sp)
63 #ifndef CONFIG_CPU_HAS_SMARTMIPS
67 LONG_S $13, PT_R13(sp)
68 LONG_S $14, PT_R14(sp)
69 LONG_S $15, PT_R15(sp)
70 LONG_S $24, PT_R24(sp)
71 #ifndef CONFIG_CPU_HAS_SMARTMIPS
74 #ifdef CONFIG_CPU_CAVIUM_OCTEON
76 * The Octeon multiplier state is affected by general
77 * multiply instructions. It must be saved before and
78 * kernel code might corrupt it
85 LONG_S $16, PT_R16(sp)
86 LONG_S $17, PT_R17(sp)
87 LONG_S $18, PT_R18(sp)
88 LONG_S $19, PT_R19(sp)
89 LONG_S $20, PT_R20(sp)
90 LONG_S $21, PT_R21(sp)
91 LONG_S $22, PT_R22(sp)
92 LONG_S $23, PT_R23(sp)
93 LONG_S $30, PT_R30(sp)
97 .macro get_saved_sp /* SMP variation */
98 ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG
99 #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
100 lui k1, %hi(kernelsp)
102 lui k1, %highest(kernelsp)
103 daddiu k1, %higher(kernelsp)
105 daddiu k1, %hi(kernelsp)
108 LONG_SRL k0, SMP_CPUID_PTRSHIFT
110 LONG_L k1, %lo(kernelsp)(k1)
113 .macro set_saved_sp stackp temp temp2
114 ASM_CPUID_MFC0 \temp, ASM_SMP_CPUID_REG
115 LONG_SRL \temp, SMP_CPUID_PTRSHIFT
116 LONG_S \stackp, kernelsp(\temp)
118 #else /* !CONFIG_SMP */
119 .macro get_saved_sp /* Uniprocessor variation */
120 #ifdef CONFIG_CPU_JUMP_WORKAROUNDS
122 * Clear BTB (branch target buffer), forbid RAS (return address
123 * stack) to workaround the Out-of-order Issue in Loongson2F
124 * via its diagnostic register.
138 #endif /* CONFIG_CPU_JUMP_WORKAROUNDS */
139 #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
140 lui k1, %hi(kernelsp)
142 lui k1, %highest(kernelsp)
143 daddiu k1, %higher(kernelsp)
145 daddiu k1, %hi(kernelsp)
148 LONG_L k1, %lo(kernelsp)(k1)
151 .macro set_saved_sp stackp temp temp2
152 LONG_S \stackp, kernelsp
161 sll k0, 3 /* extract cu0 bit */
166 /* Called from user mode, new stack. */
168 #ifndef CONFIG_CPU_DADDI_WORKAROUNDS
170 PTR_SUBU sp, k1, PT_SIZE
173 8: PTR_SUBU k1, PT_SIZE
178 LONG_S k0, PT_R29(sp)
181 * You might think that you don't need to save $0,
182 * but the FPU emulator and gdb remote debug stub
183 * need it to operate correctly
188 LONG_S v1, PT_STATUS(sp)
189 #ifdef CONFIG_MIPS_MT_SMTC
191 * Ideally, these instructions would be shuffled in
192 * to cover the pipeline delay.
195 mfc0 k0, CP0_TCSTATUS
197 LONG_S k0, PT_TCSTATUS(sp)
198 #endif /* CONFIG_MIPS_MT_SMTC */
202 LONG_S v1, PT_CAUSE(sp)
210 LONG_S v1, PT_EPC(sp)
211 LONG_S $25, PT_R25(sp)
212 LONG_S $28, PT_R28(sp)
213 LONG_S $31, PT_R31(sp)
214 ori $28, sp, _THREAD_MASK
215 xori $28, _THREAD_MASK
216 #ifdef CONFIG_CPU_CAVIUM_OCTEON
218 pref 0, 0($28) /* Prefetch the current pointer */
238 #ifdef CONFIG_CPU_CAVIUM_OCTEON
239 /* Restore the Octeon multiplier state */
240 jal octeon_mult_restore
242 #ifdef CONFIG_CPU_HAS_SMARTMIPS
243 LONG_L $24, PT_ACX(sp)
245 LONG_L $24, PT_HI(sp)
247 LONG_L $24, PT_LO(sp)
250 LONG_L $24, PT_LO(sp)
252 LONG_L $24, PT_HI(sp)
259 LONG_L $10, PT_R10(sp)
260 LONG_L $11, PT_R11(sp)
261 LONG_L $12, PT_R12(sp)
262 LONG_L $13, PT_R13(sp)
263 LONG_L $14, PT_R14(sp)
264 LONG_L $15, PT_R15(sp)
265 LONG_L $24, PT_R24(sp)
268 .macro RESTORE_STATIC
269 LONG_L $16, PT_R16(sp)
270 LONG_L $17, PT_R17(sp)
271 LONG_L $18, PT_R18(sp)
272 LONG_L $19, PT_R19(sp)
273 LONG_L $20, PT_R20(sp)
274 LONG_L $21, PT_R21(sp)
275 LONG_L $22, PT_R22(sp)
276 LONG_L $23, PT_R23(sp)
277 LONG_L $30, PT_R30(sp)
280 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
292 LONG_L v0, PT_STATUS(sp)
297 LONG_L $31, PT_R31(sp)
298 LONG_L $28, PT_R28(sp)
299 LONG_L $25, PT_R25(sp)
309 .macro RESTORE_SP_AND_RET
312 LONG_L k0, PT_EPC(sp)
313 LONG_L sp, PT_R29(sp)
324 #ifdef CONFIG_MIPS_MT_SMTC
327 * We need to make sure the read-modify-write
328 * of Status below isn't perturbed by an interrupt
329 * or cross-TC access, so we need to do at least a DMT,
330 * protected by an interrupt-inhibit. But setting IXMT
331 * also creates a few-cycle window where an IPI could
332 * be queued and not be detected before potentially
333 * returning to a WAIT or user-mode loop. It must be
336 * We're in the middle of a context switch, and
337 * we can't dispatch it directly without trashing
338 * some registers, so we'll try to detect this unlikely
339 * case and program a software interrupt in the VPE,
340 * as would be done for a cross-VPE IPI. To accommodate
341 * the handling of that case, we're doing a DVPE instead
342 * of just a DMT here to protect against other threads.
343 * This is a lot of cruft to cover a tiny window.
344 * If you can find a better design, implement it!
347 mfc0 v0, CP0_TCSTATUS
348 ori v0, TCSTATUS_IXMT
349 mtc0 v0, CP0_TCSTATUS
353 #endif /* CONFIG_MIPS_MT_SMTC */
360 LONG_L v0, PT_STATUS(sp)
365 #ifdef CONFIG_MIPS_MT_SMTC
367 * Only after EXL/ERL have been restored to status can we
368 * restore TCStatus.IXMT.
370 LONG_L v1, PT_TCSTATUS(sp)
372 mfc0 a0, CP0_TCSTATUS
373 andi v1, TCSTATUS_IXMT
377 * We'd like to detect any IPIs queued in the tiny window
378 * above and request an software interrupt to service them
381 * Computing the offset into the IPIQ array of the executing
382 * TC's IPI queue in-line would be tedious. We use part of
383 * the TCContext register to hold 16 bits of offset that we
384 * can add in-line to find the queue head.
386 mfc0 v0, CP0_TCCONTEXT
393 * If we have a queue, provoke dispatch within the VPE by setting C_SW1
400 * This test should really never branch but
401 * let's be prudent here. Having atomized
402 * the shared register modifications, we can
403 * now EVPE, and must do so before interrupts
404 * are potentially re-enabled.
406 andi a1, a1, MVPCONTROL_EVP
410 /* We know that TCStatua.IXMT should be set from above */
411 xori a0, a0, TCSTATUS_IXMT
413 mtc0 a0, CP0_TCSTATUS
417 #endif /* CONFIG_MIPS_MT_SMTC */
418 LONG_L v1, PT_EPC(sp)
420 LONG_L $31, PT_R31(sp)
421 LONG_L $28, PT_R28(sp)
422 LONG_L $25, PT_R25(sp)
436 .macro RESTORE_SP_AND_RET
437 LONG_L sp, PT_R29(sp)
446 LONG_L sp, PT_R29(sp)
457 .macro RESTORE_ALL_AND_RET
466 * Move to kernel mode and disable interrupts.
467 * Set cp0 enable bit as sign that we're running on the kernel stack
470 #if !defined(CONFIG_MIPS_MT_SMTC)
472 li t1, ST0_CU0 | STATMASK
476 #else /* CONFIG_MIPS_MT_SMTC */
478 * For SMTC, we need to set privilege
479 * and disable interrupts only for the
480 * current TC, using the TCStatus register.
482 mfc0 t0, CP0_TCSTATUS
483 /* Fortunately CU 0 is in the same place in both registers */
484 /* Set TCU0, TMX, TKSU (for later inversion) and IXMT */
485 li t1, ST0_CU0 | 0x08001c00
487 /* Clear TKSU, leave IXMT */
489 mtc0 t0, CP0_TCSTATUS
491 /* We need to leave the global IE bit set, but clear EXL...*/
493 ori t0, ST0_EXL | ST0_ERL
494 xori t0, ST0_EXL | ST0_ERL
496 #endif /* CONFIG_MIPS_MT_SMTC */
501 * Move to kernel mode and enable interrupts.
502 * Set cp0 enable bit as sign that we're running on the kernel stack
505 #if !defined(CONFIG_MIPS_MT_SMTC)
507 li t1, ST0_CU0 | STATMASK
509 xori t0, STATMASK & ~1
511 #else /* CONFIG_MIPS_MT_SMTC */
513 * For SMTC, we need to set privilege
514 * and enable interrupts only for the
515 * current TC, using the TCStatus register.
518 mfc0 t0, CP0_TCSTATUS
519 /* Fortunately CU 0 is in the same place in both registers */
520 /* Set TCU0, TKSU (for later inversion) and IXMT */
521 li t1, ST0_CU0 | 0x08001c00
523 /* Clear TKSU *and* IXMT */
525 mtc0 t0, CP0_TCSTATUS
527 /* We need to leave the global IE bit set, but clear EXL...*/
532 /* irq_enable_hazard below should expand to EHB for 24K/34K cpus */
533 #endif /* CONFIG_MIPS_MT_SMTC */
538 * Just move to kernel mode and leave interrupts as they are. Note
539 * for the R3000 this means copying the previous enable from IEp.
540 * Set cp0 enable bit as sign that we're running on the kernel stack
543 #ifdef CONFIG_MIPS_MT_SMTC
545 * This gets baroque in SMTC. We want to
546 * protect the non-atomic clearing of EXL
547 * with DMT/EMT, but we don't want to take
548 * an interrupt while DMT is still in effect.
551 /* KMODE gets invoked from both reorder and noreorder code */
555 mfc0 v0, CP0_TCSTATUS
556 andi v1, v0, TCSTATUS_IXMT
557 ori v0, TCSTATUS_IXMT
558 mtc0 v0, CP0_TCSTATUS
562 * We don't know a priori if ra is "live"
568 #endif /* CONFIG_MIPS_MT_SMTC */
570 li t1, ST0_CU0 | (STATMASK & ~1)
571 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
577 xori t0, STATMASK & ~1
579 #ifdef CONFIG_MIPS_MT_SMTC
581 andi v0, v0, VPECONTROL_TE
586 mfc0 v0, CP0_TCSTATUS
587 /* Clear IXMT, then OR in previous value */
588 ori v0, TCSTATUS_IXMT
589 xori v0, TCSTATUS_IXMT
591 mtc0 v0, CP0_TCSTATUS
593 * irq_disable_hazard below should expand to EHB
597 #endif /* CONFIG_MIPS_MT_SMTC */
601 #endif /* _ASM_STACKFRAME_H */