2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1996, 97, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2001 MIPS Technologies, Inc.
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/signal.h>
12 #include <linux/module.h>
13 #include <asm/branch.h>
15 #include <asm/cpu-features.h>
17 #include <asm/fpu_emulator.h>
19 #include <asm/mips-r2-to-r6-emul.h>
20 #include <asm/ptrace.h>
21 #include <asm/uaccess.h>
24 * Calculate and return exception PC in case of branch delay slot
25 * for microMIPS and MIPS16e. It does not clear the ISA mode bit.
27 int __isa_exception_epc(struct pt_regs *regs)
30 long epc = regs->cp0_epc;
32 /* Calculate exception PC in branch delay slot. */
33 if (__get_user(inst, (u16 __user *) msk_isa16_mode(epc))) {
34 /* This should never happen because delay slot was checked. */
35 force_sig(SIGSEGV, current);
39 union mips16e_instruction inst_mips16e;
41 inst_mips16e.full = inst;
42 if (inst_mips16e.ri.opcode == MIPS16e_jal_op)
46 } else if (mm_insn_16bit(inst))
54 /* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
55 static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7};
57 int __mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
58 unsigned long *contpc)
60 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
68 switch (insn.mm_i_format.opcode) {
70 if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) ==
72 switch (insn.mm_i_format.simmediate >>
73 MM_POOL32A_MINOR_SHIFT) {
78 if (insn.mm_i_format.rt != 0) /* Not mm_jr */
79 regs->regs[insn.mm_i_format.rt] =
83 *contpc = regs->regs[insn.mm_i_format.rs];
89 switch (insn.mm_i_format.rt) {
92 regs->regs[31] = regs->cp0_epc +
97 if ((long)regs->regs[insn.mm_i_format.rs] < 0)
98 *contpc = regs->cp0_epc +
100 (insn.mm_i_format.simmediate << 1);
102 *contpc = regs->cp0_epc +
104 dec_insn.next_pc_inc;
108 regs->regs[31] = regs->cp0_epc +
110 dec_insn.next_pc_inc;
113 if ((long)regs->regs[insn.mm_i_format.rs] >= 0)
114 *contpc = regs->cp0_epc +
116 (insn.mm_i_format.simmediate << 1);
118 *contpc = regs->cp0_epc +
120 dec_insn.next_pc_inc;
123 if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
124 *contpc = regs->cp0_epc +
126 (insn.mm_i_format.simmediate << 1);
128 *contpc = regs->cp0_epc +
130 dec_insn.next_pc_inc;
133 if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
134 *contpc = regs->cp0_epc +
136 (insn.mm_i_format.simmediate << 1);
138 *contpc = regs->cp0_epc +
140 dec_insn.next_pc_inc;
150 fcr31 = read_32bit_cp1_register(CP1_STATUS);
152 fcr31 = current->thread.fpu.fcr31;
158 bit = (insn.mm_i_format.rs >> 2);
161 if (fcr31 & (1 << bit))
162 *contpc = regs->cp0_epc +
164 (insn.mm_i_format.simmediate << 1);
166 *contpc = regs->cp0_epc +
167 dec_insn.pc_inc + dec_insn.next_pc_inc;
172 switch (insn.mm_i_format.rt) {
175 regs->regs[31] = regs->cp0_epc +
176 dec_insn.pc_inc + dec_insn.next_pc_inc;
179 *contpc = regs->regs[insn.mm_i_format.rs];
184 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0)
185 *contpc = regs->cp0_epc +
187 (insn.mm_b1_format.simmediate << 1);
189 *contpc = regs->cp0_epc +
190 dec_insn.pc_inc + dec_insn.next_pc_inc;
193 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0)
194 *contpc = regs->cp0_epc +
196 (insn.mm_b1_format.simmediate << 1);
198 *contpc = regs->cp0_epc +
199 dec_insn.pc_inc + dec_insn.next_pc_inc;
202 *contpc = regs->cp0_epc + dec_insn.pc_inc +
203 (insn.mm_b0_format.simmediate << 1);
206 if (regs->regs[insn.mm_i_format.rs] ==
207 regs->regs[insn.mm_i_format.rt])
208 *contpc = regs->cp0_epc +
210 (insn.mm_i_format.simmediate << 1);
212 *contpc = regs->cp0_epc +
214 dec_insn.next_pc_inc;
217 if (regs->regs[insn.mm_i_format.rs] !=
218 regs->regs[insn.mm_i_format.rt])
219 *contpc = regs->cp0_epc +
221 (insn.mm_i_format.simmediate << 1);
223 *contpc = regs->cp0_epc +
224 dec_insn.pc_inc + dec_insn.next_pc_inc;
227 regs->regs[31] = regs->cp0_epc +
228 dec_insn.pc_inc + dec_insn.next_pc_inc;
229 *contpc = regs->cp0_epc + dec_insn.pc_inc;
232 *contpc |= (insn.j_format.target << 2);
236 regs->regs[31] = regs->cp0_epc +
237 dec_insn.pc_inc + dec_insn.next_pc_inc;
240 *contpc = regs->cp0_epc + dec_insn.pc_inc;
243 *contpc |= (insn.j_format.target << 1);
244 set_isa16_mode(*contpc);
251 * Compute return address and emulate branch in microMIPS mode after an
252 * exception only. It does not handle compact branches/jumps and cannot
253 * be used in interrupt context. (Compact branches/jumps do not cause
256 int __microMIPS_compute_return_epc(struct pt_regs *regs)
261 unsigned long contpc;
262 struct mm_decoded_insn mminsn = { 0 };
264 mminsn.micro_mips_mode = 1;
266 /* This load never faults. */
267 pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc);
268 __get_user(halfword, pc16);
270 contpc = regs->cp0_epc + 2;
271 word = ((unsigned int)halfword << 16);
274 if (!mm_insn_16bit(halfword)) {
275 __get_user(halfword, pc16);
277 contpc = regs->cp0_epc + 4;
283 if (get_user(halfword, pc16))
285 mminsn.next_pc_inc = 2;
286 word = ((unsigned int)halfword << 16);
288 if (!mm_insn_16bit(halfword)) {
290 if (get_user(halfword, pc16))
292 mminsn.next_pc_inc = 4;
295 mminsn.next_insn = word;
297 mm_isBranchInstr(regs, mminsn, &contpc);
299 regs->cp0_epc = contpc;
304 force_sig(SIGSEGV, current);
309 * Compute return address and emulate branch in MIPS16e mode after an
310 * exception only. It does not handle compact branches/jumps and cannot
311 * be used in interrupt context. (Compact branches/jumps do not cause
314 int __MIPS16e_compute_return_epc(struct pt_regs *regs)
317 union mips16e_instruction inst;
324 /* Read the instruction. */
325 addr = (u16 __user *)msk_isa16_mode(epc);
326 if (__get_user(inst.full, addr)) {
327 force_sig(SIGSEGV, current);
331 switch (inst.ri.opcode) {
332 case MIPS16e_extend_op:
337 * JAL and JALX in MIPS16e mode
341 if (__get_user(inst2, addr)) {
342 force_sig(SIGSEGV, current);
345 fullinst = ((unsigned)inst.full << 16) | inst2;
346 regs->regs[31] = epc + 6;
351 * JAL:5 X:1 TARGET[20-16]:5 TARGET[25:21]:5 TARGET[15:0]:16
353 * ......TARGET[15:0].................TARGET[20:16]...........
354 * ......TARGET[25:21]
357 ((fullinst & 0xffff) << 2) | ((fullinst & 0x3e00000) >> 3) |
358 ((fullinst & 0x1f0000) << 7);
360 set_isa16_mode(epc); /* Set ISA mode bit. */
368 if (inst.rr.func == MIPS16e_jr_func) {
371 regs->cp0_epc = regs->regs[31];
374 regs->regs[reg16to32[inst.rr.rx]];
378 regs->regs[31] = epc + 2;
380 regs->regs[31] = epc + 4;
388 * All other cases have no branch delay slot and are 16-bits.
389 * Branches do not cause an exception.
397 * __compute_return_epc_for_insn - Computes the return address and do emulate
398 * branch simulation, if required.
400 * @regs: Pointer to pt_regs
401 * @insn: branch instruction to decode
402 * @returns: -EFAULT on error and forces SIGBUS, and on success
403 * returns 0 or BRANCH_LIKELY_TAKEN as appropriate after
404 * evaluating the branch.
406 * MIPS R6 Compact branches and forbidden slots:
407 * Compact branches do not throw exceptions because they do
408 * not have delay slots. The forbidden slot instruction ($PC+4)
409 * is only executed if the branch was not taken. Otherwise the
410 * forbidden slot is skipped entirely. This means that the
411 * only possible reason to be here because of a MIPS R6 compact
412 * branch instruction is that the forbidden slot has thrown one.
413 * In that case the branch was not taken, so the EPC can be safely
416 int __compute_return_epc_for_insn(struct pt_regs *regs,
417 union mips_instruction insn)
419 unsigned int bit, fcr31, dspcontrol, reg;
420 long epc = regs->cp0_epc;
423 switch (insn.i_format.opcode) {
425 * jr and jalr are in r_format format.
428 switch (insn.r_format.func) {
430 regs->regs[insn.r_format.rd] = epc + 8;
433 if (NO_R6EMU && insn.r_format.func == jr_op)
435 regs->cp0_epc = regs->regs[insn.r_format.rs];
441 * This group contains:
442 * bltz_op, bgez_op, bltzl_op, bgezl_op,
443 * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
446 switch (insn.i_format.rt) {
451 if ((long)regs->regs[insn.i_format.rs] < 0) {
452 epc = epc + 4 + (insn.i_format.simmediate << 2);
453 if (insn.i_format.rt == bltzl_op)
454 ret = BRANCH_LIKELY_TAKEN;
464 if ((long)regs->regs[insn.i_format.rs] >= 0) {
465 epc = epc + 4 + (insn.i_format.simmediate << 2);
466 if (insn.i_format.rt == bgezl_op)
467 ret = BRANCH_LIKELY_TAKEN;
475 if (NO_R6EMU && (insn.i_format.rs ||
476 insn.i_format.rt == bltzall_op)) {
480 regs->regs[31] = epc + 8;
482 * OK we are here either because we hit a NAL
483 * instruction or because we are emulating an
484 * old bltzal{,l} one. Lets figure out what the
487 if (!insn.i_format.rs) {
489 * NAL or BLTZAL with rs == 0
490 * Doesn't matter if we are R6 or not. The
494 (insn.i_format.simmediate << 2);
497 /* Now do the real thing for non-R6 BLTZAL{,L} */
498 if ((long)regs->regs[insn.i_format.rs] < 0) {
499 epc = epc + 4 + (insn.i_format.simmediate << 2);
500 if (insn.i_format.rt == bltzall_op)
501 ret = BRANCH_LIKELY_TAKEN;
509 if (NO_R6EMU && (insn.i_format.rs ||
510 insn.i_format.rt == bgezall_op)) {
514 regs->regs[31] = epc + 8;
516 * OK we are here either because we hit a BAL
517 * instruction or because we are emulating an
518 * old bgezal{,l} one. Lets figure out what the
521 if (!insn.i_format.rs) {
523 * BAL or BGEZAL with rs == 0
524 * Doesn't matter if we are R6 or not. The
528 (insn.i_format.simmediate << 2);
531 /* Now do the real thing for non-R6 BGEZAL{,L} */
532 if ((long)regs->regs[insn.i_format.rs] >= 0) {
533 epc = epc + 4 + (insn.i_format.simmediate << 2);
534 if (insn.i_format.rt == bgezall_op)
535 ret = BRANCH_LIKELY_TAKEN;
545 dspcontrol = rddsp(0x01);
547 if (dspcontrol >= 32) {
548 epc = epc + 4 + (insn.i_format.simmediate << 2);
557 * These are unconditional and in j_format.
560 regs->regs[31] = regs->cp0_epc + 8;
565 epc |= (insn.j_format.target << 2);
567 if (insn.i_format.opcode == jalx_op)
568 set_isa16_mode(regs->cp0_epc);
572 * These are conditional and in i_format.
578 if (regs->regs[insn.i_format.rs] ==
579 regs->regs[insn.i_format.rt]) {
580 epc = epc + 4 + (insn.i_format.simmediate << 2);
581 if (insn.i_format.opcode == beql_op)
582 ret = BRANCH_LIKELY_TAKEN;
592 if (regs->regs[insn.i_format.rs] !=
593 regs->regs[insn.i_format.rt]) {
594 epc = epc + 4 + (insn.i_format.simmediate << 2);
595 if (insn.i_format.opcode == bnel_op)
596 ret = BRANCH_LIKELY_TAKEN;
602 case blezl_op: /* not really i_format */
603 if (!insn.i_format.rt && NO_R6EMU)
607 * Compact branches for R6 for the
608 * blez and blezl opcodes.
609 * BLEZ | rs = 0 | rt != 0 == BLEZALC
610 * BLEZ | rs = rt != 0 == BGEZALC
611 * BLEZ | rs != 0 | rt != 0 == BGEUC
612 * BLEZL | rs = 0 | rt != 0 == BLEZC
613 * BLEZL | rs = rt != 0 == BGEZC
614 * BLEZL | rs != 0 | rt != 0 == BGEC
616 * For real BLEZ{,L}, rt is always 0.
619 if (cpu_has_mips_r6 && insn.i_format.rt) {
620 if ((insn.i_format.opcode == blez_op) &&
621 ((!insn.i_format.rs && insn.i_format.rt) ||
622 (insn.i_format.rs == insn.i_format.rt)))
623 regs->regs[31] = epc + 4;
627 /* rt field assumed to be zero */
628 if ((long)regs->regs[insn.i_format.rs] <= 0) {
629 epc = epc + 4 + (insn.i_format.simmediate << 2);
630 if (insn.i_format.opcode == blezl_op)
631 ret = BRANCH_LIKELY_TAKEN;
638 if (!insn.i_format.rt && NO_R6EMU)
642 * Compact branches for R6 for the
643 * bgtz and bgtzl opcodes.
644 * BGTZ | rs = 0 | rt != 0 == BGTZALC
645 * BGTZ | rs = rt != 0 == BLTZALC
646 * BGTZ | rs != 0 | rt != 0 == BLTUC
647 * BGTZL | rs = 0 | rt != 0 == BGTZC
648 * BGTZL | rs = rt != 0 == BLTZC
649 * BGTZL | rs != 0 | rt != 0 == BLTC
651 * *ZALC varint for BGTZ &&& rt != 0
652 * For real GTZ{,L}, rt is always 0.
654 if (cpu_has_mips_r6 && insn.i_format.rt) {
655 if ((insn.i_format.opcode == blez_op) &&
656 ((!insn.i_format.rs && insn.i_format.rt) ||
657 (insn.i_format.rs == insn.i_format.rt)))
658 regs->regs[31] = epc + 4;
663 /* rt field assumed to be zero */
664 if ((long)regs->regs[insn.i_format.rs] > 0) {
665 epc = epc + 4 + (insn.i_format.simmediate << 2);
666 if (insn.i_format.opcode == bgtzl_op)
667 ret = BRANCH_LIKELY_TAKEN;
674 * And now the FPA/cp1 branch instructions.
677 if (cpu_has_mips_r6 &&
678 ((insn.i_format.rs == bc1eqz_op) ||
679 (insn.i_format.rs == bc1nez_op))) {
680 if (!used_math()) { /* First time FPU user */
682 if (ret && NO_R6EMU) {
689 lose_fpu(1); /* Save FPU state for the emulator. */
690 reg = insn.i_format.rt;
692 switch (insn.i_format.rs) {
695 if (get_fpr32(¤t->thread.fpu.fpr[reg], 0)
701 if (!(get_fpr32(¤t->thread.fpu.fpr[reg], 0)
709 (insn.i_format.simmediate << 2);
719 fcr31 = read_32bit_cp1_register(CP1_STATUS);
721 fcr31 = current->thread.fpu.fcr31;
724 bit = (insn.i_format.rt >> 2);
727 switch (insn.i_format.rt & 3) {
730 if (~fcr31 & (1 << bit)) {
732 (insn.i_format.simmediate << 2);
733 if (insn.i_format.rt == 2)
734 ret = BRANCH_LIKELY_TAKEN;
742 if (fcr31 & (1 << bit)) {
744 (insn.i_format.simmediate << 2);
745 if (insn.i_format.rt == 3)
746 ret = BRANCH_LIKELY_TAKEN;
754 #ifdef CONFIG_CPU_CAVIUM_OCTEON
755 case lwc2_op: /* This is bbit0 on Octeon */
756 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
758 epc = epc + 4 + (insn.i_format.simmediate << 2);
763 case ldc2_op: /* This is bbit032 on Octeon */
764 if ((regs->regs[insn.i_format.rs] &
765 (1ull<<(insn.i_format.rt+32))) == 0)
766 epc = epc + 4 + (insn.i_format.simmediate << 2);
771 case swc2_op: /* This is bbit1 on Octeon */
772 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
773 epc = epc + 4 + (insn.i_format.simmediate << 2);
778 case sdc2_op: /* This is bbit132 on Octeon */
779 if (regs->regs[insn.i_format.rs] &
780 (1ull<<(insn.i_format.rt+32)))
781 epc = epc + 4 + (insn.i_format.simmediate << 2);
788 /* Only valid for MIPS R6 */
789 if (!cpu_has_mips_r6) {
796 if (!cpu_has_mips_r6) {
800 /* Compact branch: BALC */
801 regs->regs[31] = epc + 4;
802 epc += 4 + (insn.i_format.simmediate << 2);
806 if (!cpu_has_mips_r6) {
810 /* Compact branch: BEQZC || JIC */
814 if (!cpu_has_mips_r6) {
818 /* Compact branch: BNEZC || JIALC */
819 if (insn.i_format.rs)
820 regs->regs[31] = epc + 4;
826 /* Only valid for MIPS R6 */
827 if (!cpu_has_mips_r6) {
833 * bovc, beqc, beqzalc, bnvc, bnec, bnezlac
835 if (insn.i_format.rt && !insn.i_format.rs)
836 regs->regs[31] = epc + 4;
844 printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current->comm);
845 force_sig(SIGBUS, current);
848 pr_info("%s: R2 branch but r2-to-r6 emulator is not preset - sending SIGILL.\n",
850 force_sig(SIGILL, current);
853 EXPORT_SYMBOL_GPL(__compute_return_epc_for_insn);
855 int __compute_return_epc(struct pt_regs *regs)
857 unsigned int __user *addr;
859 union mips_instruction insn;
866 * Read the instruction
868 addr = (unsigned int __user *) epc;
869 if (__get_user(insn.word, addr)) {
870 force_sig(SIGSEGV, current);
874 return __compute_return_epc_for_insn(regs, insn);
877 printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
878 force_sig(SIGBUS, current);