2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2007 MIPS Technologies, Inc.
7 * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
9 #include <linux/clockchips.h>
10 #include <linux/interrupt.h>
11 #include <linux/percpu.h>
12 #include <linux/smp.h>
13 #include <linux/irq.h>
16 #include <asm/cevt-r4k.h>
18 static int mips_next_event(unsigned long delta,
19 struct clock_event_device *evt)
24 cnt = read_c0_count();
26 write_c0_compare(cnt);
27 res = ((int)(read_c0_count() - cnt) >= 0) ? -ETIME : 0;
31 DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
32 int cp0_timer_irq_installed;
35 * Possibly handle a performance counter interrupt.
36 * Return true if the timer interrupt should not be checked
38 static inline int handle_perf_irq(int r2)
41 * The performance counter overflow interrupt may be shared with the
42 * timer interrupt (cp0_perfcount_irq < 0). If it is and a
43 * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
44 * and we can't reliably determine if a counter interrupt has also
45 * happened (!r2) then don't check for a timer interrupt.
47 return (cp0_perfcount_irq < 0) &&
48 perf_irq() == IRQ_HANDLED &&
52 irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
54 const int r2 = cpu_has_mips_r2_r6;
55 struct clock_event_device *cd;
56 int cpu = smp_processor_id();
60 * Before R2 of the architecture there was no way to see if a
61 * performance counter interrupt was pending, so we have to run
62 * the performance counter interrupt handler anyway.
64 if (handle_perf_irq(r2))
68 * The same applies to performance counter interrupts. But with the
69 * above we now know that the reason we got here must be a timer
70 * interrupt. Being the paranoiacs we are we check anyway.
72 if (!r2 || (read_c0_cause() & CAUSEF_TI)) {
73 /* Clear Count/Compare Interrupt */
74 write_c0_compare(read_c0_compare());
75 cd = &per_cpu(mips_clockevent_device, cpu);
76 cd->event_handler(cd);
84 struct irqaction c0_compare_irqaction = {
85 .handler = c0_compare_interrupt,
87 * IRQF_SHARED: The timer interrupt may be shared with other interrupts
88 * such as perf counter and FDC interrupts.
90 .flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED,
95 void mips_event_handler(struct clock_event_device *dev)
100 * FIXME: This doesn't hold for the relocated E9000 compare interrupt.
102 static int c0_compare_int_pending(void)
104 /* When cpu_has_mips_r2, this checks Cause.TI instead of Cause.IP7 */
105 return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP);
109 * Compare interrupt can be routed and latched outside the core,
110 * so wait up to worst case number of cycle counter ticks for timer interrupt
111 * changes to propagate to the cause register.
113 #define COMPARE_INT_SEEN_TICKS 50
115 int c0_compare_int_usable(void)
120 #ifdef CONFIG_KVM_GUEST
125 * IP7 already pending? Try to clear it by acking the timer.
127 if (c0_compare_int_pending()) {
128 cnt = read_c0_count();
129 write_c0_compare(cnt);
130 back_to_back_c0_hazard();
131 while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
132 if (!c0_compare_int_pending())
134 if (c0_compare_int_pending())
138 for (delta = 0x10; delta <= 0x400000; delta <<= 1) {
139 cnt = read_c0_count();
141 write_c0_compare(cnt);
142 back_to_back_c0_hazard();
143 if ((int)(read_c0_count() - cnt) < 0)
145 /* increase delta if the timer was already expired */
148 while ((int)(read_c0_count() - cnt) <= 0)
149 ; /* Wait for expiry */
151 while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
152 if (c0_compare_int_pending())
154 if (!c0_compare_int_pending())
156 cnt = read_c0_count();
157 write_c0_compare(cnt);
158 back_to_back_c0_hazard();
159 while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
160 if (!c0_compare_int_pending())
162 if (c0_compare_int_pending())
166 * Feels like a real count / compare timer.
171 unsigned int __weak get_c0_compare_int(void)
173 return MIPS_CPU_IRQ_BASE + cp0_compare_irq;
176 int r4k_clockevent_init(void)
178 unsigned int cpu = smp_processor_id();
179 struct clock_event_device *cd;
182 if (!cpu_has_counter || !mips_hpt_frequency)
185 if (!c0_compare_int_usable())
189 * With vectored interrupts things are getting platform specific.
190 * get_c0_compare_int is a hook to allow a platform to return the
191 * interrupt number of its liking.
193 irq = get_c0_compare_int();
195 cd = &per_cpu(mips_clockevent_device, cpu);
198 cd->features = CLOCK_EVT_FEAT_ONESHOT |
199 CLOCK_EVT_FEAT_C3STOP |
200 CLOCK_EVT_FEAT_PERCPU;
202 clockevent_set_clock(cd, mips_hpt_frequency);
204 /* Calculate the min / max delta */
205 cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
206 cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
210 cd->cpumask = cpumask_of(cpu);
211 cd->set_next_event = mips_next_event;
212 cd->event_handler = mips_event_handler;
214 clockevents_register_device(cd);
216 if (cp0_timer_irq_installed)
219 cp0_timer_irq_installed = 1;
221 setup_irq(irq, &c0_compare_irqaction);