arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004, 2011, 2012  MIPS Technologies, Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ptrace.h>
  17 #include <linux/smp.h>
  18 #include <linux/stddef.h>
  19 #include <linux/export.h>
  20
  21 #include <asm/bugs.h>
  22 #include <asm/cpu.h>
  23 #include <asm/cpu-features.h>
  24 #include <asm/cpu-type.h>
  25 #include <asm/fpu.h>
  26 #include <asm/mipsregs.h>
  27 #include <asm/mipsmtregs.h>
  28 #include <asm/msa.h>
  29 #include <asm/watch.h>
  30 #include <asm/elf.h>
  31 #include <asm/pgtable-bits.h>
  32 #include <asm/spram.h>
  33 #include <asm/uaccess.h>
  34
  35 /*
  36  * Get the FPU Implementation/Revision.
  37  */
  38 static inline unsigned long cpu_get_fpu_id(void)
  39 {
  40         unsigned long tmp, fpu_id;
  41
  42         tmp = read_c0_status();
  43         __enable_fpu(FPU_AS_IS);
  44         fpu_id = read_32bit_cp1_register(CP1_REVISION);
  45         write_c0_status(tmp);
  46         return fpu_id;
  47 }
  48
  49 /*
  50  * Check if the CPU has an external FPU.
  51  */
  52 static inline int __cpu_has_fpu(void)
  53 {
  54         return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
  55 }
  56
  57 static inline unsigned long cpu_get_msa_id(void)
  58 {
  59         unsigned long status, msa_id;
  60
  61         status = read_c0_status();
  62         __enable_fpu(FPU_64BIT);
  63         enable_msa();
  64         msa_id = read_msa_ir();
  65         disable_msa();
  66         write_c0_status(status);
  67         return msa_id;
  68 }
  69
  70 /*
  71  * Determine the FCSR mask for FPU hardware.
  72  */
  73 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
  74 {
  75         unsigned long sr, mask, fcsr, fcsr0, fcsr1;
  76
  77         mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
  78
  79         sr = read_c0_status();
  80         __enable_fpu(FPU_AS_IS);
  81
  82         fcsr = read_32bit_cp1_register(CP1_STATUS);
  83
  84         fcsr0 = fcsr & mask;
  85         write_32bit_cp1_register(CP1_STATUS, fcsr0);
  86         fcsr0 = read_32bit_cp1_register(CP1_STATUS);
  87
  88         fcsr1 = fcsr | ~mask;
  89         write_32bit_cp1_register(CP1_STATUS, fcsr1);
  90         fcsr1 = read_32bit_cp1_register(CP1_STATUS);
  91
  92         write_32bit_cp1_register(CP1_STATUS, fcsr);
  93
  94         write_c0_status(sr);
  95
  96         c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
  97 }
  98
  99 /*
 100  * Set the FIR feature flags for the FPU emulator.
 101  */
 102 static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
 103 {
 104         u32 value;
 105
 106         value = 0;
 107         if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
 108                             MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 109                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
 110                 value |= MIPS_FPIR_D | MIPS_FPIR_S;
 111         if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 112                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
 113                 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
 114         c->fpu_id = value;
 115 }
 116
 117 /* Determined FPU emulator mask to use for the boot CPU with "nofpu".  */
 118 static unsigned int mips_nofpu_msk31;
 119
 120 /*
 121  * Set options for FPU hardware.
 122  */
 123 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
 124 {
 125         c->fpu_id = cpu_get_fpu_id();
 126         mips_nofpu_msk31 = c->fpu_msk31;
 127
 128         if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
 129                             MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 130                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
 131                 if (c->fpu_id & MIPS_FPIR_3D)
 132                         c->ases |= MIPS_ASE_MIPS3D;
 133                 if (c->fpu_id & MIPS_FPIR_FREP)
 134                         c->options |= MIPS_CPU_FRE;
 135         }
 136
 137         cpu_set_fpu_fcsr_mask(c);
 138 }
 139
 140 /*
 141  * Set options for the FPU emulator.
 142  */
 143 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
 144 {
 145         c->options &= ~MIPS_CPU_FPU;
 146         c->fpu_msk31 = mips_nofpu_msk31;
 147
 148         cpu_set_nofpu_id(c);
 149 }
 150
 151 static int mips_fpu_disabled;
 152
 153 static int __init fpu_disable(char *s)
 154 {
 155         cpu_set_nofpu_opts(&boot_cpu_data);
 156         mips_fpu_disabled = 1;
 157
 158         return 1;
 159 }
 160
 161 __setup("nofpu", fpu_disable);
 162
 163 int mips_dsp_disabled;
 164
 165 static int __init dsp_disable(char *s)
 166 {
 167         cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
 168         mips_dsp_disabled = 1;
 169
 170         return 1;
 171 }
 172
 173 __setup("nodsp", dsp_disable);
 174
 175 static int mips_htw_disabled;
 176
 177 static int __init htw_disable(char *s)
 178 {
 179         mips_htw_disabled = 1;
 180         cpu_data[0].options &= ~MIPS_CPU_HTW;
 181         write_c0_pwctl(read_c0_pwctl() &
 182                        ~(1 << MIPS_PWCTL_PWEN_SHIFT));
 183
 184         return 1;
 185 }
 186
 187 __setup("nohtw", htw_disable);
 188
 189 static int mips_ftlb_disabled;
 190 static int mips_has_ftlb_configured;
 191
 192 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable);
 193
 194 static int __init ftlb_disable(char *s)
 195 {
 196         unsigned int config4, mmuextdef;
 197
 198         /*
 199          * If the core hasn't done any FTLB configuration, there is nothing
 200          * for us to do here.
 201          */
 202         if (!mips_has_ftlb_configured)
 203                 return 1;
 204
 205         /* Disable it in the boot cpu */
 206         set_ftlb_enable(&cpu_data[0], 0);
 207
 208         back_to_back_c0_hazard();
 209
 210         config4 = read_c0_config4();
 211
 212         /* Check that FTLB has been disabled */
 213         mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
 214         /* MMUSIZEEXT == VTLB ON, FTLB OFF */
 215         if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
 216                 /* This should never happen */
 217                 pr_warn("FTLB could not be disabled!\n");
 218                 return 1;
 219         }
 220
 221         mips_ftlb_disabled = 1;
 222         mips_has_ftlb_configured = 0;
 223
 224         /*
 225          * noftlb is mainly used for debug purposes so print
 226          * an informative message instead of using pr_debug()
 227          */
 228         pr_info("FTLB has been disabled\n");
 229
 230         /*
 231          * Some of these bits are duplicated in the decode_config4.
 232          * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
 233          * once FTLB has been disabled so undo what decode_config4 did.
 234          */
 235         cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
 236                                cpu_data[0].tlbsizeftlbsets;
 237         cpu_data[0].tlbsizeftlbsets = 0;
 238         cpu_data[0].tlbsizeftlbways = 0;
 239
 240         return 1;
 241 }
 242
 243 __setup("noftlb", ftlb_disable);
 244
 245
 246 static inline void check_errata(void)
 247 {
 248         struct cpuinfo_mips *c = &current_cpu_data;
 249
 250         switch (current_cpu_type()) {
 251         case CPU_34K:
 252                 /*
 253                  * Erratum "RPS May Cause Incorrect Instruction Execution"
 254                  * This code only handles VPE0, any SMP/RTOS code
 255                  * making use of VPE1 will be responsable for that VPE.
 256                  */
 257                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
 258                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
 259                 break;
 260         default:
 261                 break;
 262         }
 263 }
 264
 265 void __init check_bugs32(void)
 266 {
 267         check_errata();
 268 }
 269
 270 /*
 271  * Probe whether cpu has config register by trying to play with
 272  * alternate cache bit and see whether it matters.
 273  * It's used by cpu_probe to distinguish between R3000A and R3081.
 274  */
 275 static inline int cpu_has_confreg(void)
 276 {
 277 #ifdef CONFIG_CPU_R3000
 278         extern unsigned long r3k_cache_size(unsigned long);
 279         unsigned long size1, size2;
 280         unsigned long cfg = read_c0_conf();
 281
 282         size1 = r3k_cache_size(ST0_ISC);
 283         write_c0_conf(cfg ^ R30XX_CONF_AC);
 284         size2 = r3k_cache_size(ST0_ISC);
 285         write_c0_conf(cfg);
 286         return size1 != size2;
 287 #else
 288         return 0;
 289 #endif
 290 }
 291
 292 static inline void set_elf_platform(int cpu, const char *plat)
 293 {
 294         if (cpu == 0)
 295                 __elf_platform = plat;
 296 }
 297
 298 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
 299 {
 300 #ifdef __NEED_VMBITS_PROBE
 301         write_c0_entryhi(0x3fffffffffffe000ULL);
 302         back_to_back_c0_hazard();
 303         c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
 304 #endif
 305 }
 306
 307 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
 308 {
 309         switch (isa) {
 310         case MIPS_CPU_ISA_M64R2:
 311                 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
 312         case MIPS_CPU_ISA_M64R1:
 313                 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
 314         case MIPS_CPU_ISA_V:
 315                 c->isa_level |= MIPS_CPU_ISA_V;
 316         case MIPS_CPU_ISA_IV:
 317                 c->isa_level |= MIPS_CPU_ISA_IV;
 318         case MIPS_CPU_ISA_III:
 319                 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
 320                 break;
 321
 322         /* R6 incompatible with everything else */
 323         case MIPS_CPU_ISA_M64R6:
 324                 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
 325         case MIPS_CPU_ISA_M32R6:
 326                 c->isa_level |= MIPS_CPU_ISA_M32R6;
 327                 /* Break here so we don't add incompatible ISAs */
 328                 break;
 329         case MIPS_CPU_ISA_M32R2:
 330                 c->isa_level |= MIPS_CPU_ISA_M32R2;
 331         case MIPS_CPU_ISA_M32R1:
 332                 c->isa_level |= MIPS_CPU_ISA_M32R1;
 333         case MIPS_CPU_ISA_II:
 334                 c->isa_level |= MIPS_CPU_ISA_II;
 335                 break;
 336         }
 337 }
 338
 339 static char unknown_isa[] = KERN_ERR \
 340         "Unsupported ISA type, c0.config0: %d.";
 341
 342 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
 343 {
 344
 345         unsigned int probability = c->tlbsize / c->tlbsizevtlb;
 346
 347         /*
 348          * 0 = All TLBWR instructions go to FTLB
 349          * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
 350          * FTLB and 1 goes to the VTLB.
 351          * 2 = 7:1: As above with 7:1 ratio.
 352          * 3 = 3:1: As above with 3:1 ratio.
 353          *
 354          * Use the linear midpoint as the probability threshold.
 355          */
 356         if (probability >= 12)
 357                 return 1;
 358         else if (probability >= 6)
 359                 return 2;
 360         else
 361                 /*
 362                  * So FTLB is less than 4 times bigger than VTLB.
 363                  * A 3:1 ratio can still be useful though.
 364                  */
 365                 return 3;
 366 }
 367
 368 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
 369 {
 370         unsigned int config6;
 371
 372         /* It's implementation dependent how the FTLB can be enabled */
 373         switch (c->cputype) {
 374         case CPU_PROAPTIV:
 375         case CPU_P5600:
 376                 /* proAptiv & related cores use Config6 to enable the FTLB */
 377                 config6 = read_c0_config6();
 378                 /* Clear the old probability value */
 379                 config6 &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
 380                 if (enable)
 381                         /* Enable FTLB */
 382                         write_c0_config6(config6 |
 383                                          (calculate_ftlb_probability(c)
 384                                           << MIPS_CONF6_FTLBP_SHIFT)
 385                                          | MIPS_CONF6_FTLBEN);
 386                 else
 387                         /* Disable FTLB */
 388                         write_c0_config6(config6 &  ~MIPS_CONF6_FTLBEN);
 389                 back_to_back_c0_hazard();
 390                 break;
 391         }
 392 }
 393
 394 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 395 {
 396         unsigned int config0;
 397         int isa;
 398
 399         config0 = read_c0_config();
 400
 401         /*
 402          * Look for Standard TLB or Dual VTLB and FTLB
 403          */
 404         if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
 405             (((config0 & MIPS_CONF_MT) >> 7) == 4))
 406                 c->options |= MIPS_CPU_TLB;
 407
 408         isa = (config0 & MIPS_CONF_AT) >> 13;
 409         switch (isa) {
 410         case 0:
 411                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 412                 case 0:
 413                         set_isa(c, MIPS_CPU_ISA_M32R1);
 414                         break;
 415                 case 1:
 416                         set_isa(c, MIPS_CPU_ISA_M32R2);
 417                         break;
 418                 case 2:
 419                         set_isa(c, MIPS_CPU_ISA_M32R6);
 420                         break;
 421                 default:
 422                         goto unknown;
 423                 }
 424                 break;
 425         case 2:
 426                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 427                 case 0:
 428                         set_isa(c, MIPS_CPU_ISA_M64R1);
 429                         break;
 430                 case 1:
 431                         set_isa(c, MIPS_CPU_ISA_M64R2);
 432                         break;
 433                 case 2:
 434                         set_isa(c, MIPS_CPU_ISA_M64R6);
 435                         break;
 436                 default:
 437                         goto unknown;
 438                 }
 439                 break;
 440         default:
 441                 goto unknown;
 442         }
 443
 444         return config0 & MIPS_CONF_M;
 445
 446 unknown:
 447         panic(unknown_isa, config0);
 448 }
 449
 450 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 451 {
 452         unsigned int config1;
 453
 454         config1 = read_c0_config1();
 455
 456         if (config1 & MIPS_CONF1_MD)
 457                 c->ases |= MIPS_ASE_MDMX;
 458         if (config1 & MIPS_CONF1_WR)
 459                 c->options |= MIPS_CPU_WATCH;
 460         if (config1 & MIPS_CONF1_CA)
 461                 c->ases |= MIPS_ASE_MIPS16;
 462         if (config1 & MIPS_CONF1_EP)
 463                 c->options |= MIPS_CPU_EJTAG;
 464         if (config1 & MIPS_CONF1_FP) {
 465                 c->options |= MIPS_CPU_FPU;
 466                 c->options |= MIPS_CPU_32FPR;
 467         }
 468         if (cpu_has_tlb) {
 469                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 470                 c->tlbsizevtlb = c->tlbsize;
 471                 c->tlbsizeftlbsets = 0;
 472         }
 473
 474         return config1 & MIPS_CONF_M;
 475 }
 476
 477 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 478 {
 479         unsigned int config2;
 480
 481         config2 = read_c0_config2();
 482
 483         if (config2 & MIPS_CONF2_SL)
 484                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 485
 486         return config2 & MIPS_CONF_M;
 487 }
 488
 489 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 490 {
 491         unsigned int config3;
 492
 493         config3 = read_c0_config3();
 494
 495         if (config3 & MIPS_CONF3_SM) {
 496                 c->ases |= MIPS_ASE_SMARTMIPS;
 497                 c->options |= MIPS_CPU_RIXI;
 498         }
 499         if (config3 & MIPS_CONF3_RXI)
 500                 c->options |= MIPS_CPU_RIXI;
 501         if (config3 & MIPS_CONF3_DSP)
 502                 c->ases |= MIPS_ASE_DSP;
 503         if (config3 & MIPS_CONF3_DSP2P)
 504                 c->ases |= MIPS_ASE_DSP2P;
 505         if (config3 & MIPS_CONF3_VINT)
 506                 c->options |= MIPS_CPU_VINT;
 507         if (config3 & MIPS_CONF3_VEIC)
 508                 c->options |= MIPS_CPU_VEIC;
 509         if (config3 & MIPS_CONF3_MT)
 510                 c->ases |= MIPS_ASE_MIPSMT;
 511         if (config3 & MIPS_CONF3_ULRI)
 512                 c->options |= MIPS_CPU_ULRI;
 513         if (config3 & MIPS_CONF3_ISA)
 514                 c->options |= MIPS_CPU_MICROMIPS;
 515         if (config3 & MIPS_CONF3_VZ)
 516                 c->ases |= MIPS_ASE_VZ;
 517         if (config3 & MIPS_CONF3_SC)
 518                 c->options |= MIPS_CPU_SEGMENTS;
 519         if (config3 & MIPS_CONF3_MSA)
 520                 c->ases |= MIPS_ASE_MSA;
 521         /* Only tested on 32-bit cores */
 522         if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) {
 523                 c->htw_seq = 0;
 524                 c->options |= MIPS_CPU_HTW;
 525         }
 526         if (config3 & MIPS_CONF3_CDMM)
 527                 c->options |= MIPS_CPU_CDMM;
 528
 529         return config3 & MIPS_CONF_M;
 530 }
 531
 532 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
 533 {
 534         unsigned int config4;
 535         unsigned int newcf4;
 536         unsigned int mmuextdef;
 537         unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
 538
 539         config4 = read_c0_config4();
 540
 541         if (cpu_has_tlb) {
 542                 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
 543                         c->options |= MIPS_CPU_TLBINV;
 544                 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
 545                 switch (mmuextdef) {
 546                 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
 547                         c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
 548                         c->tlbsizevtlb = c->tlbsize;
 549                         break;
 550                 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
 551                         c->tlbsizevtlb +=
 552                                 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
 553                                   MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
 554                         c->tlbsize = c->tlbsizevtlb;
 555                         ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
 556                         /* fall through */
 557                 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
 558                         if (mips_ftlb_disabled)
 559                                 break;
 560                         newcf4 = (config4 & ~ftlb_page) |
 561                                 (page_size_ftlb(mmuextdef) <<
 562                                  MIPS_CONF4_FTLBPAGESIZE_SHIFT);
 563                         write_c0_config4(newcf4);
 564                         back_to_back_c0_hazard();
 565                         config4 = read_c0_config4();
 566                         if (config4 != newcf4) {
 567                                 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
 568                                        PAGE_SIZE, config4);
 569                                 /* Switch FTLB off */
 570                                 set_ftlb_enable(c, 0);
 571                                 break;
 572                         }
 573                         c->tlbsizeftlbsets = 1 <<
 574                                 ((config4 & MIPS_CONF4_FTLBSETS) >>
 575                                  MIPS_CONF4_FTLBSETS_SHIFT);
 576                         c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
 577                                               MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
 578                         c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
 579                         mips_has_ftlb_configured = 1;
 580                         break;
 581                 }
 582         }
 583
 584         c->kscratch_mask = (config4 >> 16) & 0xff;
 585
 586         return config4 & MIPS_CONF_M;
 587 }
 588
 589 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
 590 {
 591         unsigned int config5;
 592
 593         config5 = read_c0_config5();
 594         config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
 595         write_c0_config5(config5);
 596
 597         if (config5 & MIPS_CONF5_EVA)
 598                 c->options |= MIPS_CPU_EVA;
 599         if (config5 & MIPS_CONF5_MRP)
 600                 c->options |= MIPS_CPU_MAAR;
 601         if (config5 & MIPS_CONF5_LLB)
 602                 c->options |= MIPS_CPU_RW_LLB;
 603 #ifdef CONFIG_XPA
 604         if (config5 & MIPS_CONF5_MVH)
 605                 c->options |= MIPS_CPU_XPA;
 606 #endif
 607
 608         return config5 & MIPS_CONF_M;
 609 }
 610
 611 static void decode_configs(struct cpuinfo_mips *c)
 612 {
 613         int ok;
 614
 615         /* MIPS32 or MIPS64 compliant CPU.  */
 616         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 617                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 618
 619         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 620
 621         /* Enable FTLB if present and not disabled */
 622         set_ftlb_enable(c, !mips_ftlb_disabled);
 623
 624         ok = decode_config0(c);                 /* Read Config registers.  */
 625         BUG_ON(!ok);                            /* Arch spec violation!  */
 626         if (ok)
 627                 ok = decode_config1(c);
 628         if (ok)
 629                 ok = decode_config2(c);
 630         if (ok)
 631                 ok = decode_config3(c);
 632         if (ok)
 633                 ok = decode_config4(c);
 634         if (ok)
 635                 ok = decode_config5(c);
 636
 637         mips_probe_watch_registers(c);
 638
 639         if (cpu_has_rixi) {
 640                 /* Enable the RIXI exceptions */
 641                 set_c0_pagegrain(PG_IEC);
 642                 back_to_back_c0_hazard();
 643                 /* Verify the IEC bit is set */
 644                 if (read_c0_pagegrain() & PG_IEC)
 645                         c->options |= MIPS_CPU_RIXIEX;
 646         }
 647
 648 #ifndef CONFIG_MIPS_CPS
 649         if (cpu_has_mips_r2_r6) {
 650                 c->core = get_ebase_cpunum();
 651                 if (cpu_has_mipsmt)
 652                         c->core >>= fls(core_nvpes()) - 1;
 653         }
 654 #endif
 655 }
 656
 657 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 658                 | MIPS_CPU_COUNTER)
 659
 660 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 661 {
 662         switch (c->processor_id & PRID_IMP_MASK) {
 663         case PRID_IMP_R2000:
 664                 c->cputype = CPU_R2000;
 665                 __cpu_name[cpu] = "R2000";
 666                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
 667                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 668                              MIPS_CPU_NOFPUEX;
 669                 if (__cpu_has_fpu())
 670                         c->options |= MIPS_CPU_FPU;
 671                 c->tlbsize = 64;
 672                 break;
 673         case PRID_IMP_R3000:
 674                 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
 675                         if (cpu_has_confreg()) {
 676                                 c->cputype = CPU_R3081E;
 677                                 __cpu_name[cpu] = "R3081";
 678                         } else {
 679                                 c->cputype = CPU_R3000A;
 680                                 __cpu_name[cpu] = "R3000A";
 681                         }
 682                 } else {
 683                         c->cputype = CPU_R3000;
 684                         __cpu_name[cpu] = "R3000";
 685                 }
 686                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
 687                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 688                              MIPS_CPU_NOFPUEX;
 689                 if (__cpu_has_fpu())
 690                         c->options |= MIPS_CPU_FPU;
 691                 c->tlbsize = 64;
 692                 break;
 693         case PRID_IMP_R4000:
 694                 if (read_c0_config() & CONF_SC) {
 695                         if ((c->processor_id & PRID_REV_MASK) >=
 696                             PRID_REV_R4400) {
 697                                 c->cputype = CPU_R4400PC;
 698                                 __cpu_name[cpu] = "R4400PC";
 699                         } else {
 700                                 c->cputype = CPU_R4000PC;
 701                                 __cpu_name[cpu] = "R4000PC";
 702                         }
 703                 } else {
 704                         int cca = read_c0_config() & CONF_CM_CMASK;
 705                         int mc;
 706
 707                         /*
 708                          * SC and MC versions can't be reliably told apart,
 709                          * but only the latter support coherent caching
 710                          * modes so assume the firmware has set the KSEG0
 711                          * coherency attribute reasonably (if uncached, we
 712                          * assume SC).
 713                          */
 714                         switch (cca) {
 715                         case CONF_CM_CACHABLE_CE:
 716                         case CONF_CM_CACHABLE_COW:
 717                         case CONF_CM_CACHABLE_CUW:
 718                                 mc = 1;
 719                                 break;
 720                         default:
 721                                 mc = 0;
 722                                 break;
 723                         }
 724                         if ((c->processor_id & PRID_REV_MASK) >=
 725                             PRID_REV_R4400) {
 726                                 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
 727                                 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
 728                         } else {
 729                                 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
 730                                 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
 731                         }
 732                 }
 733
 734                 set_isa(c, MIPS_CPU_ISA_III);
 735                 c->fpu_msk31 |= FPU_CSR_CONDX;
 736                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 737                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 738                              MIPS_CPU_LLSC;
 739                 c->tlbsize = 48;
 740                 break;
 741         case PRID_IMP_VR41XX:
 742                 set_isa(c, MIPS_CPU_ISA_III);
 743                 c->fpu_msk31 |= FPU_CSR_CONDX;
 744                 c->options = R4K_OPTS;
 745                 c->tlbsize = 32;
 746                 switch (c->processor_id & 0xf0) {
 747                 case PRID_REV_VR4111:
 748                         c->cputype = CPU_VR4111;
 749                         __cpu_name[cpu] = "NEC VR4111";
 750                         break;
 751                 case PRID_REV_VR4121:
 752                         c->cputype = CPU_VR4121;
 753                         __cpu_name[cpu] = "NEC VR4121";
 754                         break;
 755                 case PRID_REV_VR4122:
 756                         if ((c->processor_id & 0xf) < 0x3) {
 757                                 c->cputype = CPU_VR4122;
 758                                 __cpu_name[cpu] = "NEC VR4122";
 759                         } else {
 760                                 c->cputype = CPU_VR4181A;
 761                                 __cpu_name[cpu] = "NEC VR4181A";
 762                         }
 763                         break;
 764                 case PRID_REV_VR4130:
 765                         if ((c->processor_id & 0xf) < 0x4) {
 766                                 c->cputype = CPU_VR4131;
 767                                 __cpu_name[cpu] = "NEC VR4131";
 768                         } else {
 769                                 c->cputype = CPU_VR4133;
 770                                 c->options |= MIPS_CPU_LLSC;
 771                                 __cpu_name[cpu] = "NEC VR4133";
 772                         }
 773                         break;
 774                 default:
 775                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 776                         c->cputype = CPU_VR41XX;
 777                         __cpu_name[cpu] = "NEC Vr41xx";
 778                         break;
 779                 }
 780                 break;
 781         case PRID_IMP_R4300:
 782                 c->cputype = CPU_R4300;
 783                 __cpu_name[cpu] = "R4300";
 784                 set_isa(c, MIPS_CPU_ISA_III);
 785                 c->fpu_msk31 |= FPU_CSR_CONDX;
 786                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 787                              MIPS_CPU_LLSC;
 788                 c->tlbsize = 32;
 789                 break;
 790         case PRID_IMP_R4600:
 791                 c->cputype = CPU_R4600;
 792                 __cpu_name[cpu] = "R4600";
 793                 set_isa(c, MIPS_CPU_ISA_III);
 794                 c->fpu_msk31 |= FPU_CSR_CONDX;
 795                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 796                              MIPS_CPU_LLSC;
 797                 c->tlbsize = 48;
 798                 break;
 799         #if 0
 800         case PRID_IMP_R4650:
 801                 /*
 802                  * This processor doesn't have an MMU, so it's not
 803                  * "real easy" to run Linux on it. It is left purely
 804                  * for documentation.  Commented out because it shares
 805                  * it's c0_prid id number with the TX3900.
 806                  */
 807                 c->cputype = CPU_R4650;
 808                 __cpu_name[cpu] = "R4650";
 809                 set_isa(c, MIPS_CPU_ISA_III);
 810                 c->fpu_msk31 |= FPU_CSR_CONDX;
 811                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 812                 c->tlbsize = 48;
 813                 break;
 814         #endif
 815         case PRID_IMP_TX39:
 816                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
 817                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
 818
 819                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 820                         c->cputype = CPU_TX3927;
 821                         __cpu_name[cpu] = "TX3927";
 822                         c->tlbsize = 64;
 823                 } else {
 824                         switch (c->processor_id & PRID_REV_MASK) {
 825                         case PRID_REV_TX3912:
 826                                 c->cputype = CPU_TX3912;
 827                                 __cpu_name[cpu] = "TX3912";
 828                                 c->tlbsize = 32;
 829                                 break;
 830                         case PRID_REV_TX3922:
 831                                 c->cputype = CPU_TX3922;
 832                                 __cpu_name[cpu] = "TX3922";
 833                                 c->tlbsize = 64;
 834                                 break;
 835                         }
 836                 }
 837                 break;
 838         case PRID_IMP_R4700:
 839                 c->cputype = CPU_R4700;
 840                 __cpu_name[cpu] = "R4700";
 841                 set_isa(c, MIPS_CPU_ISA_III);
 842                 c->fpu_msk31 |= FPU_CSR_CONDX;
 843                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 844                              MIPS_CPU_LLSC;
 845                 c->tlbsize = 48;
 846                 break;
 847         case PRID_IMP_TX49:
 848                 c->cputype = CPU_TX49XX;
 849                 __cpu_name[cpu] = "R49XX";
 850                 set_isa(c, MIPS_CPU_ISA_III);
 851                 c->fpu_msk31 |= FPU_CSR_CONDX;
 852                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 853                 if (!(c->processor_id & 0x08))
 854                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 855                 c->tlbsize = 48;
 856                 break;
 857         case PRID_IMP_R5000:
 858                 c->cputype = CPU_R5000;
 859                 __cpu_name[cpu] = "R5000";
 860                 set_isa(c, MIPS_CPU_ISA_IV);
 861                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 862                              MIPS_CPU_LLSC;
 863                 c->tlbsize = 48;
 864                 break;
 865         case PRID_IMP_R5432:
 866                 c->cputype = CPU_R5432;
 867                 __cpu_name[cpu] = "R5432";
 868                 set_isa(c, MIPS_CPU_ISA_IV);
 869                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 870                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 871                 c->tlbsize = 48;
 872                 break;
 873         case PRID_IMP_R5500:
 874                 c->cputype = CPU_R5500;
 875                 __cpu_name[cpu] = "R5500";
 876                 set_isa(c, MIPS_CPU_ISA_IV);
 877                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 878                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 879                 c->tlbsize = 48;
 880                 break;
 881         case PRID_IMP_NEVADA:
 882                 c->cputype = CPU_NEVADA;
 883                 __cpu_name[cpu] = "Nevada";
 884                 set_isa(c, MIPS_CPU_ISA_IV);
 885                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 886                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 887                 c->tlbsize = 48;
 888                 break;
 889         case PRID_IMP_R6000:
 890                 c->cputype = CPU_R6000;
 891                 __cpu_name[cpu] = "R6000";
 892                 set_isa(c, MIPS_CPU_ISA_II);
 893                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
 894                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 895                              MIPS_CPU_LLSC;
 896                 c->tlbsize = 32;
 897                 break;
 898         case PRID_IMP_R6000A:
 899                 c->cputype = CPU_R6000A;
 900                 __cpu_name[cpu] = "R6000A";
 901                 set_isa(c, MIPS_CPU_ISA_II);
 902                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
 903                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 904                              MIPS_CPU_LLSC;
 905                 c->tlbsize = 32;
 906                 break;
 907         case PRID_IMP_RM7000:
 908                 c->cputype = CPU_RM7000;
 909                 __cpu_name[cpu] = "RM7000";
 910                 set_isa(c, MIPS_CPU_ISA_IV);
 911                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 912                              MIPS_CPU_LLSC;
 913                 /*
 914                  * Undocumented RM7000:  Bit 29 in the info register of
 915                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 916                  * entries.
 917                  *
 918                  * 29      1 =>    64 entry JTLB
 919                  *         0 =>    48 entry JTLB
 920                  */
 921                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 922                 break;
 923         case PRID_IMP_R8000:
 924                 c->cputype = CPU_R8000;
 925                 __cpu_name[cpu] = "RM8000";
 926                 set_isa(c, MIPS_CPU_ISA_IV);
 927                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 928                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 929                              MIPS_CPU_LLSC;
 930                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 931                 break;
 932         case PRID_IMP_R10000:
 933                 c->cputype = CPU_R10000;
 934                 __cpu_name[cpu] = "R10000";
 935                 set_isa(c, MIPS_CPU_ISA_IV);
 936                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 937                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 938                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 939                              MIPS_CPU_LLSC;
 940                 c->tlbsize = 64;
 941                 break;
 942         case PRID_IMP_R12000:
 943                 c->cputype = CPU_R12000;
 944                 __cpu_name[cpu] = "R12000";
 945                 set_isa(c, MIPS_CPU_ISA_IV);
 946                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 947                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 948                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 949                              MIPS_CPU_LLSC;
 950                 c->tlbsize = 64;
 951                 break;
 952         case PRID_IMP_R14000:
 953                 if (((c->processor_id >> 4) & 0x0f) > 2) {
 954                         c->cputype = CPU_R16000;
 955                         __cpu_name[cpu] = "R16000";
 956                 } else {
 957                         c->cputype = CPU_R14000;
 958                         __cpu_name[cpu] = "R14000";
 959                 }
 960                 set_isa(c, MIPS_CPU_ISA_IV);
 961                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 962                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 963                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 964                              MIPS_CPU_LLSC;
 965                 c->tlbsize = 64;
 966                 break;
 967         case PRID_IMP_LOONGSON_64:  /* Loongson-2/3 */
 968                 switch (c->processor_id & PRID_REV_MASK) {
 969                 case PRID_REV_LOONGSON2E:
 970                         c->cputype = CPU_LOONGSON2;
 971                         __cpu_name[cpu] = "ICT Loongson-2";
 972                         set_elf_platform(cpu, "loongson2e");
 973                         set_isa(c, MIPS_CPU_ISA_III);
 974                         c->fpu_msk31 |= FPU_CSR_CONDX;
 975                         break;
 976                 case PRID_REV_LOONGSON2F:
 977                         c->cputype = CPU_LOONGSON2;
 978                         __cpu_name[cpu] = "ICT Loongson-2";
 979                         set_elf_platform(cpu, "loongson2f");
 980                         set_isa(c, MIPS_CPU_ISA_III);
 981                         c->fpu_msk31 |= FPU_CSR_CONDX;
 982                         break;
 983                 case PRID_REV_LOONGSON3A:
 984                         c->cputype = CPU_LOONGSON3;
 985                         __cpu_name[cpu] = "ICT Loongson-3";
 986                         set_elf_platform(cpu, "loongson3a");
 987                         set_isa(c, MIPS_CPU_ISA_M64R1);
 988                         break;
 989                 case PRID_REV_LOONGSON3B_R1:
 990                 case PRID_REV_LOONGSON3B_R2:
 991                         c->cputype = CPU_LOONGSON3;
 992                         __cpu_name[cpu] = "ICT Loongson-3";
 993                         set_elf_platform(cpu, "loongson3b");
 994                         set_isa(c, MIPS_CPU_ISA_M64R1);
 995                         break;
 996                 }
 997
 998                 c->options = R4K_OPTS |
 999                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
1000                              MIPS_CPU_32FPR;
1001                 c->tlbsize = 64;
1002                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1003                 break;
1004         case PRID_IMP_LOONGSON_32:  /* Loongson-1 */
1005                 decode_configs(c);
1006
1007                 c->cputype = CPU_LOONGSON1;
1008
1009                 switch (c->processor_id & PRID_REV_MASK) {
1010                 case PRID_REV_LOONGSON1B:
1011                         __cpu_name[cpu] = "Loongson 1B";
1012                         break;
1013                 }
1014
1015                 break;
1016         }
1017 }
1018
1019 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1020 {
1021         c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1022         switch (c->processor_id & PRID_IMP_MASK) {
1023         case PRID_IMP_QEMU_GENERIC:
1024                 c->writecombine = _CACHE_UNCACHED;
1025                 c->cputype = CPU_QEMU_GENERIC;
1026                 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1027                 break;
1028         case PRID_IMP_4KC:
1029                 c->cputype = CPU_4KC;
1030                 c->writecombine = _CACHE_UNCACHED;
1031                 __cpu_name[cpu] = "MIPS 4Kc";
1032                 break;
1033         case PRID_IMP_4KEC:
1034         case PRID_IMP_4KECR2:
1035                 c->cputype = CPU_4KEC;
1036                 c->writecombine = _CACHE_UNCACHED;
1037                 __cpu_name[cpu] = "MIPS 4KEc";
1038                 break;
1039         case PRID_IMP_4KSC:
1040         case PRID_IMP_4KSD:
1041                 c->cputype = CPU_4KSC;
1042                 c->writecombine = _CACHE_UNCACHED;
1043                 __cpu_name[cpu] = "MIPS 4KSc";
1044                 break;
1045         case PRID_IMP_5KC:
1046                 c->cputype = CPU_5KC;
1047                 c->writecombine = _CACHE_UNCACHED;
1048                 __cpu_name[cpu] = "MIPS 5Kc";
1049                 break;
1050         case PRID_IMP_5KE:
1051                 c->cputype = CPU_5KE;
1052                 c->writecombine = _CACHE_UNCACHED;
1053                 __cpu_name[cpu] = "MIPS 5KE";
1054                 break;
1055         case PRID_IMP_20KC:
1056                 c->cputype = CPU_20KC;
1057                 c->writecombine = _CACHE_UNCACHED;
1058                 __cpu_name[cpu] = "MIPS 20Kc";
1059                 break;
1060         case PRID_IMP_24K:
1061                 c->cputype = CPU_24K;
1062                 c->writecombine = _CACHE_UNCACHED;
1063                 __cpu_name[cpu] = "MIPS 24Kc";
1064                 break;
1065         case PRID_IMP_24KE:
1066                 c->cputype = CPU_24K;
1067                 c->writecombine = _CACHE_UNCACHED;
1068                 __cpu_name[cpu] = "MIPS 24KEc";
1069                 break;
1070         case PRID_IMP_25KF:
1071                 c->cputype = CPU_25KF;
1072                 c->writecombine = _CACHE_UNCACHED;
1073                 __cpu_name[cpu] = "MIPS 25Kc";
1074                 break;
1075         case PRID_IMP_34K:
1076                 c->cputype = CPU_34K;
1077                 c->writecombine = _CACHE_UNCACHED;
1078                 __cpu_name[cpu] = "MIPS 34Kc";
1079                 break;
1080         case PRID_IMP_74K:
1081                 c->cputype = CPU_74K;
1082                 c->writecombine = _CACHE_UNCACHED;
1083                 __cpu_name[cpu] = "MIPS 74Kc";
1084                 break;
1085         case PRID_IMP_M14KC:
1086                 c->cputype = CPU_M14KC;
1087                 c->writecombine = _CACHE_UNCACHED;
1088                 __cpu_name[cpu] = "MIPS M14Kc";
1089                 break;
1090         case PRID_IMP_M14KEC:
1091                 c->cputype = CPU_M14KEC;
1092                 c->writecombine = _CACHE_UNCACHED;
1093                 __cpu_name[cpu] = "MIPS M14KEc";
1094                 break;
1095         case PRID_IMP_1004K:
1096                 c->cputype = CPU_1004K;
1097                 c->writecombine = _CACHE_UNCACHED;
1098                 __cpu_name[cpu] = "MIPS 1004Kc";
1099                 break;
1100         case PRID_IMP_1074K:
1101                 c->cputype = CPU_1074K;
1102                 c->writecombine = _CACHE_UNCACHED;
1103                 __cpu_name[cpu] = "MIPS 1074Kc";
1104                 break;
1105         case PRID_IMP_INTERAPTIV_UP:
1106                 c->cputype = CPU_INTERAPTIV;
1107                 __cpu_name[cpu] = "MIPS interAptiv";
1108                 break;
1109         case PRID_IMP_INTERAPTIV_MP:
1110                 c->cputype = CPU_INTERAPTIV;
1111                 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1112                 break;
1113         case PRID_IMP_PROAPTIV_UP:
1114                 c->cputype = CPU_PROAPTIV;
1115                 __cpu_name[cpu] = "MIPS proAptiv";
1116                 break;
1117         case PRID_IMP_PROAPTIV_MP:
1118                 c->cputype = CPU_PROAPTIV;
1119                 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1120                 break;
1121         case PRID_IMP_P5600:
1122                 c->cputype = CPU_P5600;
1123                 __cpu_name[cpu] = "MIPS P5600";
1124                 break;
1125         case PRID_IMP_M5150:
1126                 c->cputype = CPU_M5150;
1127                 __cpu_name[cpu] = "MIPS M5150";
1128                 break;
1129         }
1130
1131         decode_configs(c);
1132
1133         spram_config();
1134 }
1135
1136 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1137 {
1138         decode_configs(c);
1139         switch (c->processor_id & PRID_IMP_MASK) {
1140         case PRID_IMP_AU1_REV1:
1141         case PRID_IMP_AU1_REV2:
1142                 c->cputype = CPU_ALCHEMY;
1143                 switch ((c->processor_id >> 24) & 0xff) {
1144                 case 0:
1145                         __cpu_name[cpu] = "Au1000";
1146                         break;
1147                 case 1:
1148                         __cpu_name[cpu] = "Au1500";
1149                         break;
1150                 case 2:
1151                         __cpu_name[cpu] = "Au1100";
1152                         break;
1153                 case 3:
1154                         __cpu_name[cpu] = "Au1550";
1155                         break;
1156                 case 4:
1157                         __cpu_name[cpu] = "Au1200";
1158                         if ((c->processor_id & PRID_REV_MASK) == 2)
1159                                 __cpu_name[cpu] = "Au1250";
1160                         break;
1161                 case 5:
1162                         __cpu_name[cpu] = "Au1210";
1163                         break;
1164                 default:
1165                         __cpu_name[cpu] = "Au1xxx";
1166                         break;
1167                 }
1168                 break;
1169         }
1170 }
1171
1172 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1173 {
1174         decode_configs(c);
1175
1176         c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1177         switch (c->processor_id & PRID_IMP_MASK) {
1178         case PRID_IMP_SB1:
1179                 c->cputype = CPU_SB1;
1180                 __cpu_name[cpu] = "SiByte SB1";
1181                 /* FPU in pass1 is known to have issues. */
1182                 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1183                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1184                 break;
1185         case PRID_IMP_SB1A:
1186                 c->cputype = CPU_SB1A;
1187                 __cpu_name[cpu] = "SiByte SB1A";
1188                 break;
1189         }
1190 }
1191
1192 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1193 {
1194         decode_configs(c);
1195         switch (c->processor_id & PRID_IMP_MASK) {
1196         case PRID_IMP_SR71000:
1197                 c->cputype = CPU_SR71000;
1198                 __cpu_name[cpu] = "Sandcraft SR71000";
1199                 c->scache.ways = 8;
1200                 c->tlbsize = 64;
1201                 break;
1202         }
1203 }
1204
1205 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1206 {
1207         decode_configs(c);
1208         switch (c->processor_id & PRID_IMP_MASK) {
1209         case PRID_IMP_PR4450:
1210                 c->cputype = CPU_PR4450;
1211                 __cpu_name[cpu] = "Philips PR4450";
1212                 set_isa(c, MIPS_CPU_ISA_M32R1);
1213                 break;
1214         }
1215 }
1216
1217 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1218 {
1219         decode_configs(c);
1220         switch (c->processor_id & PRID_IMP_MASK) {
1221         case PRID_IMP_BMIPS32_REV4:
1222         case PRID_IMP_BMIPS32_REV8:
1223                 c->cputype = CPU_BMIPS32;
1224                 __cpu_name[cpu] = "Broadcom BMIPS32";
1225                 set_elf_platform(cpu, "bmips32");
1226                 break;
1227         case PRID_IMP_BMIPS3300:
1228         case PRID_IMP_BMIPS3300_ALT:
1229         case PRID_IMP_BMIPS3300_BUG:
1230                 c->cputype = CPU_BMIPS3300;
1231                 __cpu_name[cpu] = "Broadcom BMIPS3300";
1232                 set_elf_platform(cpu, "bmips3300");
1233                 break;
1234         case PRID_IMP_BMIPS43XX: {
1235                 int rev = c->processor_id & PRID_REV_MASK;
1236
1237                 if (rev >= PRID_REV_BMIPS4380_LO &&
1238                                 rev <= PRID_REV_BMIPS4380_HI) {
1239                         c->cputype = CPU_BMIPS4380;
1240                         __cpu_name[cpu] = "Broadcom BMIPS4380";
1241                         set_elf_platform(cpu, "bmips4380");
1242                 } else {
1243                         c->cputype = CPU_BMIPS4350;
1244                         __cpu_name[cpu] = "Broadcom BMIPS4350";
1245                         set_elf_platform(cpu, "bmips4350");
1246                 }
1247                 break;
1248         }
1249         case PRID_IMP_BMIPS5000:
1250         case PRID_IMP_BMIPS5200:
1251                 c->cputype = CPU_BMIPS5000;
1252                 __cpu_name[cpu] = "Broadcom BMIPS5000";
1253                 set_elf_platform(cpu, "bmips5000");
1254                 c->options |= MIPS_CPU_ULRI;
1255                 break;
1256         }
1257 }
1258
1259 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1260 {
1261         decode_configs(c);
1262         switch (c->processor_id & PRID_IMP_MASK) {
1263         case PRID_IMP_CAVIUM_CN38XX:
1264         case PRID_IMP_CAVIUM_CN31XX:
1265         case PRID_IMP_CAVIUM_CN30XX:
1266                 c->cputype = CPU_CAVIUM_OCTEON;
1267                 __cpu_name[cpu] = "Cavium Octeon";
1268                 goto platform;
1269         case PRID_IMP_CAVIUM_CN58XX:
1270         case PRID_IMP_CAVIUM_CN56XX:
1271         case PRID_IMP_CAVIUM_CN50XX:
1272         case PRID_IMP_CAVIUM_CN52XX:
1273                 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1274                 __cpu_name[cpu] = "Cavium Octeon+";
1275 platform:
1276                 set_elf_platform(cpu, "octeon");
1277                 break;
1278         case PRID_IMP_CAVIUM_CN61XX:
1279         case PRID_IMP_CAVIUM_CN63XX:
1280         case PRID_IMP_CAVIUM_CN66XX:
1281         case PRID_IMP_CAVIUM_CN68XX:
1282         case PRID_IMP_CAVIUM_CNF71XX:
1283                 c->cputype = CPU_CAVIUM_OCTEON2;
1284                 __cpu_name[cpu] = "Cavium Octeon II";
1285                 set_elf_platform(cpu, "octeon2");
1286                 break;
1287         case PRID_IMP_CAVIUM_CN70XX:
1288         case PRID_IMP_CAVIUM_CN78XX:
1289                 c->cputype = CPU_CAVIUM_OCTEON3;
1290                 __cpu_name[cpu] = "Cavium Octeon III";
1291                 set_elf_platform(cpu, "octeon3");
1292                 break;
1293         default:
1294                 printk(KERN_INFO "Unknown Octeon chip!\n");
1295                 c->cputype = CPU_UNKNOWN;
1296                 break;
1297         }
1298 }
1299
1300 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1301 {
1302         decode_configs(c);
1303         /* JZRISC does not implement the CP0 counter. */
1304         c->options &= ~MIPS_CPU_COUNTER;
1305         BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1306         switch (c->processor_id & PRID_IMP_MASK) {
1307         case PRID_IMP_JZRISC:
1308                 c->cputype = CPU_JZRISC;
1309                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1310                 __cpu_name[cpu] = "Ingenic JZRISC";
1311                 break;
1312         default:
1313                 panic("Unknown Ingenic Processor ID!");
1314                 break;
1315         }
1316 }
1317
1318 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1319 {
1320         decode_configs(c);
1321
1322         if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1323                 c->cputype = CPU_ALCHEMY;
1324                 __cpu_name[cpu] = "Au1300";
1325                 /* following stuff is not for Alchemy */
1326                 return;
1327         }
1328
1329         c->options = (MIPS_CPU_TLB       |
1330                         MIPS_CPU_4KEX    |
1331                         MIPS_CPU_COUNTER |
1332                         MIPS_CPU_DIVEC   |
1333                         MIPS_CPU_WATCH   |
1334                         MIPS_CPU_EJTAG   |
1335                         MIPS_CPU_LLSC);
1336
1337         switch (c->processor_id & PRID_IMP_MASK) {
1338         case PRID_IMP_NETLOGIC_XLP2XX:
1339         case PRID_IMP_NETLOGIC_XLP9XX:
1340         case PRID_IMP_NETLOGIC_XLP5XX:
1341                 c->cputype = CPU_XLP;
1342                 __cpu_name[cpu] = "Broadcom XLPII";
1343                 break;
1344
1345         case PRID_IMP_NETLOGIC_XLP8XX:
1346         case PRID_IMP_NETLOGIC_XLP3XX:
1347                 c->cputype = CPU_XLP;
1348                 __cpu_name[cpu] = "Netlogic XLP";
1349                 break;
1350
1351         case PRID_IMP_NETLOGIC_XLR732:
1352         case PRID_IMP_NETLOGIC_XLR716:
1353         case PRID_IMP_NETLOGIC_XLR532:
1354         case PRID_IMP_NETLOGIC_XLR308:
1355         case PRID_IMP_NETLOGIC_XLR532C:
1356         case PRID_IMP_NETLOGIC_XLR516C:
1357         case PRID_IMP_NETLOGIC_XLR508C:
1358         case PRID_IMP_NETLOGIC_XLR308C:
1359                 c->cputype = CPU_XLR;
1360                 __cpu_name[cpu] = "Netlogic XLR";
1361                 break;
1362
1363         case PRID_IMP_NETLOGIC_XLS608:
1364         case PRID_IMP_NETLOGIC_XLS408:
1365         case PRID_IMP_NETLOGIC_XLS404:
1366         case PRID_IMP_NETLOGIC_XLS208:
1367         case PRID_IMP_NETLOGIC_XLS204:
1368         case PRID_IMP_NETLOGIC_XLS108:
1369         case PRID_IMP_NETLOGIC_XLS104:
1370         case PRID_IMP_NETLOGIC_XLS616B:
1371         case PRID_IMP_NETLOGIC_XLS608B:
1372         case PRID_IMP_NETLOGIC_XLS416B:
1373         case PRID_IMP_NETLOGIC_XLS412B:
1374         case PRID_IMP_NETLOGIC_XLS408B:
1375         case PRID_IMP_NETLOGIC_XLS404B:
1376                 c->cputype = CPU_XLR;
1377                 __cpu_name[cpu] = "Netlogic XLS";
1378                 break;
1379
1380         default:
1381                 pr_info("Unknown Netlogic chip id [%02x]!\n",
1382                        c->processor_id);
1383                 c->cputype = CPU_XLR;
1384                 break;
1385         }
1386
1387         if (c->cputype == CPU_XLP) {
1388                 set_isa(c, MIPS_CPU_ISA_M64R2);
1389                 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1390                 /* This will be updated again after all threads are woken up */
1391                 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1392         } else {
1393                 set_isa(c, MIPS_CPU_ISA_M64R1);
1394                 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1395         }
1396         c->kscratch_mask = 0xf;
1397 }
1398
1399 #ifdef CONFIG_64BIT
1400 /* For use by uaccess.h */
1401 u64 __ua_limit;
1402 EXPORT_SYMBOL(__ua_limit);
1403 #endif
1404
1405 const char *__cpu_name[NR_CPUS];
1406 const char *__elf_platform;
1407
1408 void cpu_probe(void)
1409 {
1410         struct cpuinfo_mips *c = &current_cpu_data;
1411         unsigned int cpu = smp_processor_id();
1412
1413         c->processor_id = PRID_IMP_UNKNOWN;
1414         c->fpu_id       = FPIR_IMP_NONE;
1415         c->cputype      = CPU_UNKNOWN;
1416         c->writecombine = _CACHE_UNCACHED;
1417
1418         c->fpu_csr31    = FPU_CSR_RN;
1419         c->fpu_msk31    = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1420
1421         c->processor_id = read_c0_prid();
1422         switch (c->processor_id & PRID_COMP_MASK) {
1423         case PRID_COMP_LEGACY:
1424                 cpu_probe_legacy(c, cpu);
1425                 break;
1426         case PRID_COMP_MIPS:
1427                 cpu_probe_mips(c, cpu);
1428                 break;
1429         case PRID_COMP_ALCHEMY:
1430                 cpu_probe_alchemy(c, cpu);
1431                 break;
1432         case PRID_COMP_SIBYTE:
1433                 cpu_probe_sibyte(c, cpu);
1434                 break;
1435         case PRID_COMP_BROADCOM:
1436                 cpu_probe_broadcom(c, cpu);
1437                 break;
1438         case PRID_COMP_SANDCRAFT:
1439                 cpu_probe_sandcraft(c, cpu);
1440                 break;
1441         case PRID_COMP_NXP:
1442                 cpu_probe_nxp(c, cpu);
1443                 break;
1444         case PRID_COMP_CAVIUM:
1445                 cpu_probe_cavium(c, cpu);
1446                 break;
1447         case PRID_COMP_INGENIC:
1448                 cpu_probe_ingenic(c, cpu);
1449                 break;
1450         case PRID_COMP_NETLOGIC:
1451                 cpu_probe_netlogic(c, cpu);
1452                 break;
1453         }
1454
1455         BUG_ON(!__cpu_name[cpu]);
1456         BUG_ON(c->cputype == CPU_UNKNOWN);
1457
1458         /*
1459          * Platform code can force the cpu type to optimize code
1460          * generation. In that case be sure the cpu type is correctly
1461          * manually setup otherwise it could trigger some nasty bugs.
1462          */
1463         BUG_ON(current_cpu_type() != c->cputype);
1464
1465         if (mips_fpu_disabled)
1466                 c->options &= ~MIPS_CPU_FPU;
1467
1468         if (mips_dsp_disabled)
1469                 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1470
1471         if (mips_htw_disabled) {
1472                 c->options &= ~MIPS_CPU_HTW;
1473                 write_c0_pwctl(read_c0_pwctl() &
1474                                ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1475         }
1476
1477         if (c->options & MIPS_CPU_FPU)
1478                 cpu_set_fpu_opts(c);
1479         else
1480                 cpu_set_nofpu_opts(c);
1481
1482         if (cpu_has_mips_r2_r6) {
1483                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1484                 /* R2 has Performance Counter Interrupt indicator */
1485                 c->options |= MIPS_CPU_PCI;
1486         }
1487         else
1488                 c->srsets = 1;
1489
1490         if (cpu_has_msa) {
1491                 c->msa_id = cpu_get_msa_id();
1492                 WARN(c->msa_id & MSA_IR_WRPF,
1493                      "Vector register partitioning unimplemented!");
1494         }
1495
1496         cpu_probe_vmbits(c);
1497
1498 #ifdef CONFIG_64BIT
1499         if (cpu == 0)
1500                 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1501 #endif
1502 }
1503
1504 void cpu_report(void)
1505 {
1506         struct cpuinfo_mips *c = &current_cpu_data;
1507
1508         pr_info("CPU%d revision is: %08x (%s)\n",
1509                 smp_processor_id(), c->processor_id, cpu_name_string());
1510         if (c->options & MIPS_CPU_FPU)
1511                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1512         if (cpu_has_msa)
1513                 pr_info("MSA revision is: %08x\n", c->msa_id);
1514 }