2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
24 #include <asm/mipsregs.h>
25 #include <asm/watch.h>
27 #include <asm/spram.h>
28 #include <asm/uaccess.h>
31 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
32 * the implementation of the "wait" feature differs between CPU families. This
33 * points to the function that implements CPU specific wait.
34 * The wait instruction stops the pipeline and reduces the power consumption of
37 void (*cpu_wait)(void);
38 EXPORT_SYMBOL(cpu_wait);
40 static void r3081_wait(void)
42 unsigned long cfg = read_c0_conf();
43 write_c0_conf(cfg | R30XX_CONF_HALT);
46 static void r39xx_wait(void)
50 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
54 extern void r4k_wait(void);
57 * This variant is preferable as it allows testing need_resched and going to
58 * sleep depending on the outcome atomically. Unfortunately the "It is
59 * implementation-dependent whether the pipeline restarts when a non-enabled
60 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
61 * using this version a gamble.
63 void r4k_wait_irqoff(void)
67 __asm__(" .set push \n"
72 __asm__(" .globl __pastwait \n"
77 * The RM7000 variant has to handle erratum 38. The workaround is to not
78 * have any pending stores when the WAIT instruction is executed.
80 static void rm7k_wait_irqoff(void)
90 " mtc0 $1, $12 # stalls until W stage \n"
92 " mtc0 $1, $12 # stalls until W stage \n"
98 * The Au1xxx wait is available only if using 32khz counter or
99 * external timer source, but specifically not CP0 Counter.
100 * alchemy/common/time.c may override cpu_wait!
102 static void au1k_wait(void)
104 __asm__(" .set mips3 \n"
105 " cache 0x14, 0(%0) \n"
106 " cache 0x14, 32(%0) \n"
115 : : "r" (au1k_wait));
118 static int __initdata nowait;
120 static int __init wait_disable(char *s)
127 __setup("nowait", wait_disable);
129 static int __cpuinitdata mips_fpu_disabled;
131 static int __init fpu_disable(char *s)
133 cpu_data[0].options &= ~MIPS_CPU_FPU;
134 mips_fpu_disabled = 1;
139 __setup("nofpu", fpu_disable);
141 int __cpuinitdata mips_dsp_disabled;
143 static int __init dsp_disable(char *s)
145 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
146 mips_dsp_disabled = 1;
151 __setup("nodsp", dsp_disable);
153 void __init check_wait(void)
155 struct cpuinfo_mips *c = ¤t_cpu_data;
158 printk("Wait instruction disabled.\n");
162 switch (c->cputype) {
165 cpu_wait = r3081_wait;
168 cpu_wait = r39xx_wait;
171 /* case CPU_R4300: */
189 case CPU_CAVIUM_OCTEON:
190 case CPU_CAVIUM_OCTEON_PLUS:
191 case CPU_CAVIUM_OCTEON2:
200 cpu_wait = rm7k_wait_irqoff;
209 if (read_c0_config7() & MIPS_CONF7_WII)
210 cpu_wait = r4k_wait_irqoff;
215 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
216 cpu_wait = r4k_wait_irqoff;
220 cpu_wait = r4k_wait_irqoff;
223 cpu_wait = au1k_wait;
227 * WAIT on Rev1.0 has E1, E2, E3 and E16.
228 * WAIT on Rev2.0 and Rev3.0 has E16.
229 * Rev3.1 WAIT is nop, why bother
231 if ((c->processor_id & 0xff) <= 0x64)
235 * Another rev is incremeting c0_count at a reduced clock
236 * rate while in WAIT mode. So we basically have the choice
237 * between using the cp0 timer as clocksource or avoiding
238 * the WAIT instruction. Until more details are known,
239 * disable the use of WAIT for 20Kc entirely.
244 if ((c->processor_id & 0x00ff) >= 0x40)
252 static inline void check_errata(void)
254 struct cpuinfo_mips *c = ¤t_cpu_data;
256 switch (c->cputype) {
259 * Erratum "RPS May Cause Incorrect Instruction Execution"
260 * This code only handles VPE0, any SMP/SMTC/RTOS code
261 * making use of VPE1 will be responsable for that VPE.
263 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
264 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
271 void __init check_bugs32(void)
277 * Probe whether cpu has config register by trying to play with
278 * alternate cache bit and see whether it matters.
279 * It's used by cpu_probe to distinguish between R3000A and R3081.
281 static inline int cpu_has_confreg(void)
283 #ifdef CONFIG_CPU_R3000
284 extern unsigned long r3k_cache_size(unsigned long);
285 unsigned long size1, size2;
286 unsigned long cfg = read_c0_conf();
288 size1 = r3k_cache_size(ST0_ISC);
289 write_c0_conf(cfg ^ R30XX_CONF_AC);
290 size2 = r3k_cache_size(ST0_ISC);
292 return size1 != size2;
298 static inline void set_elf_platform(int cpu, const char *plat)
301 __elf_platform = plat;
305 * Get the FPU Implementation/Revision.
307 static inline unsigned long cpu_get_fpu_id(void)
309 unsigned long tmp, fpu_id;
311 tmp = read_c0_status();
313 fpu_id = read_32bit_cp1_register(CP1_REVISION);
314 write_c0_status(tmp);
319 * Check the CPU has an FPU the official way.
321 static inline int __cpu_has_fpu(void)
323 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
326 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
328 #ifdef __NEED_VMBITS_PROBE
329 write_c0_entryhi(0x3fffffffffffe000ULL);
330 back_to_back_c0_hazard();
331 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
335 static void __cpuinit set_isa(struct cpuinfo_mips *c, unsigned int isa)
338 case MIPS_CPU_ISA_M64R2:
339 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
340 case MIPS_CPU_ISA_M64R1:
341 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
343 c->isa_level |= MIPS_CPU_ISA_V;
344 case MIPS_CPU_ISA_IV:
345 c->isa_level |= MIPS_CPU_ISA_IV;
346 case MIPS_CPU_ISA_III:
347 c->isa_level |= MIPS_CPU_ISA_I | MIPS_CPU_ISA_II |
351 case MIPS_CPU_ISA_M32R2:
352 c->isa_level |= MIPS_CPU_ISA_M32R2;
353 case MIPS_CPU_ISA_M32R1:
354 c->isa_level |= MIPS_CPU_ISA_M32R1;
355 case MIPS_CPU_ISA_II:
356 c->isa_level |= MIPS_CPU_ISA_II;
358 c->isa_level |= MIPS_CPU_ISA_I;
363 static char unknown_isa[] __cpuinitdata = KERN_ERR \
364 "Unsupported ISA type, c0.config0: %d.";
366 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
368 unsigned int config0;
371 config0 = read_c0_config();
373 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
374 c->options |= MIPS_CPU_TLB;
375 isa = (config0 & MIPS_CONF_AT) >> 13;
378 switch ((config0 & MIPS_CONF_AR) >> 10) {
380 set_isa(c, MIPS_CPU_ISA_M32R1);
383 set_isa(c, MIPS_CPU_ISA_M32R2);
390 switch ((config0 & MIPS_CONF_AR) >> 10) {
392 set_isa(c, MIPS_CPU_ISA_M64R1);
395 set_isa(c, MIPS_CPU_ISA_M64R2);
405 return config0 & MIPS_CONF_M;
408 panic(unknown_isa, config0);
411 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
413 unsigned int config1;
415 config1 = read_c0_config1();
417 if (config1 & MIPS_CONF1_MD)
418 c->ases |= MIPS_ASE_MDMX;
419 if (config1 & MIPS_CONF1_WR)
420 c->options |= MIPS_CPU_WATCH;
421 if (config1 & MIPS_CONF1_CA)
422 c->ases |= MIPS_ASE_MIPS16;
423 if (config1 & MIPS_CONF1_EP)
424 c->options |= MIPS_CPU_EJTAG;
425 if (config1 & MIPS_CONF1_FP) {
426 c->options |= MIPS_CPU_FPU;
427 c->options |= MIPS_CPU_32FPR;
430 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
432 return config1 & MIPS_CONF_M;
435 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
437 unsigned int config2;
439 config2 = read_c0_config2();
441 if (config2 & MIPS_CONF2_SL)
442 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
444 return config2 & MIPS_CONF_M;
447 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
449 unsigned int config3;
451 config3 = read_c0_config3();
453 if (config3 & MIPS_CONF3_SM) {
454 c->ases |= MIPS_ASE_SMARTMIPS;
455 c->options |= MIPS_CPU_RIXI;
457 if (config3 & MIPS_CONF3_RXI)
458 c->options |= MIPS_CPU_RIXI;
459 if (config3 & MIPS_CONF3_DSP)
460 c->ases |= MIPS_ASE_DSP;
461 if (config3 & MIPS_CONF3_DSP2P)
462 c->ases |= MIPS_ASE_DSP2P;
463 if (config3 & MIPS_CONF3_VINT)
464 c->options |= MIPS_CPU_VINT;
465 if (config3 & MIPS_CONF3_VEIC)
466 c->options |= MIPS_CPU_VEIC;
467 if (config3 & MIPS_CONF3_MT)
468 c->ases |= MIPS_ASE_MIPSMT;
469 if (config3 & MIPS_CONF3_ULRI)
470 c->options |= MIPS_CPU_ULRI;
471 if (config3 & MIPS_CONF3_ISA)
472 c->options |= MIPS_CPU_MICROMIPS;
473 #ifdef CONFIG_CPU_MICROMIPS
474 write_c0_config3(read_c0_config3() | MIPS_CONF3_ISA_OE);
476 if (config3 & MIPS_CONF3_VZ)
477 c->ases |= MIPS_ASE_VZ;
479 return config3 & MIPS_CONF_M;
482 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
484 unsigned int config4;
486 config4 = read_c0_config4();
488 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
490 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
492 c->kscratch_mask = (config4 >> 16) & 0xff;
494 return config4 & MIPS_CONF_M;
497 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
501 /* MIPS32 or MIPS64 compliant CPU. */
502 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
503 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
505 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
507 ok = decode_config0(c); /* Read Config registers. */
508 BUG_ON(!ok); /* Arch spec violation! */
510 ok = decode_config1(c);
512 ok = decode_config2(c);
514 ok = decode_config3(c);
516 ok = decode_config4(c);
518 mips_probe_watch_registers(c);
521 c->core = read_c0_ebase() & 0x3ff;
524 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
527 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
529 switch (c->processor_id & 0xff00) {
531 c->cputype = CPU_R2000;
532 __cpu_name[cpu] = "R2000";
533 set_isa(c, MIPS_CPU_ISA_I);
534 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
537 c->options |= MIPS_CPU_FPU;
541 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
542 if (cpu_has_confreg()) {
543 c->cputype = CPU_R3081E;
544 __cpu_name[cpu] = "R3081";
546 c->cputype = CPU_R3000A;
547 __cpu_name[cpu] = "R3000A";
550 c->cputype = CPU_R3000;
551 __cpu_name[cpu] = "R3000";
553 set_isa(c, MIPS_CPU_ISA_I);
554 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
557 c->options |= MIPS_CPU_FPU;
561 if (read_c0_config() & CONF_SC) {
562 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
563 c->cputype = CPU_R4400PC;
564 __cpu_name[cpu] = "R4400PC";
566 c->cputype = CPU_R4000PC;
567 __cpu_name[cpu] = "R4000PC";
570 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
571 c->cputype = CPU_R4400SC;
572 __cpu_name[cpu] = "R4400SC";
574 c->cputype = CPU_R4000SC;
575 __cpu_name[cpu] = "R4000SC";
579 set_isa(c, MIPS_CPU_ISA_III);
580 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
581 MIPS_CPU_WATCH | MIPS_CPU_VCE |
585 case PRID_IMP_VR41XX:
586 set_isa(c, MIPS_CPU_ISA_III);
587 c->options = R4K_OPTS;
589 switch (c->processor_id & 0xf0) {
590 case PRID_REV_VR4111:
591 c->cputype = CPU_VR4111;
592 __cpu_name[cpu] = "NEC VR4111";
594 case PRID_REV_VR4121:
595 c->cputype = CPU_VR4121;
596 __cpu_name[cpu] = "NEC VR4121";
598 case PRID_REV_VR4122:
599 if ((c->processor_id & 0xf) < 0x3) {
600 c->cputype = CPU_VR4122;
601 __cpu_name[cpu] = "NEC VR4122";
603 c->cputype = CPU_VR4181A;
604 __cpu_name[cpu] = "NEC VR4181A";
607 case PRID_REV_VR4130:
608 if ((c->processor_id & 0xf) < 0x4) {
609 c->cputype = CPU_VR4131;
610 __cpu_name[cpu] = "NEC VR4131";
612 c->cputype = CPU_VR4133;
613 c->options |= MIPS_CPU_LLSC;
614 __cpu_name[cpu] = "NEC VR4133";
618 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
619 c->cputype = CPU_VR41XX;
620 __cpu_name[cpu] = "NEC Vr41xx";
625 c->cputype = CPU_R4300;
626 __cpu_name[cpu] = "R4300";
627 set_isa(c, MIPS_CPU_ISA_III);
628 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
633 c->cputype = CPU_R4600;
634 __cpu_name[cpu] = "R4600";
635 set_isa(c, MIPS_CPU_ISA_III);
636 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
643 * This processor doesn't have an MMU, so it's not
644 * "real easy" to run Linux on it. It is left purely
645 * for documentation. Commented out because it shares
646 * it's c0_prid id number with the TX3900.
648 c->cputype = CPU_R4650;
649 __cpu_name[cpu] = "R4650";
650 set_isa(c, MIPS_CPU_ISA_III);
651 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
656 set_isa(c, MIPS_CPU_ISA_I);
657 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
659 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
660 c->cputype = CPU_TX3927;
661 __cpu_name[cpu] = "TX3927";
664 switch (c->processor_id & 0xff) {
665 case PRID_REV_TX3912:
666 c->cputype = CPU_TX3912;
667 __cpu_name[cpu] = "TX3912";
670 case PRID_REV_TX3922:
671 c->cputype = CPU_TX3922;
672 __cpu_name[cpu] = "TX3922";
679 c->cputype = CPU_R4700;
680 __cpu_name[cpu] = "R4700";
681 set_isa(c, MIPS_CPU_ISA_III);
682 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
687 c->cputype = CPU_TX49XX;
688 __cpu_name[cpu] = "R49XX";
689 set_isa(c, MIPS_CPU_ISA_III);
690 c->options = R4K_OPTS | MIPS_CPU_LLSC;
691 if (!(c->processor_id & 0x08))
692 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
696 c->cputype = CPU_R5000;
697 __cpu_name[cpu] = "R5000";
698 set_isa(c, MIPS_CPU_ISA_IV);
699 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
704 c->cputype = CPU_R5432;
705 __cpu_name[cpu] = "R5432";
706 set_isa(c, MIPS_CPU_ISA_IV);
707 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
708 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
712 c->cputype = CPU_R5500;
713 __cpu_name[cpu] = "R5500";
714 set_isa(c, MIPS_CPU_ISA_IV);
715 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
716 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
719 case PRID_IMP_NEVADA:
720 c->cputype = CPU_NEVADA;
721 __cpu_name[cpu] = "Nevada";
722 set_isa(c, MIPS_CPU_ISA_IV);
723 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
724 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
728 c->cputype = CPU_R6000;
729 __cpu_name[cpu] = "R6000";
730 set_isa(c, MIPS_CPU_ISA_II);
731 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
735 case PRID_IMP_R6000A:
736 c->cputype = CPU_R6000A;
737 __cpu_name[cpu] = "R6000A";
738 set_isa(c, MIPS_CPU_ISA_II);
739 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
743 case PRID_IMP_RM7000:
744 c->cputype = CPU_RM7000;
745 __cpu_name[cpu] = "RM7000";
746 set_isa(c, MIPS_CPU_ISA_IV);
747 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
750 * Undocumented RM7000: Bit 29 in the info register of
751 * the RM7000 v2.0 indicates if the TLB has 48 or 64
754 * 29 1 => 64 entry JTLB
757 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
759 case PRID_IMP_RM9000:
760 c->cputype = CPU_RM9000;
761 __cpu_name[cpu] = "RM9000";
762 set_isa(c, MIPS_CPU_ISA_IV);
763 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
766 * Bit 29 in the info register of the RM9000
767 * indicates if the TLB has 48 or 64 entries.
769 * 29 1 => 64 entry JTLB
772 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
775 c->cputype = CPU_R8000;
776 __cpu_name[cpu] = "RM8000";
777 set_isa(c, MIPS_CPU_ISA_IV);
778 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
779 MIPS_CPU_FPU | MIPS_CPU_32FPR |
781 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
783 case PRID_IMP_R10000:
784 c->cputype = CPU_R10000;
785 __cpu_name[cpu] = "R10000";
786 set_isa(c, MIPS_CPU_ISA_IV);
787 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
788 MIPS_CPU_FPU | MIPS_CPU_32FPR |
789 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
793 case PRID_IMP_R12000:
794 c->cputype = CPU_R12000;
795 __cpu_name[cpu] = "R12000";
796 set_isa(c, MIPS_CPU_ISA_IV);
797 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
798 MIPS_CPU_FPU | MIPS_CPU_32FPR |
799 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
803 case PRID_IMP_R14000:
804 c->cputype = CPU_R14000;
805 __cpu_name[cpu] = "R14000";
806 set_isa(c, MIPS_CPU_ISA_IV);
807 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
808 MIPS_CPU_FPU | MIPS_CPU_32FPR |
809 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
813 case PRID_IMP_LOONGSON2:
814 c->cputype = CPU_LOONGSON2;
815 __cpu_name[cpu] = "ICT Loongson-2";
817 switch (c->processor_id & PRID_REV_MASK) {
818 case PRID_REV_LOONGSON2E:
819 set_elf_platform(cpu, "loongson2e");
821 case PRID_REV_LOONGSON2F:
822 set_elf_platform(cpu, "loongson2f");
826 set_isa(c, MIPS_CPU_ISA_III);
827 c->options = R4K_OPTS |
828 MIPS_CPU_FPU | MIPS_CPU_LLSC |
832 case PRID_IMP_LOONGSON1:
835 c->cputype = CPU_LOONGSON1;
837 switch (c->processor_id & PRID_REV_MASK) {
838 case PRID_REV_LOONGSON1B:
839 __cpu_name[cpu] = "Loongson 1B";
847 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
850 switch (c->processor_id & 0xff00) {
852 c->cputype = CPU_4KC;
853 __cpu_name[cpu] = "MIPS 4Kc";
856 case PRID_IMP_4KECR2:
857 c->cputype = CPU_4KEC;
858 __cpu_name[cpu] = "MIPS 4KEc";
862 c->cputype = CPU_4KSC;
863 __cpu_name[cpu] = "MIPS 4KSc";
866 c->cputype = CPU_5KC;
867 __cpu_name[cpu] = "MIPS 5Kc";
870 c->cputype = CPU_5KE;
871 __cpu_name[cpu] = "MIPS 5KE";
874 c->cputype = CPU_20KC;
875 __cpu_name[cpu] = "MIPS 20Kc";
878 c->cputype = CPU_24K;
879 __cpu_name[cpu] = "MIPS 24Kc";
882 c->cputype = CPU_24K;
883 __cpu_name[cpu] = "MIPS 24KEc";
886 c->cputype = CPU_25KF;
887 __cpu_name[cpu] = "MIPS 25Kc";
890 c->cputype = CPU_34K;
891 __cpu_name[cpu] = "MIPS 34Kc";
894 c->cputype = CPU_74K;
895 __cpu_name[cpu] = "MIPS 74Kc";
898 c->cputype = CPU_M14KC;
899 __cpu_name[cpu] = "MIPS M14Kc";
901 case PRID_IMP_M14KEC:
902 c->cputype = CPU_M14KEC;
903 __cpu_name[cpu] = "MIPS M14KEc";
906 c->cputype = CPU_1004K;
907 __cpu_name[cpu] = "MIPS 1004Kc";
910 c->cputype = CPU_74K;
911 __cpu_name[cpu] = "MIPS 1074Kc";
918 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
921 switch (c->processor_id & 0xff00) {
922 case PRID_IMP_AU1_REV1:
923 case PRID_IMP_AU1_REV2:
924 c->cputype = CPU_ALCHEMY;
925 switch ((c->processor_id >> 24) & 0xff) {
927 __cpu_name[cpu] = "Au1000";
930 __cpu_name[cpu] = "Au1500";
933 __cpu_name[cpu] = "Au1100";
936 __cpu_name[cpu] = "Au1550";
939 __cpu_name[cpu] = "Au1200";
940 if ((c->processor_id & 0xff) == 2)
941 __cpu_name[cpu] = "Au1250";
944 __cpu_name[cpu] = "Au1210";
947 __cpu_name[cpu] = "Au1xxx";
954 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
958 switch (c->processor_id & 0xff00) {
960 c->cputype = CPU_SB1;
961 __cpu_name[cpu] = "SiByte SB1";
962 /* FPU in pass1 is known to have issues. */
963 if ((c->processor_id & 0xff) < 0x02)
964 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
967 c->cputype = CPU_SB1A;
968 __cpu_name[cpu] = "SiByte SB1A";
973 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
976 switch (c->processor_id & 0xff00) {
977 case PRID_IMP_SR71000:
978 c->cputype = CPU_SR71000;
979 __cpu_name[cpu] = "Sandcraft SR71000";
986 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
989 switch (c->processor_id & 0xff00) {
990 case PRID_IMP_PR4450:
991 c->cputype = CPU_PR4450;
992 __cpu_name[cpu] = "Philips PR4450";
993 set_isa(c, MIPS_CPU_ISA_M32R1);
998 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1001 switch (c->processor_id & 0xff00) {
1002 case PRID_IMP_BMIPS32_REV4:
1003 case PRID_IMP_BMIPS32_REV8:
1004 c->cputype = CPU_BMIPS32;
1005 __cpu_name[cpu] = "Broadcom BMIPS32";
1006 set_elf_platform(cpu, "bmips32");
1008 case PRID_IMP_BMIPS3300:
1009 case PRID_IMP_BMIPS3300_ALT:
1010 case PRID_IMP_BMIPS3300_BUG:
1011 c->cputype = CPU_BMIPS3300;
1012 __cpu_name[cpu] = "Broadcom BMIPS3300";
1013 set_elf_platform(cpu, "bmips3300");
1015 case PRID_IMP_BMIPS43XX: {
1016 int rev = c->processor_id & 0xff;
1018 if (rev >= PRID_REV_BMIPS4380_LO &&
1019 rev <= PRID_REV_BMIPS4380_HI) {
1020 c->cputype = CPU_BMIPS4380;
1021 __cpu_name[cpu] = "Broadcom BMIPS4380";
1022 set_elf_platform(cpu, "bmips4380");
1024 c->cputype = CPU_BMIPS4350;
1025 __cpu_name[cpu] = "Broadcom BMIPS4350";
1026 set_elf_platform(cpu, "bmips4350");
1030 case PRID_IMP_BMIPS5000:
1031 c->cputype = CPU_BMIPS5000;
1032 __cpu_name[cpu] = "Broadcom BMIPS5000";
1033 set_elf_platform(cpu, "bmips5000");
1034 c->options |= MIPS_CPU_ULRI;
1039 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1042 switch (c->processor_id & 0xff00) {
1043 case PRID_IMP_CAVIUM_CN38XX:
1044 case PRID_IMP_CAVIUM_CN31XX:
1045 case PRID_IMP_CAVIUM_CN30XX:
1046 c->cputype = CPU_CAVIUM_OCTEON;
1047 __cpu_name[cpu] = "Cavium Octeon";
1049 case PRID_IMP_CAVIUM_CN58XX:
1050 case PRID_IMP_CAVIUM_CN56XX:
1051 case PRID_IMP_CAVIUM_CN50XX:
1052 case PRID_IMP_CAVIUM_CN52XX:
1053 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1054 __cpu_name[cpu] = "Cavium Octeon+";
1056 set_elf_platform(cpu, "octeon");
1058 case PRID_IMP_CAVIUM_CN61XX:
1059 case PRID_IMP_CAVIUM_CN63XX:
1060 case PRID_IMP_CAVIUM_CN66XX:
1061 case PRID_IMP_CAVIUM_CN68XX:
1062 c->cputype = CPU_CAVIUM_OCTEON2;
1063 __cpu_name[cpu] = "Cavium Octeon II";
1064 set_elf_platform(cpu, "octeon2");
1067 printk(KERN_INFO "Unknown Octeon chip!\n");
1068 c->cputype = CPU_UNKNOWN;
1073 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1076 /* JZRISC does not implement the CP0 counter. */
1077 c->options &= ~MIPS_CPU_COUNTER;
1078 switch (c->processor_id & 0xff00) {
1079 case PRID_IMP_JZRISC:
1080 c->cputype = CPU_JZRISC;
1081 __cpu_name[cpu] = "Ingenic JZRISC";
1084 panic("Unknown Ingenic Processor ID!");
1089 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1093 if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) {
1094 c->cputype = CPU_ALCHEMY;
1095 __cpu_name[cpu] = "Au1300";
1096 /* following stuff is not for Alchemy */
1100 c->options = (MIPS_CPU_TLB |
1108 switch (c->processor_id & 0xff00) {
1109 case PRID_IMP_NETLOGIC_XLP8XX:
1110 case PRID_IMP_NETLOGIC_XLP3XX:
1111 c->cputype = CPU_XLP;
1112 __cpu_name[cpu] = "Netlogic XLP";
1115 case PRID_IMP_NETLOGIC_XLR732:
1116 case PRID_IMP_NETLOGIC_XLR716:
1117 case PRID_IMP_NETLOGIC_XLR532:
1118 case PRID_IMP_NETLOGIC_XLR308:
1119 case PRID_IMP_NETLOGIC_XLR532C:
1120 case PRID_IMP_NETLOGIC_XLR516C:
1121 case PRID_IMP_NETLOGIC_XLR508C:
1122 case PRID_IMP_NETLOGIC_XLR308C:
1123 c->cputype = CPU_XLR;
1124 __cpu_name[cpu] = "Netlogic XLR";
1127 case PRID_IMP_NETLOGIC_XLS608:
1128 case PRID_IMP_NETLOGIC_XLS408:
1129 case PRID_IMP_NETLOGIC_XLS404:
1130 case PRID_IMP_NETLOGIC_XLS208:
1131 case PRID_IMP_NETLOGIC_XLS204:
1132 case PRID_IMP_NETLOGIC_XLS108:
1133 case PRID_IMP_NETLOGIC_XLS104:
1134 case PRID_IMP_NETLOGIC_XLS616B:
1135 case PRID_IMP_NETLOGIC_XLS608B:
1136 case PRID_IMP_NETLOGIC_XLS416B:
1137 case PRID_IMP_NETLOGIC_XLS412B:
1138 case PRID_IMP_NETLOGIC_XLS408B:
1139 case PRID_IMP_NETLOGIC_XLS404B:
1140 c->cputype = CPU_XLR;
1141 __cpu_name[cpu] = "Netlogic XLS";
1145 pr_info("Unknown Netlogic chip id [%02x]!\n",
1147 c->cputype = CPU_XLR;
1151 if (c->cputype == CPU_XLP) {
1152 set_isa(c, MIPS_CPU_ISA_M64R2);
1153 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1154 /* This will be updated again after all threads are woken up */
1155 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1157 set_isa(c, MIPS_CPU_ISA_M64R1);
1158 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1163 /* For use by uaccess.h */
1165 EXPORT_SYMBOL(__ua_limit);
1168 const char *__cpu_name[NR_CPUS];
1169 const char *__elf_platform;
1171 __cpuinit void cpu_probe(void)
1173 struct cpuinfo_mips *c = ¤t_cpu_data;
1174 unsigned int cpu = smp_processor_id();
1176 c->processor_id = PRID_IMP_UNKNOWN;
1177 c->fpu_id = FPIR_IMP_NONE;
1178 c->cputype = CPU_UNKNOWN;
1180 c->processor_id = read_c0_prid();
1181 switch (c->processor_id & 0xff0000) {
1182 case PRID_COMP_LEGACY:
1183 cpu_probe_legacy(c, cpu);
1185 case PRID_COMP_MIPS:
1186 cpu_probe_mips(c, cpu);
1188 case PRID_COMP_ALCHEMY:
1189 cpu_probe_alchemy(c, cpu);
1191 case PRID_COMP_SIBYTE:
1192 cpu_probe_sibyte(c, cpu);
1194 case PRID_COMP_BROADCOM:
1195 cpu_probe_broadcom(c, cpu);
1197 case PRID_COMP_SANDCRAFT:
1198 cpu_probe_sandcraft(c, cpu);
1201 cpu_probe_nxp(c, cpu);
1203 case PRID_COMP_CAVIUM:
1204 cpu_probe_cavium(c, cpu);
1206 case PRID_COMP_INGENIC:
1207 cpu_probe_ingenic(c, cpu);
1209 case PRID_COMP_NETLOGIC:
1210 cpu_probe_netlogic(c, cpu);
1214 BUG_ON(!__cpu_name[cpu]);
1215 BUG_ON(c->cputype == CPU_UNKNOWN);
1218 * Platform code can force the cpu type to optimize code
1219 * generation. In that case be sure the cpu type is correctly
1220 * manually setup otherwise it could trigger some nasty bugs.
1222 BUG_ON(current_cpu_type() != c->cputype);
1224 if (mips_fpu_disabled)
1225 c->options &= ~MIPS_CPU_FPU;
1227 if (mips_dsp_disabled)
1228 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1230 if (c->options & MIPS_CPU_FPU) {
1231 c->fpu_id = cpu_get_fpu_id();
1233 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1234 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
1235 if (c->fpu_id & MIPS_FPIR_3D)
1236 c->ases |= MIPS_ASE_MIPS3D;
1240 if (cpu_has_mips_r2) {
1241 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1242 /* R2 has Performance Counter Interrupt indicator */
1243 c->options |= MIPS_CPU_PCI;
1248 cpu_probe_vmbits(c);
1252 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1256 __cpuinit void cpu_report(void)
1258 struct cpuinfo_mips *c = ¤t_cpu_data;
1260 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1261 c->processor_id, cpu_name_string());
1262 if (c->options & MIPS_CPU_FPU)
1263 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);