2 * Copyright (C) 2006 - 2008 Lemote Inc. & Insititute of Computing Technology
3 * Author: Yanhua, yanh@lemote.com
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/cpufreq.h>
11 #include <linux/platform_device.h>
13 #include <asm/clock.h>
17 static LIST_HEAD(clock_list);
18 static DEFINE_SPINLOCK(clock_lock);
19 static DEFINE_MUTEX(clock_list_sem);
21 /* Minimum CLK support */
23 DC_ZERO, DC_25PT = 2, DC_37PT, DC_50PT, DC_62PT, DC_75PT,
24 DC_87PT, DC_DISABLE, DC_RESV
27 struct cpufreq_frequency_table loongson2_clockmod_table[] = {
28 {DC_RESV, CPUFREQ_ENTRY_INVALID},
29 {DC_ZERO, CPUFREQ_ENTRY_INVALID},
37 {DC_RESV, CPUFREQ_TABLE_END},
39 EXPORT_SYMBOL_GPL(loongson2_clockmod_table);
41 static struct clk cpu_clk = {
43 .flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
47 struct clk *clk_get(struct device *dev, const char *id)
51 EXPORT_SYMBOL(clk_get);
53 static void propagate_rate(struct clk *clk)
57 list_for_each_entry(clkp, &clock_list, node) {
58 if (likely(clkp->parent != clk))
60 if (likely(clkp->ops && clkp->ops->recalc))
61 clkp->ops->recalc(clkp);
62 if (unlikely(clkp->flags & CLK_RATE_PROPAGATES))
67 int clk_enable(struct clk *clk)
71 EXPORT_SYMBOL(clk_enable);
73 void clk_disable(struct clk *clk)
76 EXPORT_SYMBOL(clk_disable);
78 unsigned long clk_get_rate(struct clk *clk)
80 return (unsigned long)clk->rate;
82 EXPORT_SYMBOL(clk_get_rate);
84 void clk_put(struct clk *clk)
87 EXPORT_SYMBOL(clk_put);
89 int clk_set_rate(struct clk *clk, unsigned long rate)
91 return clk_set_rate_ex(clk, rate, 0);
93 EXPORT_SYMBOL_GPL(clk_set_rate);
95 int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
101 if (likely(clk->ops && clk->ops->set_rate)) {
104 spin_lock_irqsave(&clock_lock, flags);
105 ret = clk->ops->set_rate(clk, rate, algo_id);
106 spin_unlock_irqrestore(&clock_lock, flags);
109 if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
112 for (i = 0; loongson2_clockmod_table[i].frequency != CPUFREQ_TABLE_END;
114 if (loongson2_clockmod_table[i].frequency ==
115 CPUFREQ_ENTRY_INVALID)
117 if (rate == loongson2_clockmod_table[i].frequency)
120 if (rate != loongson2_clockmod_table[i].frequency)
125 regval = LOONGSON_CHIPCFG0;
126 regval = (regval & ~0x7) | (loongson2_clockmod_table[i].index - 1);
127 LOONGSON_CHIPCFG0 = regval;
131 EXPORT_SYMBOL_GPL(clk_set_rate_ex);
133 long clk_round_rate(struct clk *clk, unsigned long rate)
135 if (likely(clk->ops && clk->ops->round_rate)) {
136 unsigned long flags, rounded;
138 spin_lock_irqsave(&clock_lock, flags);
139 rounded = clk->ops->round_rate(clk, rate);
140 spin_unlock_irqrestore(&clock_lock, flags);
147 EXPORT_SYMBOL_GPL(clk_round_rate);
150 * This is the simple version of Loongson-2 wait, Maybe we need do this in
151 * interrupt disabled content
154 DEFINE_SPINLOCK(loongson2_wait_lock);
155 void loongson2_cpu_wait(void)
160 spin_lock_irqsave(&loongson2_wait_lock, flags);
161 cpu_freq = LOONGSON_CHIPCFG0;
162 LOONGSON_CHIPCFG0 &= ~0x7; /* Put CPU into wait mode */
163 LOONGSON_CHIPCFG0 = cpu_freq; /* Restore CPU state */
164 spin_unlock_irqrestore(&loongson2_wait_lock, flags);
166 EXPORT_SYMBOL_GPL(loongson2_cpu_wait);
168 MODULE_AUTHOR("Yanhua <yanh@lemote.com>");
169 MODULE_DESCRIPTION("cpufreq driver for Loongson 2F");
170 MODULE_LICENSE("GPL");