2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 * Copyright (C) 2001 MIPS Technologies, Inc.
9 * Copyright (C) 2002, 2007 Maciej W. Rozycki
11 #include <linux/init.h>
14 #include <asm/asmmacro.h>
15 #include <asm/cacheops.h>
16 #include <asm/irqflags.h>
17 #include <asm/regdef.h>
18 #include <asm/fpregdef.h>
19 #include <asm/mipsregs.h>
20 #include <asm/stackframe.h>
22 #include <asm/thread_info.h>
24 #define PANIC_PIC(msg) \
37 NESTED(except_vec0_generic, 0, sp)
38 PANIC_PIC("Exception vector 0 called")
39 END(except_vec0_generic)
41 NESTED(except_vec1_generic, 0, sp)
42 PANIC_PIC("Exception vector 1 called")
43 END(except_vec1_generic)
46 * General exception vector for all other CPUs.
48 * Be careful when changing this, it has to be at most 128 bytes
49 * to fit into space reserved for the exception handler.
51 NESTED(except_vec3_generic, 0, sp)
54 #if R5432_CP0_INTERRUPT_WAR
62 PTR_L k0, exception_handlers(k1)
65 END(except_vec3_generic)
68 * General exception handler for CPUs with virtual coherency exception.
70 * Be careful when changing this, it has to be at most 256 (as a special
71 * exception) bytes to fit into space reserved for the exception handler.
73 NESTED(except_vec3_r4000, 0, sp)
83 beq k1, k0, handle_vced
85 beq k1, k0, handle_vcei
90 PTR_L k0, exception_handlers(k1)
94 * Big shit, we now may have two dirty primary cache lines for the same
95 * physical address. We can safely invalidate the line pointed to by
96 * c0_badvaddr because after return from this exception handler the
97 * load / store will be re-executed.
100 MFC0 k0, CP0_BADVADDR
101 li k1, -4 # Is this ...
102 and k0, k1 # ... really needed?
104 cache Index_Store_Tag_D, (k0)
105 cache Hit_Writeback_Inv_SD, (k0)
106 #ifdef CONFIG_PROC_FS
107 PTR_LA k0, vced_count
115 MFC0 k0, CP0_BADVADDR
116 cache Hit_Writeback_Inv_SD, (k0) # also cleans pi
117 #ifdef CONFIG_PROC_FS
118 PTR_LA k0, vcei_count
125 END(except_vec3_r4000)
129 .align 5 /* 32 byte rollback region */
133 /* start of rollback region */
134 LONG_L t0, TI_FLAGS($28)
136 andi t0, _TIF_NEED_RESCHED
143 /* end of rollback region (the region size must be power of two) */
149 .macro BUILD_ROLLBACK_PROLOGUE handler
150 FEXPORT(rollback_\handler)
155 ori k0, 0x1f /* 32 byte rollback region */
164 BUILD_ROLLBACK_PROLOGUE handle_int
165 NESTED(handle_int, PT_SIZE, sp)
166 #ifdef CONFIG_TRACE_IRQFLAGS
168 * Check to see if the interrupted code has just disabled
169 * interrupts and ignore this interrupt for now if so.
171 * local_irq_disable() disables interrupts and then calls
172 * trace_hardirqs_off() to track the state. If an interrupt is taken
173 * after interrupts are disabled but before the state is updated
174 * it will appear to restore_all that it is incorrectly returning with
175 * interrupts disabled
180 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
201 LONG_L s0, TI_REGS($28)
202 LONG_S sp, TI_REGS($28)
203 PTR_LA ra, ret_from_irq
210 * Special interrupt vector for MIPS64 ISA & embedded MIPS processors.
211 * This is a dedicated interrupt exception vector which reduces the
212 * interrupt processing overhead. The jump instruction will be replaced
213 * at the initialization time.
215 * Be careful when changing this, it has to be at most 128 bytes
216 * to fit into space reserved for the exception handler.
218 NESTED(except_vec4, 0, sp)
219 1: j 1b /* Dummy, will be replaced */
223 * EJTAG debug exception handler.
224 * The EJTAG debug exception entry point is 0xbfc00480, which
225 * normally is in the boot PROM, so the boot PROM must do a
226 * unconditional jump to this vector.
228 NESTED(except_vec_ejtag_debug, 0, sp)
229 j ejtag_debug_handler
230 END(except_vec_ejtag_debug)
235 * Vectored interrupt handler.
236 * This prototype is copied to ebase + n*IntCtl.VS and patched
237 * to invoke the handler
239 BUILD_ROLLBACK_PROLOGUE except_vec_vi
240 NESTED(except_vec_vi, 0, sp)
245 #ifdef CONFIG_MIPS_MT_SMTC
247 * To keep from blindly blocking *all* interrupts
248 * during service by SMTC kernel, we also want to
249 * pass the IM value to be cleared.
251 FEXPORT(except_vec_vi_mori)
253 #endif /* CONFIG_MIPS_MT_SMTC */
254 FEXPORT(except_vec_vi_lui)
255 lui v0, 0 /* Patched */
256 j except_vec_vi_handler
257 FEXPORT(except_vec_vi_ori)
258 ori v0, 0 /* Patched */
261 EXPORT(except_vec_vi_end)
264 * Common Vectored Interrupt code
265 * Complete the register saves and invoke the handler which is passed in $v0
267 NESTED(except_vec_vi_handler, 0, sp)
270 #ifdef CONFIG_MIPS_MT_SMTC
272 * SMTC has an interesting problem that interrupts are level-triggered,
273 * and the CLI macro will clear EXL, potentially causing a duplicate
274 * interrupt service invocation. So we need to clear the associated
275 * IM bit of Status prior to doing CLI, and restore it after the
276 * service routine has been invoked - we must assume that the
277 * service routine will have cleared the state, and any active
278 * level represents a new or otherwised unserviced event...
282 #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
283 mfc0 t2, CP0_TCCONTEXT
285 mtc0 t2, CP0_TCCONTEXT
286 #endif /* CONFIG_MIPS_MT_SMTC_IM_BACKSTOP */
290 #endif /* CONFIG_MIPS_MT_SMTC */
292 #ifdef CONFIG_TRACE_IRQFLAGS
294 #ifdef CONFIG_MIPS_MT_SMTC
298 #ifdef CONFIG_MIPS_MT_SMTC
304 LONG_L s0, TI_REGS($28)
305 LONG_S sp, TI_REGS($28)
306 PTR_LA ra, ret_from_irq
308 END(except_vec_vi_handler)
311 * EJTAG debug exception handler.
313 NESTED(ejtag_debug_handler, PT_SIZE, sp)
319 sll k0, k0, 30 # Check for SDBBP.
320 bgez k0, ejtag_return
322 PTR_LA k0, ejtag_debug_buffer
326 jal ejtag_exception_handler
328 PTR_LA k0, ejtag_debug_buffer
336 END(ejtag_debug_handler)
339 * This buffer is reserved for the use of the EJTAG debug
343 EXPORT(ejtag_debug_buffer)
350 * NMI debug exception handler for MIPS reference boards.
351 * The NMI debug exception entry point is 0xbfc00000, which
352 * normally is in the boot PROM, so the boot PROM must do a
353 * unconditional jump to this vector.
355 NESTED(except_vec_nmi, 0, sp)
361 NESTED(nmi_handler, PT_SIZE, sp)
366 jal nmi_exception_handler
373 .macro __build_clear_none
376 .macro __build_clear_sti
381 .macro __build_clear_cli
386 .macro __build_clear_fpe
388 /* gas fails to assemble cfc1 for some archs (octeon).*/ \
399 .macro __build_clear_ade
400 MFC0 t0, CP0_BADVADDR
401 PTR_S t0, PT_BVADDR(sp)
405 .macro __BUILD_silent exception
408 /* Gas tries to parse the PRINT argument as a string containing
409 string escapes and emits bogus warnings if it believes to
410 recognize an unknown escape code. So make the arguments
411 start with an n and gas will believe \n is ok ... */
412 .macro __BUILD_verbose nexception
413 LONG_L a1, PT_EPC(sp)
415 PRINT("Got \nexception at %08lx\012")
418 PRINT("Got \nexception at %016lx\012")
422 .macro __BUILD_count exception
423 LONG_L t0,exception_count_\exception
425 LONG_S t0,exception_count_\exception
426 .comm exception_count\exception, 8, 8
429 .macro __BUILD_HANDLER exception handler clear verbose ext
431 NESTED(handle_\exception, PT_SIZE, sp)
434 FEXPORT(handle_\exception\ext)
437 __BUILD_\verbose \exception
439 PTR_LA ra, ret_from_exception
441 END(handle_\exception)
444 .macro BUILD_HANDLER exception handler clear verbose
445 __BUILD_HANDLER \exception \handler \clear \verbose _int
448 BUILD_HANDLER adel ade ade silent /* #4 */
449 BUILD_HANDLER ades ade ade silent /* #5 */
450 BUILD_HANDLER ibe be cli silent /* #6 */
451 BUILD_HANDLER dbe be cli silent /* #7 */
452 BUILD_HANDLER bp bp sti silent /* #9 */
453 BUILD_HANDLER ri ri sti silent /* #10 */
454 BUILD_HANDLER cpu cpu sti silent /* #11 */
455 BUILD_HANDLER ov ov sti silent /* #12 */
456 BUILD_HANDLER tr tr sti silent /* #13 */
457 BUILD_HANDLER fpe fpe fpe silent /* #15 */
458 BUILD_HANDLER mdmx mdmx sti silent /* #22 */
459 #ifdef CONFIG_HARDWARE_WATCHPOINTS
461 * For watch, interrupts will be enabled after the watch
462 * registers are read.
464 BUILD_HANDLER watch watch cli silent /* #23 */
466 BUILD_HANDLER watch watch sti verbose /* #23 */
468 BUILD_HANDLER mcheck mcheck cli verbose /* #24 */
469 BUILD_HANDLER mt mt sti silent /* #25 */
470 BUILD_HANDLER dsp dsp sti silent /* #26 */
471 BUILD_HANDLER reserved reserved sti verbose /* others */
474 LEAF(handle_ri_rdhwr_vivt)
475 #ifdef CONFIG_MIPS_MT_SMTC
476 PANIC_PIC("handle_ri_rdhwr_vivt called")
481 /* check if TLB contains a entry for EPC */
483 andi k1, 0xff /* ASID_MASK */
485 PTR_SRL k0, _PAGE_SHIFT + 1
486 PTR_SLL k0, _PAGE_SHIFT + 1
494 bltz k1, handle_ri /* slow path */
497 END(handle_ri_rdhwr_vivt)
499 LEAF(handle_ri_rdhwr)
503 /* 0x7c03e83b: rdhwr v1,$29 */
509 bne k0, k1, handle_ri /* if not ours */
510 /* The insn is rdhwr. No need to check CAUSE.BD here. */
511 get_saved_sp /* k1 := current_thread_info */
514 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
516 xori k1, _THREAD_MASK
517 LONG_L v1, TI_TP_VALUE(k1)
522 #ifndef CONFIG_CPU_DADDI_WORKAROUNDS
523 LONG_ADDIU k0, 4 /* stall on $k0 */
530 /* I hope three instructions between MTC0 and ERET are enough... */
532 xori k1, _THREAD_MASK
533 LONG_L v1, TI_TP_VALUE(k1)
542 /* A temporary overflow handler used by check_daddi(). */
546 BUILD_HANDLER daddi_ov daddi_ov none silent /* #12 */