3 #include <linux/bitmap.h>
4 #include <linux/init.h>
10 #include <asm/gcmpregs.h>
11 #include <linux/hardirq.h>
12 #include <asm-generic/bitops/find.h>
15 static unsigned long _gic_base;
16 static unsigned int _irqbase;
17 static unsigned int gic_irq_flags[GIC_NUM_INTRS];
18 #define GIC_IRQ_FLAG_EDGE 0x0001
20 struct gic_pcpu_mask pcpu_masks[NR_CPUS];
21 static struct gic_pending_regs pending_regs[NR_CPUS];
22 static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
24 void gic_send_ipi(unsigned int intr)
26 pr_debug("CPU%d: %s status %08x\n", smp_processor_id(), __func__,
28 GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr);
31 /* This is Malta specific and needs to be exported */
32 static void __init vpe_local_setup(unsigned int numvpes)
35 unsigned long timer_interrupt = 5, perf_interrupt = 5;
39 * Setup the default performance counter timer interrupts
42 for (i = 0; i < numvpes; i++) {
43 GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
45 /* Are Interrupts locally routable? */
46 GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_CTL), vpe_ctl);
47 if (vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK)
48 GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
49 GIC_MAP_TO_PIN_MSK | timer_interrupt);
51 if (vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK)
52 GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
53 GIC_MAP_TO_PIN_MSK | perf_interrupt);
57 unsigned int gic_get_int(void)
60 unsigned long *pending, *intrmask, *pcpu_mask;
61 unsigned long *pending_abs, *intrmask_abs;
63 /* Get per-cpu bitmaps */
64 pending = pending_regs[smp_processor_id()].pending;
65 intrmask = intrmask_regs[smp_processor_id()].intrmask;
66 pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;
68 pending_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
69 GIC_SH_PEND_31_0_OFS);
70 intrmask_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
71 GIC_SH_MASK_31_0_OFS);
73 for (i = 0; i < BITS_TO_LONGS(GIC_NUM_INTRS); i++) {
74 GICREAD(*pending_abs, pending[i]);
75 GICREAD(*intrmask_abs, intrmask[i]);
80 bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS);
81 bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS);
83 i = find_first_bit(pending, GIC_NUM_INTRS);
85 pr_debug("CPU%d: %s pend=%d\n", smp_processor_id(), __func__, i);
90 static unsigned int gic_irq_startup(unsigned int irq)
93 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
94 GIC_SET_INTR_MASK(irq);
98 static void gic_irq_ack(unsigned int irq)
101 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
102 GIC_CLR_INTR_MASK(irq);
104 if (gic_irq_flags[irq] & GIC_IRQ_FLAG_EDGE)
105 GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
108 static void gic_mask_irq(unsigned int irq)
111 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
112 GIC_CLR_INTR_MASK(irq);
115 static void gic_unmask_irq(unsigned int irq)
118 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
119 GIC_SET_INTR_MASK(irq);
124 static DEFINE_SPINLOCK(gic_lock);
126 static int gic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
128 cpumask_t tmp = CPU_MASK_NONE;
133 pr_debug("%s(%d) called\n", __func__, irq);
134 cpumask_and(&tmp, cpumask, cpu_online_mask);
138 /* Assumption : cpumask refers to a single CPU */
139 spin_lock_irqsave(&gic_lock, flags);
141 /* Re-route this IRQ */
142 GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
144 /* Update the pcpu_masks */
145 for (i = 0; i < NR_CPUS; i++)
146 clear_bit(irq, pcpu_masks[i].pcpu_mask);
147 set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);
150 cpumask_copy(irq_desc[irq].affinity, cpumask);
151 spin_unlock_irqrestore(&gic_lock, flags);
157 static struct irq_chip gic_irq_controller = {
159 .startup = gic_irq_startup,
161 .mask = gic_mask_irq,
162 .mask_ack = gic_mask_irq,
163 .unmask = gic_unmask_irq,
164 .eoi = gic_unmask_irq,
166 .set_affinity = gic_set_affinity,
170 static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
171 unsigned int pin, unsigned int polarity, unsigned int trigtype,
174 /* Setup Intr to Pin mapping */
175 if (pin & GIC_MAP_TO_NMI_MSK) {
176 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
177 /* FIXME: hack to route NMI to all cpu's */
178 for (cpu = 0; cpu < NR_CPUS; cpu += 32) {
179 GICWRITE(GIC_REG_ADDR(SHARED,
180 GIC_SH_MAP_TO_VPE_REG_OFF(intr, cpu)),
184 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)),
185 GIC_MAP_TO_PIN_MSK | pin);
186 /* Setup Intr to CPU mapping */
187 GIC_SH_MAP_TO_VPE_SMASK(intr, cpu);
190 /* Setup Intr Polarity */
191 GIC_SET_POLARITY(intr, polarity);
193 /* Setup Intr Trigger Type */
194 GIC_SET_TRIGGER(intr, trigtype);
196 /* Init Intr Masks */
197 GIC_CLR_INTR_MASK(intr);
198 /* Initialise per-cpu Interrupt software masks */
199 if (flags & GIC_FLAG_IPI)
200 set_bit(intr, pcpu_masks[cpu].pcpu_mask);
201 if (flags & GIC_FLAG_TRANSPARENT)
202 GIC_SET_INTR_MASK(intr);
203 if (trigtype == GIC_TRIG_EDGE)
204 gic_irq_flags[intr] |= GIC_IRQ_FLAG_EDGE;
207 static void __init gic_basic_init(int numintrs, int numvpes,
208 struct gic_intr_map *intrmap, int mapsize)
213 for (i = 0; i < numintrs; i++) {
214 GIC_SET_POLARITY(i, GIC_POL_POS);
215 GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
216 GIC_CLR_INTR_MASK(i);
217 if (i < GIC_NUM_INTRS)
218 gic_irq_flags[i] = 0;
221 /* Setup specifics */
222 for (i = 0; i < mapsize; i++) {
223 cpu = intrmap[i].cpunum;
224 if (cpu == GIC_UNUSED)
226 if (cpu == 0 && i != 0 && intrmap[i].flags == 0)
236 vpe_local_setup(numvpes);
238 for (i = _irqbase; i < (_irqbase + numintrs); i++)
239 set_irq_chip(i, &gic_irq_controller);
242 void __init gic_init(unsigned long gic_base_addr,
243 unsigned long gic_addrspace_size,
244 struct gic_intr_map *intr_map, unsigned int intr_map_size,
245 unsigned int irqbase)
247 unsigned int gicconfig;
248 int numvpes, numintrs;
250 _gic_base = (unsigned long) ioremap_nocache(gic_base_addr,
254 GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
255 numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
256 GIC_SH_CONFIG_NUMINTRS_SHF;
257 numintrs = ((numintrs + 1) * 8);
259 numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
260 GIC_SH_CONFIG_NUMVPES_SHF;
262 pr_debug("%s called\n", __func__);
264 gic_basic_init(numintrs, numvpes, intr_map, intr_map_size);