arch/mips/kernel/irq-gic.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
   7  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
   8  */
   9 #include <linux/bitmap.h>
  10 #include <linux/init.h>
  11 #include <linux/smp.h>
  12 #include <linux/irq.h>
  13 #include <linux/clocksource.h>
  14
  15 #include <asm/io.h>
  16 #include <asm/gic.h>
  17 #include <asm/setup.h>
  18 #include <asm/traps.h>
  19 #include <linux/hardirq.h>
  20 #include <asm-generic/bitops/find.h>
  21
  22 unsigned int gic_frequency;
  23 unsigned int gic_present;
  24 unsigned long _gic_base;
  25 unsigned int gic_irq_base;
  26 unsigned int gic_irq_flags[GIC_NUM_INTRS];
  27
  28 /* The index into this array is the vector # of the interrupt. */
  29 struct gic_shared_intr_map gic_shared_intr_map[GIC_NUM_INTRS];
  30
  31 static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
  32 static struct gic_pending_regs pending_regs[NR_CPUS];
  33 static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
  34
  35 #if defined(CONFIG_CSRC_GIC) || defined(CONFIG_CEVT_GIC)
  36 cycle_t gic_read_count(void)
  37 {
  38         unsigned int hi, hi2, lo;
  39
  40         do {
  41                 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi);
  42                 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), lo);
  43                 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi2);
  44         } while (hi2 != hi);
  45
  46         return (((cycle_t) hi) << 32) + lo;
  47 }
  48
  49 void gic_write_compare(cycle_t cnt)
  50 {
  51         GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI),
  52                                 (int)(cnt >> 32));
  53         GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO),
  54                                 (int)(cnt & 0xffffffff));
  55 }
  56
  57 cycle_t gic_read_compare(void)
  58 {
  59         unsigned int hi, lo;
  60
  61         GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI), hi);
  62         GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO), lo);
  63
  64         return (((cycle_t) hi) << 32) + lo;
  65 }
  66 #endif
  67
  68 unsigned int gic_get_timer_pending(void)
  69 {
  70         unsigned int vpe_pending;
  71
  72         GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), 0);
  73         GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_PEND), vpe_pending);
  74         return (vpe_pending & GIC_VPE_PEND_TIMER_MSK);
  75 }
  76
  77 void gic_bind_eic_interrupt(int irq, int set)
  78 {
  79         /* Convert irq vector # to hw int # */
  80         irq -= GIC_PIN_TO_VEC_OFFSET;
  81
  82         /* Set irq to use shadow set */
  83         GICWRITE(GIC_REG_ADDR(VPE_LOCAL, GIC_VPE_EIC_SS(irq)), set);
  84 }
  85
  86 void gic_send_ipi(unsigned int intr)
  87 {
  88         GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr);
  89 }
  90
  91 static void gic_eic_irq_dispatch(void)
  92 {
  93         unsigned int cause = read_c0_cause();
  94         int irq;
  95
  96         irq = (cause & ST0_IM) >> STATUSB_IP2;
  97         if (irq == 0)
  98                 irq = -1;
  99
 100         if (irq >= 0)
 101                 do_IRQ(gic_irq_base + irq);
 102         else
 103                 spurious_interrupt();
 104 }
 105
 106 static void __init vpe_local_setup(unsigned int numvpes)
 107 {
 108         unsigned long timer_intr = GIC_INT_TMR;
 109         unsigned long perf_intr = GIC_INT_PERFCTR;
 110         unsigned int vpe_ctl;
 111         int i;
 112
 113         if (cpu_has_veic) {
 114                 /*
 115                  * GIC timer interrupt -> CPU HW Int X (vector X+2) ->
 116                  * map to pin X+2-1 (since GIC adds 1)
 117                  */
 118                 timer_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
 119                 /*
 120                  * GIC perfcnt interrupt -> CPU HW Int X (vector X+2) ->
 121                  * map to pin X+2-1 (since GIC adds 1)
 122                  */
 123                 perf_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
 124         }
 125
 126         /*
 127          * Setup the default performance counter timer interrupts
 128          * for all VPEs
 129          */
 130         for (i = 0; i < numvpes; i++) {
 131                 GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
 132
 133                 /* Are Interrupts locally routable? */
 134                 GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_CTL), vpe_ctl);
 135                 if (vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK)
 136                         GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
 137                                  GIC_MAP_TO_PIN_MSK | timer_intr);
 138                 if (cpu_has_veic) {
 139                         set_vi_handler(timer_intr + GIC_PIN_TO_VEC_OFFSET,
 140                                 gic_eic_irq_dispatch);
 141                         gic_shared_intr_map[timer_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_TIMER_MSK;
 142                 }
 143
 144                 if (vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK)
 145                         GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
 146                                  GIC_MAP_TO_PIN_MSK | perf_intr);
 147                 if (cpu_has_veic) {
 148                         set_vi_handler(perf_intr + GIC_PIN_TO_VEC_OFFSET, gic_eic_irq_dispatch);
 149                         gic_shared_intr_map[perf_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_PERFCNT_MSK;
 150                 }
 151         }
 152 }
 153
 154 unsigned int gic_compare_int(void)
 155 {
 156         unsigned int pending;
 157
 158         GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_PEND), pending);
 159         if (pending & GIC_VPE_PEND_CMP_MSK)
 160                 return 1;
 161         else
 162                 return 0;
 163 }
 164
 165 unsigned int gic_get_int(void)
 166 {
 167         unsigned int i;
 168         unsigned long *pending, *intrmask, *pcpu_mask;
 169         unsigned long *pending_abs, *intrmask_abs;
 170
 171         /* Get per-cpu bitmaps */
 172         pending = pending_regs[smp_processor_id()].pending;
 173         intrmask = intrmask_regs[smp_processor_id()].intrmask;
 174         pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;
 175
 176         pending_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
 177                                                          GIC_SH_PEND_31_0_OFS);
 178         intrmask_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
 179                                                           GIC_SH_MASK_31_0_OFS);
 180
 181         for (i = 0; i < BITS_TO_LONGS(GIC_NUM_INTRS); i++) {
 182                 GICREAD(*pending_abs, pending[i]);
 183                 GICREAD(*intrmask_abs, intrmask[i]);
 184                 pending_abs++;
 185                 intrmask_abs++;
 186         }
 187
 188         bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS);
 189         bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS);
 190
 191         return find_first_bit(pending, GIC_NUM_INTRS);
 192 }
 193
 194 static void gic_mask_irq(struct irq_data *d)
 195 {
 196         GIC_CLR_INTR_MASK(d->irq - gic_irq_base);
 197 }
 198
 199 static void gic_unmask_irq(struct irq_data *d)
 200 {
 201         GIC_SET_INTR_MASK(d->irq - gic_irq_base);
 202 }
 203
 204 #ifdef CONFIG_SMP
 205 static DEFINE_SPINLOCK(gic_lock);
 206
 207 static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
 208                             bool force)
 209 {
 210         unsigned int irq = (d->irq - gic_irq_base);
 211         cpumask_t       tmp = CPU_MASK_NONE;
 212         unsigned long   flags;
 213         int             i;
 214
 215         cpumask_and(&tmp, cpumask, cpu_online_mask);
 216         if (cpus_empty(tmp))
 217                 return -1;
 218
 219         /* Assumption : cpumask refers to a single CPU */
 220         spin_lock_irqsave(&gic_lock, flags);
 221
 222         /* Re-route this IRQ */
 223         GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
 224
 225         /* Update the pcpu_masks */
 226         for (i = 0; i < NR_CPUS; i++)
 227                 clear_bit(irq, pcpu_masks[i].pcpu_mask);
 228         set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);
 229
 230         cpumask_copy(d->affinity, cpumask);
 231         spin_unlock_irqrestore(&gic_lock, flags);
 232
 233         return IRQ_SET_MASK_OK_NOCOPY;
 234 }
 235 #endif
 236
 237 static struct irq_chip gic_irq_controller = {
 238         .name                   =       "MIPS GIC",
 239         .irq_ack                =       gic_irq_ack,
 240         .irq_mask               =       gic_mask_irq,
 241         .irq_mask_ack           =       gic_mask_irq,
 242         .irq_unmask             =       gic_unmask_irq,
 243         .irq_eoi                =       gic_finish_irq,
 244 #ifdef CONFIG_SMP
 245         .irq_set_affinity       =       gic_set_affinity,
 246 #endif
 247 };
 248
 249 static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
 250         unsigned int pin, unsigned int polarity, unsigned int trigtype,
 251         unsigned int flags)
 252 {
 253         struct gic_shared_intr_map *map_ptr;
 254
 255         /* Setup Intr to Pin mapping */
 256         if (pin & GIC_MAP_TO_NMI_MSK) {
 257                 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
 258                 /* FIXME: hack to route NMI to all cpu's */
 259                 for (cpu = 0; cpu < NR_CPUS; cpu += 32) {
 260                         GICWRITE(GIC_REG_ADDR(SHARED,
 261                                           GIC_SH_MAP_TO_VPE_REG_OFF(intr, cpu)),
 262                                  0xffffffff);
 263                 }
 264         } else {
 265                 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)),
 266                          GIC_MAP_TO_PIN_MSK | pin);
 267                 /* Setup Intr to CPU mapping */
 268                 GIC_SH_MAP_TO_VPE_SMASK(intr, cpu);
 269                 if (cpu_has_veic) {
 270                         set_vi_handler(pin + GIC_PIN_TO_VEC_OFFSET,
 271                                 gic_eic_irq_dispatch);
 272                         map_ptr = &gic_shared_intr_map[pin + GIC_PIN_TO_VEC_OFFSET];
 273                         if (map_ptr->num_shared_intr >= GIC_MAX_SHARED_INTR)
 274                                 BUG();
 275                         map_ptr->intr_list[map_ptr->num_shared_intr++] = intr;
 276                 }
 277         }
 278
 279         /* Setup Intr Polarity */
 280         GIC_SET_POLARITY(intr, polarity);
 281
 282         /* Setup Intr Trigger Type */
 283         GIC_SET_TRIGGER(intr, trigtype);
 284
 285         /* Init Intr Masks */
 286         GIC_CLR_INTR_MASK(intr);
 287         /* Initialise per-cpu Interrupt software masks */
 288         if (flags & GIC_FLAG_IPI)
 289                 set_bit(intr, pcpu_masks[cpu].pcpu_mask);
 290         if ((flags & GIC_FLAG_TRANSPARENT) && (cpu_has_veic == 0))
 291                 GIC_SET_INTR_MASK(intr);
 292         if (trigtype == GIC_TRIG_EDGE)
 293                 gic_irq_flags[intr] |= GIC_TRIG_EDGE;
 294 }
 295
 296 static void __init gic_basic_init(int numintrs, int numvpes,
 297                         struct gic_intr_map *intrmap, int mapsize)
 298 {
 299         unsigned int i, cpu;
 300         unsigned int pin_offset = 0;
 301
 302         board_bind_eic_interrupt = &gic_bind_eic_interrupt;
 303
 304         /* Setup defaults */
 305         for (i = 0; i < numintrs; i++) {
 306                 GIC_SET_POLARITY(i, GIC_POL_POS);
 307                 GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
 308                 GIC_CLR_INTR_MASK(i);
 309                 if (i < GIC_NUM_INTRS) {
 310                         gic_irq_flags[i] = 0;
 311                         gic_shared_intr_map[i].num_shared_intr = 0;
 312                         gic_shared_intr_map[i].local_intr_mask = 0;
 313                 }
 314         }
 315
 316         /*
 317          * In EIC mode, the HW_INT# is offset by (2-1). Need to subtract
 318          * one because the GIC will add one (since 0=no intr).
 319          */
 320         if (cpu_has_veic)
 321                 pin_offset = (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
 322
 323         /* Setup specifics */
 324         for (i = 0; i < mapsize; i++) {
 325                 cpu = intrmap[i].cpunum;
 326                 if (cpu == GIC_UNUSED)
 327                         continue;
 328                 if (cpu == 0 && i != 0 && intrmap[i].flags == 0)
 329                         continue;
 330                 gic_setup_intr(i,
 331                         intrmap[i].cpunum,
 332                         intrmap[i].pin + pin_offset,
 333                         intrmap[i].polarity,
 334                         intrmap[i].trigtype,
 335                         intrmap[i].flags);
 336         }
 337
 338         vpe_local_setup(numvpes);
 339 }
 340
 341 void __init gic_init(unsigned long gic_base_addr,
 342                      unsigned long gic_addrspace_size,
 343                      struct gic_intr_map *intr_map, unsigned int intr_map_size,
 344                      unsigned int irqbase)
 345 {
 346         unsigned int gicconfig;
 347         int numvpes, numintrs;
 348
 349         _gic_base = (unsigned long) ioremap_nocache(gic_base_addr,
 350                                                     gic_addrspace_size);
 351         gic_irq_base = irqbase;
 352
 353         GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
 354         numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
 355                    GIC_SH_CONFIG_NUMINTRS_SHF;
 356         numintrs = ((numintrs + 1) * 8);
 357
 358         numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
 359                   GIC_SH_CONFIG_NUMVPES_SHF;
 360         numvpes = numvpes + 1;
 361
 362         gic_basic_init(numintrs, numvpes, intr_map, intr_map_size);
 363
 364         gic_platform_init(numintrs, &gic_irq_controller);
 365 }