2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
7 * Copyright (c) 2004 MIPS Inc
8 * Author: chris@mips.com
10 * Copyright (C) 2004, 06 Ralf Baechle <ralf@linux-mips.org>
12 #include <linux/module.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/sched.h>
16 #include <linux/kernel_stat.h>
19 #include <asm/msc01_ic.h>
20 #include <asm/traps.h>
22 static unsigned long _icctrl_msc;
23 #define MSC01_IC_REG_BASE _icctrl_msc
25 #define MSCIC_WRITE(reg, data) do { *(volatile u32 *)(reg) = data; } while (0)
26 #define MSCIC_READ(reg, data) do { data = *(volatile u32 *)(reg); } while (0)
28 static unsigned int irq_base;
30 /* mask off an interrupt */
31 static inline void mask_msc_irq(struct irq_data *d)
33 unsigned int irq = d->irq;
35 if (irq < (irq_base + 32))
36 MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base));
38 MSCIC_WRITE(MSC01_IC_DISH, 1<<(irq - irq_base - 32));
41 /* unmask an interrupt */
42 static inline void unmask_msc_irq(struct irq_data *d)
44 unsigned int irq = d->irq;
46 if (irq < (irq_base + 32))
47 MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base));
49 MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32));
53 * Masks and ACKs an IRQ
55 static void level_mask_and_ack_msc_irq(struct irq_data *d)
57 unsigned int irq = d->irq;
61 MSCIC_WRITE(MSC01_IC_EOI, 0);
62 /* This actually needs to be a call into platform code */
67 * Masks and ACKs an IRQ
69 static void edge_mask_and_ack_msc_irq(struct irq_data *d)
71 unsigned int irq = d->irq;
75 MSCIC_WRITE(MSC01_IC_EOI, 0);
78 MSCIC_READ(MSC01_IC_SUP+irq*8, r);
79 MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT);
80 MSCIC_WRITE(MSC01_IC_SUP+irq*8, r);
86 * Interrupt handler for interrupts coming from SOC-it.
92 /* read the interrupt vector register */
93 MSCIC_READ(MSC01_IC_VEC, irq);
95 do_IRQ(irq + irq_base);
97 /* Ignore spurious interrupt */
101 static void msc_bind_eic_interrupt(int irq, int set)
103 MSCIC_WRITE(MSC01_IC_RAMW,
104 (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF));
107 static struct irq_chip msc_levelirq_type = {
108 .name = "SOC-it-Level",
109 .irq_ack = level_mask_and_ack_msc_irq,
110 .irq_mask = mask_msc_irq,
111 .irq_mask_ack = level_mask_and_ack_msc_irq,
112 .irq_unmask = unmask_msc_irq,
113 .irq_eoi = unmask_msc_irq,
116 static struct irq_chip msc_edgeirq_type = {
117 .name = "SOC-it-Edge",
118 .irq_ack = edge_mask_and_ack_msc_irq,
119 .irq_mask = mask_msc_irq,
120 .irq_mask_ack = edge_mask_and_ack_msc_irq,
121 .irq_unmask = unmask_msc_irq,
122 .irq_eoi = unmask_msc_irq,
126 void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq)
128 _icctrl_msc = (unsigned long) ioremap(icubase, 0x40000);
130 /* Reset interrupt controller - initialises all registers to 0 */
131 MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);
133 board_bind_eic_interrupt = &msc_bind_eic_interrupt;
135 for (; nirq >= 0; nirq--, imp++) {
138 switch (imp->im_type) {
140 irq_set_chip_and_handler_name(irqbase + n,
145 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
147 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
149 case MSC01_IRQ_LEVEL:
150 irq_set_chip_and_handler_name(irqbase + n,
155 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
157 MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl);
163 MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */