2 * General MIPS MT support routines, usable in AP/SP, SMVP, or SMTC kernels
3 * Copyright (C) 2005 Mips Technologies, Inc
6 #include <linux/device.h>
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
9 #include <linux/cpumask.h>
10 #include <linux/module.h>
11 #include <linux/interrupt.h>
12 #include <linux/security.h>
15 #include <asm/processor.h>
16 #include <asm/atomic.h>
17 #include <asm/system.h>
18 #include <asm/hardirq.h>
19 #include <asm/mmu_context.h>
21 #include <asm/mipsmtregs.h>
22 #include <asm/r4kcache.h>
23 #include <asm/cacheflush.h>
26 * CPU mask used to set process affinity for MT VPEs/TCs with FPUs
29 cpumask_t mt_fpu_cpumask;
31 #ifdef CONFIG_MIPS_MT_FPAFF
33 #include <linux/cpu.h>
34 #include <linux/delay.h>
35 #include <asm/uaccess.h>
37 unsigned long mt_fpemul_threshold = 0;
40 * Replacement functions for the sys_sched_setaffinity() and
41 * sys_sched_getaffinity() system calls, so that we can integrate
42 * FPU affinity with the user's requested processor affinity.
43 * This code is 98% identical with the sys_sched_setaffinity()
44 * and sys_sched_getaffinity() system calls, and should be
45 * updated when kernel/sched.c changes.
49 * find_process_by_pid - find a process with a matching PID value.
50 * used in sys_sched_set/getaffinity() in kernel/sched.c, so
53 static inline struct task_struct *find_process_by_pid(pid_t pid)
55 return pid ? find_task_by_pid(pid) : current;
60 * mipsmt_sys_sched_setaffinity - set the cpu affinity of a process
62 asmlinkage long mipsmt_sys_sched_setaffinity(pid_t pid, unsigned int len,
63 unsigned long __user *user_mask_ptr)
66 cpumask_t effective_mask;
68 struct task_struct *p;
70 if (len < sizeof(new_mask))
73 if (copy_from_user(&new_mask, user_mask_ptr, sizeof(new_mask)))
77 read_lock(&tasklist_lock);
79 p = find_process_by_pid(pid);
81 read_unlock(&tasklist_lock);
87 * It is not safe to call set_cpus_allowed with the
88 * tasklist_lock held. We will bump the task_struct's
89 * usage count and drop tasklist_lock before invoking
95 if ((current->euid != p->euid) && (current->euid != p->uid) &&
96 !capable(CAP_SYS_NICE)) {
97 read_unlock(&tasklist_lock);
101 retval = security_task_setscheduler(p, 0, NULL);
105 /* Record new user-specified CPU set for future reference */
106 p->thread.user_cpus_allowed = new_mask;
108 /* Unlock the task list */
109 read_unlock(&tasklist_lock);
111 /* Compute new global allowed CPU set if necessary */
112 if ((p->thread.mflags & MF_FPUBOUND)
113 && cpus_intersects(new_mask, mt_fpu_cpumask)) {
114 cpus_and(effective_mask, new_mask, mt_fpu_cpumask);
115 retval = set_cpus_allowed(p, effective_mask);
117 p->thread.mflags &= ~MF_FPUBOUND;
118 retval = set_cpus_allowed(p, new_mask);
124 unlock_cpu_hotplug();
129 * mipsmt_sys_sched_getaffinity - get the cpu affinity of a process
131 asmlinkage long mipsmt_sys_sched_getaffinity(pid_t pid, unsigned int len,
132 unsigned long __user *user_mask_ptr)
134 unsigned int real_len;
137 struct task_struct *p;
139 real_len = sizeof(mask);
144 read_lock(&tasklist_lock);
147 p = find_process_by_pid(pid);
150 retval = security_task_getscheduler(p);
154 cpus_and(mask, p->thread.user_cpus_allowed, cpu_possible_map);
157 read_unlock(&tasklist_lock);
158 unlock_cpu_hotplug();
161 if (copy_to_user(user_mask_ptr, &mask, real_len))
166 #endif /* CONFIG_MIPS_MT_FPAFF */
169 * Dump new MIPS MT state for the core. Does not leave TCs halted.
170 * Takes an argument which taken to be a pre-call MVPControl value.
173 void mips_mt_regdump(unsigned long mvpctl)
176 unsigned long vpflags;
177 unsigned long mvpconf0;
182 unsigned long haltval;
183 unsigned long tcstatval;
184 #ifdef CONFIG_MIPS_MT_SMTC
185 void smtc_soft_dump(void);
186 #endif /* CONFIG_MIPT_MT_SMTC */
188 local_irq_save(flags);
190 printk("=== MIPS MT State Dump ===\n");
191 printk("-- Global State --\n");
192 printk(" MVPControl Passed: %08lx\n", mvpctl);
193 printk(" MVPControl Read: %08lx\n", vpflags);
194 printk(" MVPConf0 : %08lx\n", (mvpconf0 = read_c0_mvpconf0()));
195 nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
196 ntc = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
197 printk("-- per-VPE State --\n");
198 for (i = 0; i < nvpe; i++) {
199 for (tc = 0; tc < ntc; tc++) {
201 if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) {
202 printk(" VPE %d\n", i);
203 printk(" VPEControl : %08lx\n",
204 read_vpe_c0_vpecontrol());
205 printk(" VPEConf0 : %08lx\n",
206 read_vpe_c0_vpeconf0());
207 printk(" VPE%d.Status : %08lx\n",
208 i, read_vpe_c0_status());
209 printk(" VPE%d.EPC : %08lx\n",
210 i, read_vpe_c0_epc());
211 printk(" VPE%d.Cause : %08lx\n",
212 i, read_vpe_c0_cause());
213 printk(" VPE%d.Config7 : %08lx\n",
214 i, read_vpe_c0_config7());
215 break; /* Next VPE */
219 printk("-- per-TC State --\n");
220 for (tc = 0; tc < ntc; tc++) {
222 if (read_tc_c0_tcbind() == read_c0_tcbind()) {
223 /* Are we dumping ourself? */
224 haltval = 0; /* Then we're not halted, and mustn't be */
225 tcstatval = flags; /* And pre-dump TCStatus is flags */
226 printk(" TC %d (current TC with VPE EPC above)\n", tc);
228 haltval = read_tc_c0_tchalt();
229 write_tc_c0_tchalt(1);
230 tcstatval = read_tc_c0_tcstatus();
231 printk(" TC %d\n", tc);
233 printk(" TCStatus : %08lx\n", tcstatval);
234 printk(" TCBind : %08lx\n", read_tc_c0_tcbind());
235 printk(" TCRestart : %08lx\n", read_tc_c0_tcrestart());
236 printk(" TCHalt : %08lx\n", haltval);
237 printk(" TCContext : %08lx\n", read_tc_c0_tccontext());
239 write_tc_c0_tchalt(0);
241 #ifdef CONFIG_MIPS_MT_SMTC
243 #endif /* CONFIG_MIPT_MT_SMTC */
244 printk("===========================\n");
246 local_irq_restore(flags);
249 static int mt_opt_norps = 0;
250 static int mt_opt_rpsctl = -1;
251 static int mt_opt_nblsu = -1;
252 static int mt_opt_forceconfig7 = 0;
253 static int mt_opt_config7 = -1;
255 static int __init rps_disable(char *s)
260 __setup("norps", rps_disable);
262 static int __init rpsctl_set(char *str)
264 get_option(&str, &mt_opt_rpsctl);
267 __setup("rpsctl=", rpsctl_set);
269 static int __init nblsu_set(char *str)
271 get_option(&str, &mt_opt_nblsu);
274 __setup("nblsu=", nblsu_set);
276 static int __init config7_set(char *str)
278 get_option(&str, &mt_opt_config7);
279 mt_opt_forceconfig7 = 1;
282 __setup("config7=", config7_set);
284 /* Experimental cache flush control parameters that should go away some day */
285 int mt_protiflush = 0;
286 int mt_protdflush = 0;
287 int mt_n_iflushes = 1;
288 int mt_n_dflushes = 1;
290 static int __init set_protiflush(char *s)
295 __setup("protiflush", set_protiflush);
297 static int __init set_protdflush(char *s)
302 __setup("protdflush", set_protdflush);
304 static int __init niflush(char *s)
306 get_option(&s, &mt_n_iflushes);
309 __setup("niflush=", niflush);
311 static int __init ndflush(char *s)
313 get_option(&s, &mt_n_dflushes);
316 __setup("ndflush=", ndflush);
317 #ifdef CONFIG_MIPS_MT_FPAFF
318 static int fpaff_threshold = -1;
320 static int __init fpaff_thresh(char *str)
322 get_option(&str, &fpaff_threshold);
326 __setup("fpaff=", fpaff_thresh);
327 #endif /* CONFIG_MIPS_MT_FPAFF */
329 static unsigned int itc_base = 0;
331 static int __init set_itc_base(char *str)
333 get_option(&str, &itc_base);
337 __setup("itcbase=", set_itc_base);
339 void mips_mt_set_cpuoptions(void)
341 unsigned int oconfig7 = read_c0_config7();
342 unsigned int nconfig7 = oconfig7;
345 printk("\"norps\" option deprectated: use \"rpsctl=\"\n");
347 if (mt_opt_rpsctl >= 0) {
348 printk("34K return prediction stack override set to %d.\n",
351 nconfig7 |= (1 << 2);
353 nconfig7 &= ~(1 << 2);
355 if (mt_opt_nblsu >= 0) {
356 printk("34K ALU/LSU sync override set to %d.\n", mt_opt_nblsu);
358 nconfig7 |= (1 << 5);
360 nconfig7 &= ~(1 << 5);
362 if (mt_opt_forceconfig7) {
363 printk("CP0.Config7 forced to 0x%08x.\n", mt_opt_config7);
364 nconfig7 = mt_opt_config7;
366 if (oconfig7 != nconfig7) {
367 __asm__ __volatile("sync");
368 write_c0_config7(nconfig7);
370 printk("Config7: 0x%08x\n", read_c0_config7());
373 /* Report Cache management debug options */
375 printk("I-cache flushes single-threaded\n");
377 printk("D-cache flushes single-threaded\n");
378 if (mt_n_iflushes != 1)
379 printk("I-Cache Flushes Repeated %d times\n", mt_n_iflushes);
380 if (mt_n_dflushes != 1)
381 printk("D-Cache Flushes Repeated %d times\n", mt_n_dflushes);
383 #ifdef CONFIG_MIPS_MT_FPAFF
384 /* FPU Use Factor empirically derived from experiments on 34K */
385 #define FPUSEFACTOR 333
387 if (fpaff_threshold >= 0) {
388 mt_fpemul_threshold = fpaff_threshold;
390 mt_fpemul_threshold =
391 (FPUSEFACTOR * (loops_per_jiffy / (500000 / HZ))) / HZ;
393 printk("FPU Affinity set after %ld emulations\n",
394 mt_fpemul_threshold);
395 #endif /* CONFIG_MIPS_MT_FPAFF */
399 * Configure ITC mapping. This code is very
400 * specific to the 34K core family, which uses
401 * a special mode bit ("ITC") in the ErrCtl
402 * register to enable access to ITC control
403 * registers via cache "tag" operations.
405 unsigned long ectlval;
406 unsigned long itcblkgrn;
408 /* ErrCtl register is known as "ecc" to Linux */
409 ectlval = read_c0_ecc();
410 write_c0_ecc(ectlval | (0x1 << 26));
412 #define INDEX_0 (0x80000000)
413 #define INDEX_8 (0x80000008)
414 /* Read "cache tag" for Dcache pseudo-index 8 */
415 cache_op(Index_Load_Tag_D, INDEX_8);
417 itcblkgrn = read_c0_dtaglo();
418 itcblkgrn &= 0xfffe0000;
419 /* Set for 128 byte pitch of ITC cells */
420 itcblkgrn |= 0x00000c00;
421 /* Stage in Tag register */
422 write_c0_dtaglo(itcblkgrn);
424 /* Write out to ITU with CACHE op */
425 cache_op(Index_Store_Tag_D, INDEX_8);
426 /* Now set base address, and turn ITC on with 0x1 bit */
427 write_c0_dtaglo((itc_base & 0xfffffc00) | 0x1 );
429 /* Write out to ITU with CACHE op */
430 cache_op(Index_Store_Tag_D, INDEX_0);
431 write_c0_ecc(ectlval);
433 printk("Mapped %ld ITC cells starting at 0x%08x\n",
434 ((itcblkgrn & 0x7fe00000) >> 20), itc_base);
439 * Function to protect cache flushes from concurrent execution
440 * depends on MP software model chosen.
443 void mt_cflush_lockdown(void)
445 #ifdef CONFIG_MIPS_MT_SMTC
446 void smtc_cflush_lockdown(void);
448 smtc_cflush_lockdown();
449 #endif /* CONFIG_MIPS_MT_SMTC */
450 /* FILL IN VSMP and AP/SP VERSIONS HERE */
453 void mt_cflush_release(void)
455 #ifdef CONFIG_MIPS_MT_SMTC
456 void smtc_cflush_release(void);
458 smtc_cflush_release();
459 #endif /* CONFIG_MIPS_MT_SMTC */
460 /* FILL IN VSMP and AP/SP VERSIONS HERE */
463 struct class *mt_class;
465 static int __init mt_init(void)
469 mtc = class_create(THIS_MODULE, "mt");
478 subsys_initcall(mt_init);